== Series Details ==
Series: drm/i915/psr: Get pipe id following atomic guidelines
URL : https://patchwork.freedesktop.org/series/53132/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Get pipe id following atomic guidelines
As stated in struct drm_encoder, crtc field should only be used
by non-atomic drivers.
So here caching the pipe id in intel_psr_enable() what is way more
simple and efficient than at every call to
intel_psr_flush()/invalidate() get the
drm.mode_config.connection_mutex lock to safely be able to
On 11/28/2018 10:56 AM, Stéphane Marchesin wrote:
Hi,
Just a drive-by comment, but did you check that this fails gracefully
on platforms which don't enable the ME? For example Chrome OS :)
That is taken care :) HDCP2.2 is attempted only if platform enables the
ME and its required kernel
Op 27-11-18 om 18:34 schreef Daniel Vetter:
> KMS drivers really should all be able to restore their display state
> on resume without fbcon helping out. So make this the default.
>
> Since I'm not entirely foolish, make it only a default, which drivers
> can still override. That way when the
== Series Details ==
Series: drm/i915: Fix TV encoder support (rev5)
URL : https://patchwork.freedesktop.org/series/52378/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10920_full =
== Summary - WARNING ==
Minor unknown changes coming with
Hi,
Just a drive-by comment, but did you check that this fails gracefully
on platforms which don't enable the ME? For example Chrome OS :)
Stéphane
On Tue, Nov 27, 2018 at 2:48 AM Ramalingam C wrote:
>
> Implements the DP adaptation specific HDCP2.2 functions.
>
> These functions perform the
On 11/27/2018 11:07 PM, Daniel Vetter wrote:
On Tue, Nov 27, 2018 at 04:54:15PM +, Bloomfield, Jon wrote:
I'm not formally reviewing this series, but while glancing at it, I noticed
-Original Message-
From: Intel-gfx On Behalf Of
Ramalingam C
Sent: Tuesday, November 27, 2018
== Series Details ==
Series: series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53097/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10918_full
On Tue, 2018-11-27 at 20:44 +0100, Daniel Vetter wrote:
> On Tue, Nov 27, 2018 at 12:48:59PM -0500, Lyude Paul wrote:
> > On Mon, 2018-11-26 at 22:22 +0100, Daniel Vetter wrote:
> > > On Mon, Nov 26, 2018 at 10:04:21PM +0100, Daniel Vetter wrote:
> > > > On Thu, Nov 15, 2018 at 07:50:05PM -0500,
== Series Details ==
Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO
size
URL : https://patchwork.freedesktop.org/series/53096/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10917_full =
== Summary - WARNING ==
Hi Uma,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.20-rc4 next-20181127]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
On Tue, Nov 27, 2018 at 11:35:54AM +, Tvrtko Ursulin wrote:
>
> On 27/11/2018 09:36, Lucas De Marchi wrote:
> > On Tue, Nov 27, 2018 at 10:37:21AM +0200, Jani Nikula wrote:
> > > On Mon, 26 Nov 2018, Rodrigo Vivi wrote:
> > > > On Thu, Nov 22, 2018 at 08:54:30AM +, Tvrtko Ursulin wrote:
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)
URL : https://patchwork.freedesktop.org/series/51878/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10915_full =
== Summary - WARNING ==
Minor unknown
On Tue, Nov 27, 2018 at 10:31:49AM +0200, Jani Nikula wrote:
> On Mon, 26 Nov 2018, Rodrigo Vivi wrote:
> > On Fri, Nov 23, 2018 at 02:42:59PM +0200, Jani Nikula wrote:
> >> On Wed, 21 Nov 2018, Rodrigo Vivi wrote:
> >> > On Tue, Nov 06, 2018 at 01:51:19PM -0800, Lucas De Marchi wrote:
> >> >>
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Manasi Navare
>Sent: Tuesday, November 27, 2018 1:41 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [CI v12 05/23] drm/dsc: Add helpers for DSC picture
>parameter set
== Series Details ==
Series: series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53113/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7a0e6f477712 drm/dsc: Modify DRM
== Series Details ==
Series: series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53113/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/dsc:
== Series Details ==
Series: series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53113/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5212 -> Patchwork_10923 =
==
== Series Details ==
Series: drm/i915/ringbuffer: Clear semaphore sync registers on ring init
URL : https://patchwork.freedesktop.org/series/53112/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5212 -> Patchwork_10922 =
== Summary - SUCCESS ==
No regressions found.
On Tue, Nov 27, 2018 at 4:46 AM Joonas Lahtinen
wrote:
> I think a more abstract property "% of GPU (processing power)" might
> be a more universal approach. One can then implement that through
> subdividing the resources or timeslicing them, depending on the GPU
> topology.
>
> Leasing 1/8th,
For the series:
Acked-by: Ben Skeggs
On Sat, 17 Nov 2018 at 10:21, Lyude Paul wrote:
>
> So we don't ever have to worry about drivers touching drm_dp_mst_port
> structs without verifying them and crashing again.
>
> Lyude Paul (6):
> drm/dp_mst: Add drm_dp_get_payload_info()
> drm/nouveau:
== Series Details ==
Series: drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev2)
URL : https://patchwork.freedesktop.org/series/49669/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5212 -> Patchwork_10921 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: drm/i915/icl: Sanitize DDI port clock gating for DSI ports
URL : https://patchwork.freedesktop.org/series/53093/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10914_full =
== Summary - WARNING ==
Minor unknown changes
On Tue, 2018-11-27 at 15:38 +0200, Ville Syrjälä wrote:
> On Mon, Nov 26, 2018 at 04:37:02PM -0800, José Roberto de Souza
> wrote:
> > i915 yet don't support PSR in Apple panels, so lets keep it
> > disabled
> > while we work on that.
> >
> > Fixes: 598c6cfe0690 (drm/i915/psr: Enable PSR1 on
== Series Details ==
Series: drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev2)
URL : https://patchwork.freedesktop.org/series/49669/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d147afa0255b drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc
From: Anusha Srivatsa
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
From: Anusha Srivatsa
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error
From: Anusha Srivatsa
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
DSC DPCD color depth register advertises its color depth capabilities
by setting each of the bits that corresponding to a specific color
depth. This patch defines those specific color depths and adds
a helper to return an array of color depth capabilities.
v2:
* Simplify the logic (Ville)
From: Anusha Srivatsa
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
On Tue, 2018-11-27 at 22:23 +0100, Daniel Vetter wrote:
> On Fri, Nov 16, 2018 at 07:21:15PM -0500, Lyude Paul wrote:
> > Some hardware (nvidia hardware in particular) needs to be notified of
> > the exact VCPI and payload settings that the topology manager decided on
> > for each mstb port. Since
On Fri, Nov 16, 2018 at 07:21:15PM -0500, Lyude Paul wrote:
> Some hardware (nvidia hardware in particular) needs to be notified of
> the exact VCPI and payload settings that the topology manager decided on
> for each mstb port. Since there isn't currently any way to get this
> information without
Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
Swati Sharma kirjoitti 22.10.2018 klo 8.31:
From: Vidya Srinivas
In this patch, a list for icl specific pixel formats is created
in which Y210, Y212 and Y216 pixel formats are added along with
legacy pixel formats for primary and sprite plane.
v3: since support for planar formats on ICL was
== Series Details ==
Series: Add Colorspace connector property interface (rev4)
URL : https://patchwork.freedesktop.org/series/47132/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10913_full =
== Summary - FAILURE ==
Serious unknown changes coming
I did earlier give R-b for this patch. The patch anyway hasn't changed
as those defines have not changed.
/Juha-Pekka
Swati Sharma kirjoitti 22.10.2018 klo 8.31:
From: Vidya Srinivas
Added needed plane control flag definitions for Y210, Y212 and
Y216 formats.
v3: no change
Signed-off-by:
== Series Details ==
Series: drm/i915: Fix TV encoder support (rev5)
URL : https://patchwork.freedesktop.org/series/52378/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10920 =
== Summary - SUCCESS ==
No regressions found.
External URL:
From: Matt Atwood
According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 0h through Fh, except for DPCD_REV,
MAX_LINK_RATE,
Petri Latvala writes:
> On Mon, Nov 26, 2018 at 12:46:46PM -0800, Eric Anholt wrote:
>> Petri Latvala writes:
>>
>> > On Wed, Nov 14, 2018 at 02:28:32PM -0800, Eric Anholt wrote:
>> >> These are basic non-rendering tests of the UABI.
>> >>
>> >> Signed-off-by: Eric Anholt
>> >> ---
>> >>
Daniel Vetter writes:
> On Mon, Nov 26, 2018 at 04:36:21PM -0800, Eric Anholt wrote:
>> Noralf Trønnes writes:
>> > +static void drm_gem_shmem_vm_close(struct vm_area_struct *vma)
>> > +{
>> > + struct drm_gem_object *obj = vma->vm_private_data;
>> > + struct drm_gem_shmem_object *shmem =
== Series Details ==
Series: drm/i915: Fix TV encoder support (rev5)
URL : https://patchwork.freedesktop.org/series/52378/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/vblank: Allow dynamic per-crtc max_vblank_count
Okay!
Commit: drm/i915:
From: Ville Syrjälä
On i965gm the hardware frame counter does not work when
the TV encoder is active. So let's not try to consult
the hardware frame counter in that case. Instead we'll
fall back to the timestamp based guesstimation method
used on gen2.
Note that the pipe timings generated by
On Tue, Nov 27, 2018 at 12:48:59PM -0500, Lyude Paul wrote:
> On Mon, 2018-11-26 at 22:22 +0100, Daniel Vetter wrote:
> > On Mon, Nov 26, 2018 at 10:04:21PM +0100, Daniel Vetter wrote:
> > > On Thu, Nov 15, 2018 at 07:50:05PM -0500, Lyude Paul wrote:
> > > > There has been a TODO waiting for quite
On Tue, Nov 27, 2018 at 08:20:04PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On i965gm we need to adjust max_vblank_count dynamically
> depending on whether the TV encoder is used or not. To
> that end add a per-crtc max_vblank_count that takes
> precedence over its device wide
On 26/11/2018 06:51, Michal Wajdeczko wrote:
On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio
wrote:
/snip/
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 8382d591c784..1a853cc627e3 100644
---
== Series Details ==
Series: drm/i915: Fix TV encoder support (rev4)
URL : https://patchwork.freedesktop.org/series/52378/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10919 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10919
== Series Details ==
Series: series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53097/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10918 =
==
== Series Details ==
Series: drm/i915: Fix TV encoder support (rev4)
URL : https://patchwork.freedesktop.org/series/52378/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/vblank: Allow dynamic per-crtc max_vblank_count
Okay!
Commit: drm/i915:
On 27/11/2018 09:38, Mika Kuoppala wrote:
Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.
Note that not all registers in the 12-deep CSB fifo are in a contiguous
range, the new ones (6-11) start at mmio_base + 0x3C0 (Bspec: 11724). If
== Series Details ==
Series: series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53097/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/dsc:
== Series Details ==
Series: series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53097/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b564f4b939ca drm/dsc: Modify DRM
== Series Details ==
Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO
size
URL : https://patchwork.freedesktop.org/series/53096/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10917 =
== Summary - SUCCESS ==
No
On Sat, 2018-11-17 at 12:24 +, Sasha Levin wrote:
> Hi,
>
> [This is an automated email]
>
> This commit has been processed because it contains a -stable tag.
> The stable tag indicates that it's relevant for the following trees: all
>
> The bot has tested the following trees: v4.19.2,
== Series Details ==
Series: drm/fbdev: Make skip_vt_switch the default (rev2)
URL : https://patchwork.freedesktop.org/series/53094/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10916 =
== Summary - FAILURE ==
Serious unknown changes coming with
From: Ville Syrjälä
On i965gm the hardware frame counter does not work when
the TV encoder is active. So let's not try to consult
the hardware frame counter in that case. Instead we'll
fall back to the timestamp based guesstimation method
used on gen2.
Note that the pipe timings generated by
From: Ville Syrjälä
On i965gm we need to adjust max_vblank_count dynamically
depending on whether the TV encoder is used or not. To
that end add a per-crtc max_vblank_count that takes
precedence over its device wide counterpart. The driver
can now call drm_crtc_set_max_vblank_count() to
== Series Details ==
Series: drm/fbdev: Make skip_vt_switch the default (rev2)
URL : https://patchwork.freedesktop.org/series/53094/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d2c59bd255a1 drm/fbdev: Make skip_vt_switch the default
-:22: ERROR:GIT_COMMIT_ID: Please use git
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)
URL : https://patchwork.freedesktop.org/series/51878/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10915 =
== Summary - SUCCESS ==
No regressions found.
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond
From: Anusha Srivatsa
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi
DSC DPCD color depth register advertises its color depth capabilities
by setting each of the bits that corresponding to a specific color
depth. This patch defines those specific color depths and adds
a helper to return an array of color depth capabilities.
v2:
* Simplify the logic (Ville)
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc
From: Anusha Srivatsa
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use
From: Anusha Srivatsa
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is
From: Anusha Srivatsa
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
== Series Details ==
Series: HDCP1.4 fixes (rev8)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5209_full -> Patchwork_10912_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are
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