On 5/8/19 12:01 AM, Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> Some buffers may only be partially filled with useful data, while the rest
> is padded (typically with 0x00 or 0xff).
>
> This patch introduces a flag to allow the supression of lines of repeated
> bytes, which are
== Series Details ==
Series: Enable Multi-segmented-gamma for ICL (rev3)
URL : https://patchwork.freedesktop.org/series/60126/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6065_full -> Patchwork_12989_full
Summary
---
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev9)
URL : https://patchwork.freedesktop.org/series/25091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6065_full -> Patchwork_12988_full
On Fri, 2019-05-03 at 22:08 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> ICL has so many planes that it can easily exceed the maximum
> effective memory bandwidth of the system. We must therefore check
> that we don't exceed that limit.
>
> The algorithm is very magic number heavy and
Hi Da.*,
So last week when I said we were ready for merge window... I lied. Lots of stuff
to sneak in this week including 6 patches that came from -misc-next. Fortunately
they _just_ missed the feature freeze so I was able to tag and merge them here.
Most of what is here is panfrost fixes, which
On Fri, 2019-05-03 at 22:08 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The pcode mailbox has two data registers. So far we've only ever used
> the one, but that's about to change. Expose the second data register
> to
> the callers of sandybridge_pcode_read().
>
> Signed-off-by: Ville
== Series Details ==
Series: Enable Multi-segmented-gamma for ICL (rev3)
URL : https://patchwork.freedesktop.org/series/60126/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6065 -> Patchwork_12989
Summary
---
We (Me and Uma) confirmed the ICL register programming sequence, by
dumping the registers.
The correct sequence should be:
ilk_lut_12p4_udw
ilk_lut_12p4_ldw
We passed maximum value LUT (1.0) and saw only blue output, if
programmed in opposite sequence.
Programming in above mentioned
This patch series enables programming of Multi-segmented-gamma
palette for ICL.
Shashank Sharma (3):
drm/i915: Change gamma/degamma_lut_size data type to u32
drm/i915: Rename ivb_load_lut_10_max
drm/i915/icl: Add Multi-segmented gamma support
Uma Shankar (1):
drm/i915/icl: Add register
Currently, data type of gamma_lut_size & degamma_lut_size elements
in intel_device_info is u16, which means it can accommodate maximum
64k values. In case of ICL multisegmented gamma, the size of gamma
LUT is 256K.
This patch changes the data type of both of these elements to u32.
Cc: Ville
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine precision. An
example use case for this is HDR curves (like PQ ST-2084).
If we plot a gamma correction curve from
From: Uma Shankar
Add macros to define multi segmented gamma registers
V2: Addressed Ville's comments:
Add gen-lable before bit definition
Addressed Jani's comment
- Use REG_GENMASK() and REG_BIT()
V3: Addressed Ville's comments:
- Put comments at the end of line.
-
This patch renames function ivb_load_lut_10_max to
ivb_load_lut_ext_max.
V3: Added Vill'es r-b.
Cc: Uma Shankar
Suggested-by: Ville Syrjala
Reviewed-by: Ville Syrjala
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_color.c | 14 +++---
1 file changed, 7 insertions(+),
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev9)
URL : https://patchwork.freedesktop.org/series/25091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6065 -> Patchwork_12988
Summary
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev9)
URL : https://patchwork.freedesktop.org/series/25091/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b14249ae3b1a drm: Add HDR source metadata property
-:70: CHECK:PARENTHESIS_ALIGNMENT:
This patch series enables HDR support in drm. It basically defines
HDR metadata structures, property to pass content (after blending)
metadata from user space compositors to driver.
Dynamic Range and Mastering infoframe creation and sending.
ToDo:
1. We need to get the color framework in place
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
Attach HDR metadata property to connector object.
v2: Rebase
v3: Updated the property name as per updated name
while creating hdr metadata property
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
v2: Addressed Shashank's review comments.
v3: Added Shashank's RB.
v4: Addressed Ville's review comments.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions supported.
Hybrid Log-Gamma (HLG) is a high dynamic range (HDR) standard.
HLG defines a nonlinear transfer function in which the lower
half of the signal values use a gamma curve and the upper half
of the signal values use a
Added state readout for DRM infoframe and enabled
state validation for DRM infoframe.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_ddi.c | 4
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_hdmi.c| 4
3 files changed, 9 insertions(+)
diff
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
v3: Addressed Shashank's review comment.
v4: Added Shashank's RB.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
Reviewed-by: Shashank
BYT/CHT doesn't support DRM Infoframe. This caused
a WARN_ON due to a missing CASE while executing
intel_hdmi_infoframes_enabled function. This patch
fixes the same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Added unpack function for DRM infoframe for dynamic
range and mastering infoframe readout.
Suggested-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 54
include/linux/hdmi.h | 1 +
2 files changed, 55 insertions(+)
HDR metadata requires a infoframe to be set. Due to fastset,
full modeset is not performed hence adding it to update_pipe
to handle that.
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +
drivers/gpu/drm/i915/intel_hdmi.c | 7
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comments
v5: Rebase. Added infoframe
From: Jonas Karlman
This adds reference count for HDR metadata blob,
handled as part of duplicate and destroy connector
state functions.
Signed-off-by: Jonas Karlman
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 6 ++
1 file changed, 6 insertions(+)
diff
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
It also implements get() and set() functions for HDR output
metadata property.The blob data is received from userspace and
saved in connector state, the same is
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
v3: No Change
v4: Addressed Shashank's review comments
v5: Addressed Shashank's comment and added his RB.
v6: Addressed Jonas Karlman
On Wed, May 08, 2019 at 11:17:56AM +0300, Gwan-gyeong Mun wrote:
> Data M/N calculations were assumed a bpp as RGB format. But when we are
> using YCbCr 4:2:0 output format on DP, we should change bpp calculations
> as YCbCr 4:2:0 format. The pipe_bpp value was assumed RGB format,
> therefore, it
On Wed, May 08, 2019 at 11:17:54AM +0300, Gwan-gyeong Mun wrote:
> Function intel_pixel_encoding_setup_vsc handles vsc header and data block
> setup for pixel encoding / colorimetry format.
>
> Setup VSC header and data block in function intel_pixel_encoding_setup_vsc
> for pixel encoding /
On Wed, May 08, 2019 at 11:17:53AM +0300, Gwan-gyeong Mun wrote:
> SDP VSC Header and Data Block follow DP 1.4a spec, section 2.2.5.7.5,
> chapter "VSC SDP Payload for Pixel Encoding/Colorimetry Format".
>
> Signed-off-by: Gwan-gyeong Mun
> Reviewed-by: Maarten Lankhorst
> ---
>
== Series Details ==
Series: drm/i915: Fix skl plane scaling for planner YUV buffers
URL : https://patchwork.freedesktop.org/series/60414/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063_full -> Patchwork_12987_full
From: Sean Paul
Everyone who implements connector_helper_funcs->atomic_check reaches
into the connector state to get the atomic state. Instead of continuing
this pattern, change the callback signature to just give atomic state
and let the driver determine what it does and does not need from it.
== Series Details ==
Series: drm/i915: Reboot CI if forcewake fails
URL : https://patchwork.freedesktop.org/series/60412/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063_full -> Patchwork_12986_full
Summary
---
On 08/05/2019 14:56, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 14:50:41)
On 08/05/2019 13:27, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:53)
From: Tvrtko Ursulin
A few additional workloads useful for experimenting with scheduling.
Signed-off-by: Tvrtko
Quoting Mika Kuoppala (2019-05-08 15:00:11)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2019-05-08 13:30:46)
> >> Chris Wilson writes:
> >>
> >> > After realising we need to sample RING_START to detect context switches
> >> > from preemption events that do not allow for the seqno to
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-05-08 13:30:46)
>> Chris Wilson writes:
>>
>> > After realising we need to sample RING_START to detect context switches
>> > from preemption events that do not allow for the seqno to advance, we
>> > can also realise that the seqno itself is
Quoting Tvrtko Ursulin (2019-05-08 14:50:41)
>
> On 08/05/2019 13:27, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-05-08 13:10:53)
> >> From: Tvrtko Ursulin
> >>
> >> A few additional workloads useful for experimenting with scheduling.
> >>
> >> Signed-off-by: Tvrtko Ursulin
> >
> >
On Wed, May 08, 2019 at 05:34:37PM +0530, Shashank Sharma wrote:
> From: Lukas Rusak
>
> Plane scaling for YUV planar formats should be max 2 times.
Nope. Spec says it should be < 2.0 on pre-glk, and < 3.0 on glk+.
>
> Cc: Maarten Lankhorst
> Cc: Juha-pekka Heikkila
> Cc: Shashank Sharma
>
On 08/05/2019 13:27, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:53)
From: Tvrtko Ursulin
A few additional workloads useful for experimenting with scheduling.
Signed-off-by: Tvrtko Ursulin
Are the extra modes & .wsim supported by scripts/media-bench.pl?
i.e. can I just
>-Original Message-
>From: Sharma, Shashank
>Sent: Tuesday, May 7, 2019 7:27 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Sharma, Shashank ; Ville Syrjälä
>; Maarten Lankhorst
>; Shankar, Uma
>Subject: [PATCH v3 1/4] drm/i915: Change gamma/degamma_lut_size data type to
>u32
>
== Series Details ==
Series: drm/i915: Fix skl plane scaling for planner YUV buffers
URL : https://patchwork.freedesktop.org/series/60414/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12987
Summary
On Wed, May 08, 2019 at 04:11:28PM +0300, Andy Shevchenko wrote:
> On Wed, May 08, 2019 at 02:28:29PM +0300, Alexandru Ardelean wrote:
> > This change re-introduces `match_string()` as a macro that uses
> > ARRAY_SIZE() to compute the size of the array.
> > The macro is added in all the places
On Wed, May 08, 2019 at 02:28:29PM +0300, Alexandru Ardelean wrote:
> This change re-introduces `match_string()` as a macro that uses
> ARRAY_SIZE() to compute the size of the array.
> The macro is added in all the places that do
> `match_string(_a, ARRAY_SIZE(_a), s)`, since the change is pretty
On 5/7/2019 7:57 PM, Ville Syrjälä wrote:
On Tue, May 07, 2019 at 07:26:44PM +0530, Shashank Sharma wrote:
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine
Quoting Mika Kuoppala (2019-05-08 13:18:06)
> Chris Wilson writes:
>
> > If the HW fail to ack a change in forcewake status, the machine is as
> > good as dead -- it may recover, but in reality it missed the mmio
> > updates and is now in a very inconsistent state. If it happens, we can't
> >
== Series Details ==
Series: drm/i915: Fix skl plane scaling for planner YUV buffers
URL : https://patchwork.freedesktop.org/series/60414/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Fix skl plane scaling for planner YUV buffers
Quoting Mika Kuoppala (2019-05-08 13:30:46)
> Chris Wilson writes:
>
> > After realising we need to sample RING_START to detect context switches
> > from preemption events that do not allow for the seqno to advance, we
> > can also realise that the seqno itself is just a distance along the ring
Chris Wilson writes:
> After realising we need to sample RING_START to detect context switches
> from preemption events that do not allow for the seqno to advance, we
> can also realise that the seqno itself is just a distance along the ring
> and so can be replaced by sampling RING_HEAD.
>
>
== Series Details ==
Series: drm/i915: Reboot CI if forcewake fails
URL : https://patchwork.freedesktop.org/series/60412/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12986
Summary
---
**SUCCESS**
Quoting Mika Kuoppala (2019-05-08 13:18:06)
> Chris Wilson writes:
>
> > If the HW fail to ack a change in forcewake status, the machine is as
> > good as dead -- it may recover, but in reality it missed the mmio
> > updates and is now in a very inconsistent state. If it happens, we can't
> >
Quoting Tvrtko Ursulin (2019-05-08 13:10:53)
> From: Tvrtko Ursulin
>
> A few additional workloads useful for experimenting with scheduling.
>
> Signed-off-by: Tvrtko Ursulin
Are the extra modes & .wsim supported by scripts/media-bench.pl?
i.e. can I just run media-bench.pl and have it
On Wed, May 08, 2019 at 02:28:35PM +0300, Alexandru Ardelean wrote:
> -static const char * const phy_types[] = {
> - "emmc 5.0 phy",
> - "emmc 5.1 phy"
> -};
> -
> enum xenon_phy_type_enum {
> EMMC_5_0_PHY,
> EMMC_5_1_PHY,
> NR_PHY_TYPES
There is no need for
Chris Wilson writes:
> If the HW fail to ack a change in forcewake status, the machine is as
> good as dead -- it may recover, but in reality it missed the mmio
> updates and is now in a very inconsistent state. If it happens, we can't
> trust the CI results (or at least the fails may be genuine
Quoting Tvrtko Ursulin (2019-05-08 13:10:38)
> From: Tvrtko Ursulin
>
> After the removal of engine global seqnos and the corresponding
> intel_engine_notify tracepoints the script needs to be adjusted to cope
> with the new state of things.
>
> To keep working it switches over using the
From: Tvrtko Ursulin
There is a repeated pattern with error handling which can be moved to a
macro to for better readability in the command parsing loop.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 244 +++---
1 file changed, 88 insertions(+),
From: Tvrtko Ursulin
A few additional workloads useful for experimenting with scheduling.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/wsim/frame-split-60fps.wsim | 16
benchmarks/wsim/high-composited-game.wsim | 11 +++
benchmarks/wsim/media-1080p-player.wsim
From: Tvrtko Ursulin
A new workload command ('S') is added which allows per context slice
(re-)configuration.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 69 +++---
benchmarks/wsim/README | 23 +-
2 files changed, 80
From: Tvrtko Ursulin
Support i915 virtual engine from gem_wsim (-b i915) and media-bench.pl
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 281 ++---
scripts/media-bench.pl | 9 +-
2 files changed, 244 insertions(+), 46 deletions(-)
diff
From: Tvrtko Ursulin
To allow exercising the SSEU configuration in combination with Virtual
Engine, allow RCS to be specified in the engine map and use appropriate
index based addressing when applying SSEU configuration to it.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 51
From: Tvrtko Ursulin
A few more opportunities to compact the code by using the error logging
helper.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 54 ---
1 file changed, 15 insertions(+), 39 deletions(-)
diff --git a/benchmarks/gem_wsim.c
From: Tvrtko Ursulin
A new command line switch ('-s') is added which toggles the low slice
count mode for workloads following on the command line.
This enables easy benchmarking of the effect of running the existing media
workloads in parallel against another client. For example:
./gem_wsim
From: Tvrtko Ursulin
Parsing an integer workload descriptor field is a common pattern which we
can extract to a helper macro and by doing so further improve the
readability of the main parsing loop.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 80
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 5245692df6eb..f654decb24cc 100644
---
From: Tvrtko Ursulin
A new workload command for enabling a load balanced context map (aka
Virtual Engine). Example usage:
B.1
This turns on load balancing for context one, assuming it has already been
configured with an engine map. Only DEFAULT engine specifier can be used
with load balanced
From: Tvrtko Ursulin
We can improve the parsing loop readability a bit more by avoiding some
line breaks caused by explicit NULL checks.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 39 +++
1 file changed, 15 insertions(+), 24 deletions(-)
From: Tvrtko Ursulin
Support new i915 uAPI for configuring contexts with engine maps.
Please refer to the README file for more detailed explanation.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 212 ++---
benchmarks/wsim/README | 17 +++-
2
From: Tvrtko Ursulin
For simulating frame split workloads it is useful to express a batch which
ends at the same time as the parallel submission on the respective bonded
engine. For this we add support for infinite batch durations and the batch
terminate command ('T'). Syntax looks like this:
From: Tvrtko Ursulin
Test the new engine discovery query.
Signed-off-by: Tvrtko Ursulin
---
tests/i915/i915_query.c | 247
1 file changed, 247 insertions(+)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index
From: Tvrtko Ursulin
Engine bonds are an i915 uAPI applicable to load balanced contexts with
engine map. They allow expression rules of engine selection between two
contexts when submissions are also tied with submit fences.
Please refer to the README for a more detailed description.
From: Tvrtko Ursulin
Add support for submit fences in a way similar to how normal input fences
are handled. Eg:
1.RCS.500-1000.0.0
1.VCS1.3000.s-1.0
1.VCS2.3000.s-2.0
Submit fences are signalled when the originating request enters the
submission backend.
Signed-off-by: Tvrtko Ursulin
From: Tvrtko Ursulin
We are moving towards bumping the uAPI headers more often instead of using
too much local struct/ioctl/param definitions since the latter are more
challenging for rebase and maintenance.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 12
1 file
From: Tvrtko Ursulin
Catch up to drm-tip headers.
Signed-off-by: Tvrtko Ursulin
---
include/drm-uapi/amdgpu_drm.h | 52 +++-
include/drm-uapi/drm.h | 36 ++
include/drm-uapi/drm_mode.h | 4 +-
include/drm-uapi/i915_drm.h | 209 +++-
From: Tvrtko Ursulin
Use the 'completed?' tracepoint field to detect more robustly when a
request has been preempted and remove it from the engine database if so.
Otherwise the script can hit a scenario where the same global seqno will
be mentioned multiple times (on an engine seqno) which
From: Tvrtko Ursulin
Mostly work to support Virtual Engine in trace.pl and gem_wsim complementing the
set of IGTs written by Chris.
Also includes trace.pl update for after engine seqno removal and engine
discovery tests.
Altogether it allows benchamrking and tracing the simulated media
From: Tvrtko Ursulin
After the removal of engine global seqnos and the corresponding
intel_engine_notify tracepoints the script needs to be adjusted to cope
with the new state of things.
To keep working it switches over using the dma_fence:dma_fence_signaled:
tracepoint and keeps one extra
== Series Details ==
Series: series starting with [01/40] drm/i915/hangcheck: Replace
hangcheck.seqno with RING_HEAD (rev4)
URL : https://patchwork.freedesktop.org/series/60403/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12985
From: Tvrtko Ursulin
Add virtual/queue timelines to both stdout and HTML output.
A new timeline is created for each queue/virtual engine to display
associated requests in queued and runnable states. Once requests are
submitted to a real engine for executing they show up on the physical
engine
From: Lukas Rusak
Plane scaling for YUV planar formats should be max 2 times.
Cc: Maarten Lankhorst
Cc: Juha-pekka Heikkila
Cc: Shashank Sharma
Signed-off-by: Lukas Rusak
---
drivers/gpu/drm/i915/intel_display.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff
== Series Details ==
Series: series starting with [01/40] drm/i915/hangcheck: Replace
hangcheck.seqno with RING_HEAD (rev4)
URL : https://patchwork.freedesktop.org/series/60403/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/hangcheck:
On 08/05/2019 12:25, Chris Wilson wrote:
Move the duplicated code within dma-fence.c into the header for wider
reuse.
For this one I am not sure whether to go with static inlines or
EXPORT_SYMBOL the helpers.
Also you'll need to mention that in the same patch you are optimized the
If the HW fail to ack a change in forcewake status, the machine is as
good as dead -- it may recover, but in reality it missed the mmio
updates and is now in a very inconsistent state. If it happens, we can't
trust the CI results (or at least the fails may be genuine but due to
the HW being dead
On 08/05/2019 12:24, Chris Wilson wrote:
Currently there is an underlying assumption that i915_request_unsubmit()
is synchronous wrt the GPU -- that is the request is no longer in flight
as we remove it. In the near future that may change, and this may upset
our signaling as we can process an
== Series Details ==
Series: drm/i915/dp: Support for DP YCbCr4:2:0 outputs
URL : https://patchwork.freedesktop.org/series/60404/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063_full -> Patchwork_12983_full
Summary
== Series Details ==
Series: series starting with [01/40] drm/i915/hangcheck: Replace
hangcheck.seqno with RING_HEAD (rev4)
URL : https://patchwork.freedesktop.org/series/60403/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e7ad7ff7e483 drm/i915/hangcheck: Replace
On 08/05/2019 12:17, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 11:29:34)
On 08/05/2019 09:06, Chris Wilson wrote:
+static int live_virtual_engine(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct intel_engine_cs *siblings[MAX_ENGINE_INSTANCE + 1];
+
On 08/05/2019 12:23, Chris Wilson wrote:
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of
Currently there is an underlying assumption that i915_request_unsubmit()
is synchronous wrt the GPU -- that is the request is no longer in flight
as we remove it. In the near future that may change, and this may upset
our signaling as we can process an interrupt for that request while it
is no
Move the duplicated code within dma-fence.c into the header for wider
reuse.
Signed-off-by: Chris Wilson
---
drivers/dma-buf/Makefile| 10 +-
drivers/dma-buf/dma-fence-trace.c | 28 +++
drivers/dma-buf/dma-fence.c | 32 +--
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the set in a manner as best to
distribute
== Series Details ==
Series: series starting with [01/40] drm/i915/hangcheck: Replace
hangcheck.seqno with RING_HEAD
URL : https://patchwork.freedesktop.org/series/60403/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12984
Quoting Tvrtko Ursulin (2019-05-08 11:29:34)
>
> On 08/05/2019 09:06, Chris Wilson wrote:
> > +static int live_virtual_engine(void *arg)
> > +{
> > + struct drm_i915_private *i915 = arg;
> > + struct intel_engine_cs *siblings[MAX_ENGINE_INSTANCE + 1];
> > + struct intel_engine_cs
== Series Details ==
Series: series starting with [01/40] drm/i915/hangcheck: Replace
hangcheck.seqno with RING_HEAD
URL : https://patchwork.freedesktop.org/series/60403/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/hangcheck: Replace
== Series Details ==
Series: series starting with [01/40] drm/i915/hangcheck: Replace
hangcheck.seqno with RING_HEAD
URL : https://patchwork.freedesktop.org/series/60403/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
67b421614964 drm/i915/hangcheck: Replace hangcheck.seqno
Op 25-04-2019 om 18:29 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> On HSW the pipe A panel fitter lives inside the display power well,
> and the input MUX for the EDP transcoder needs to be configured
> appropriately to route the data through the power well as needed.
> Changing the MUX
On 08/05/2019 09:06, Chris Wilson wrote:
Allow the user to specify a local engine index (as opposed to
class:index) that they can use to refer to a preset engine inside the
ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES.
This will be useful for setting SSEU parameters on
On 08/05/2019 09:06, Chris Wilson wrote:
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of
== Series Details ==
Series: drm/i915/dp: Support for DP YCbCr4:2:0 outputs
URL : https://patchwork.freedesktop.org/series/60404/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12983
Summary
---
On 08/05/2019 09:06, Chris Wilson wrote:
The SINGLE_TIMELINE flag can be used to create a context such that all
engine instances within that context share a common timeline. This can
be useful for mixing operations between real and virtual engines, or
when using a composite context for a single
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