[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Try to fix encoder possible_clones/crtc

== Series Details == Series: drm: Try to fix encoder possible_clones/crtc URL : https://patchwork.freedesktop.org/series/63399/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13568_full Summary

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+

Hello Ram, On 7/2/2019 11:24 AM, Ramalingam C wrote: From Gen12 onwards, HDCP HW block is implemented within transcoders. Till Gen11 HDCP HW block was part of DDI. Hence required changes in HW programming is handled here. v2: _MMIO_TRANS is used [Lucas and Daniel] platform check is

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Reorder error cleanup for whitelist checking (rev2)

== Series Details == Series: drm/i915/selftests: Reorder error cleanup for whitelist checking (rev2) URL : https://patchwork.freedesktop.org/series/63394/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13567_full

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Explicitly track active fw_domain timers (rev3)

== Series Details == Series: drm/i915: Explicitly track active fw_domain timers (rev3) URL : https://patchwork.freedesktop.org/series/63331/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13566_full

Re: [Intel-gfx] [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote: > From: José Roberto de Souza > > On TGL the special EDP transcoder is gone and it should be handled by > transcoder A. > > v2 (Lucas): > - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville) > - Use crtc->dev since

Re: [Intel-gfx] [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks

On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote: > Transition the remaining uses of intel_port_is_* over to the > equivalent > intel_phy_is_* functions and drop the port functions. Awesome Reviewed-by: José Roberto de Souza > > Cc: José Roberto de Souza > Signed-off-by: Matt Roper >

Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: simplify guc client

On Tue, Jul 02, 2019 at 01:09:46PM -0700, Daniele Ceraolo Spurio wrote: We originally added support, in some cases partial, for different modes of operations via guc clients: - proxy vs direct submission; - variable engine mask per-client. We only ever used one flow (all submissions via a

Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Remove preemption support for current fw

On Tue, Jul 02, 2019 at 01:09:45PM -0700, Daniele Ceraolo Spurio wrote: From: Chris Wilson Preemption via GuC submission is not being supported with its current legacy incarnation. The current FW does support a similar pre-emption flow via H2G, but it is class-based instead of being

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915: Clear the shared PLL from the put_dplls() hook

== Series Details == Series: series starting with [v2,1/2] drm/i915: Clear the shared PLL from the put_dplls() hook URL : https://patchwork.freedesktop.org/series/63384/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13564_full

Re: [Intel-gfx] [PATCH] drm/i915/userptr: Acquire the page lock around set_page_dirty()

Hi, [This is an automated email] This commit has been processed because it contains a "Fixes:" tag, fixing commit: 5cc9ed4b9a7a drm/i915: Introduce mapping of user pages into video memory (userptr) ioctl. The bot has tested the following trees: v5.1.16, v4.19.57, v4.14.132, v4.9.184,

Re: [Intel-gfx] [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'

On Mon, 2019-07-08 at 23:59 +, Souza, Jose wrote: > On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote: > > Our past DDI-based Intel platforms have had a fixed DDI<->PHY > > mapping. > > Because of this, both the bspec documentation and our i915 code has > > used > > the term "port" when

Re: [Intel-gfx] [PATCH v4 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace

On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote: > Convert the code that operates directly on gen11 combo PHY's to use > the > new namespace. Combo PHY registers are those named "ICL_PORT_*" plus > ICL_DPHY_CHKN. > > Note that a lot of the PHY programming happens in the MIPI DSI code. > For

Re: [Intel-gfx] [PATCH v5 2/5] drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY

On Wed, 2019-07-03 at 18:06 -0700, Matt Roper wrote: > Although the register name implies that it operates on DDI's, > DPCLKA_CFGCR0_ICL actually needs to be programmed according to the > PHY > that's in use. I.e., when using EHL's DDI-D on combo PHY A, the bits > described as "port A" in the

Re: [Intel-gfx] [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'

On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote: > Our past DDI-based Intel platforms have had a fixed DDI<->PHY > mapping. > Because of this, both the bspec documentation and our i915 code has > used > the term "port" when talking about either DDI's or PHY's; it was > always > easy to tell

Re: [Intel-gfx] linux-next: manual merge of the drm-intel tree with the pci tree

Hi all, On Mon, 24 Jun 2019 13:53:52 +1000 Stephen Rothwell wrote: > > On Mon, 17 Jun 2019 13:20:27 +1000 Stephen Rothwell > wrote: > > > > Today's linux-next merge of the drm-intel tree got a conflict in: > > > > drivers/gpu/drm/i915/i915_drv.h > > > > between commit: > > > >

[Intel-gfx] ✓ Fi.CI.BAT: success for Initial support for Tiger Lake (rev2)

== Series Details == Series: Initial support for Tiger Lake (rev2) URL : https://patchwork.freedesktop.org/series/62726/ State : success == Summary == CI Bug Log - changes from CI_DRM_6433 -> Patchwork_13574 Summary --- **SUCCESS**

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/userptr: Acquire the page lock around set_page_dirty()

== Series Details == Series: drm/i915/userptr: Acquire the page lock around set_page_dirty() URL : https://patchwork.freedesktop.org/series/63383/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13563_full

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev2)

== Series Details == Series: Initial support for Tiger Lake (rev2) URL : https://patchwork.freedesktop.org/series/62726/ State : warning == Summary == $ dim checkpatch origin/drm-tip 00d88902cdbe drm/i915: Add 4th pipe and transcoder 1957212e1a06 drm/i915/tgl: add initial Tiger Lake

[Intel-gfx] [PATCH v2 18/25] drm/i915/tgl: extend intel_port_is_combophy/tc

From: Mahesh Kumar TGL has 3 combophy ports, so extend check for tigerlake in intel_port_is_combophy/tc function. Cc: Mika Kahola Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display.c | 12 +--- 1 file changed, 9 insertions(+), 3

[Intel-gfx] [PATCH v2 21/25] drm/i915/tgl: apply Display WA #1178 to fix type C dongles

Add port C to workaround to cover Tiger Lake. Cc: Rodrigo Vivi Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display_power.c | 11 --- drivers/gpu/drm/i915/i915_reg.h| 4 +++- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] [PATCH v2 12/25] drm/i915/tgl: Add pll manager

From: Vandita Kulkarni Add a new pll array for Tiger Lake. The TC pll functions for type C will be covered in later patches after its phy is implemented. Cc: Madhav Chauhan Cc: Rodrigo Vivi Signed-off-by: Vandita Kulkarni Signed-off-by: Lucas De Marchi ---

[Intel-gfx] [PATCH v2 20/25] drm/i915/tgl: Add vbt value mapping for DDC Bus pin

From: Mahesh Kumar Add VBT-value to DDC bus pin mapping for the same. Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_bios.c | 17 - drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +++ 2 files changed, 19

[Intel-gfx] [PATCH v2 17/25] drm/i915/tgl: select correct bit for port select

From: Mahesh Kumar Bit definitions for port-select got changed for TRANS_CLK_SEL & TRANS_DDI_FUNC_CTL registers in TGL. Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++- drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH v2 07/25] drm/i915/tgl: Check if pipe D is fused

From: José Roberto de Souza On Tiger Lake there is one more pipe - check if it's fused. Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_device_info.c | 3 +++ 2 files changed, 4 insertions(+)

[Intel-gfx] [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A

From: José Roberto de Souza On TGL the special EDP transcoder is gone and it should be handled by transcoder A. v2 (Lucas): - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville) - Use crtc->dev since new_crtc_state->state may be NULL on atomic commit (suggested by Maarten) Cc:

[Intel-gfx] [PATCH v2 19/25] drm/i915/tgl: init ddi port A-C for Tiger Lake

From: Mahesh Kumar This patch initializes DDI PORT A, B & C for Tiger lake. Other TC ports need to be initialized later once corresponding code is there. Cc: Madhav Chauhan Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display.c | 9

[Intel-gfx] [PATCH v2 04/25] drm/i915/tgl: Add TGL PCH detection in virtualized environment

From: Mahesh Kumar Assume PCH_TGP when platform is TGL. Cc: Rodrigo Vivi Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_drv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH v2 16/25] drm/i915/tgl: port to ddc pin mapping

From: Mahesh Kumar Create a helper function to get ddc pin according to port number. Cc: Anusha Srivatsa Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff

[Intel-gfx] [PATCH v2 02/25] drm/i915/tgl: add initial Tiger Lake definitions

From: Daniele Ceraolo Spurio Tiger Lake is a Intel® Processor containing Intel® HD Graphics. This is just an initial Tiger Lake definition. PCI IDs, generic support and new features coming in following patches. v2 (Lucas): - Remove modular FIA - feature will be re-introduced in future Cc:

[Intel-gfx] [PATCH v2 22/25] drm/i915/gen12: MBUS B credit change

From: Rodrigo Vivi Previously, the recommended B credit for all platforms was 24 / number of pipes, which would give 6 for newer platforms with 4 pipes. However 6 is not enough and we need 12 on these cases. We also need a different BW credit for these platforms. Cc: Arthur J Runyan

[Intel-gfx] [PATCH v2 15/25] drm/i915/tgl: Add gmbus gpio pin to port mapping

From: Mahesh Kumar Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are mapped to TC ports. Cc: Anusha Srivatsa Cc: Rodrigo Vivi Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi ---

[Intel-gfx] [PATCH v2 13/25] drm/i915/tgl: Add additional ports for Tiger Lake

From: Vandita Kulkarni There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a combophy port. This results in 6 typeC ports and 3 combophy ports. These 6 TC ports can be DP alternate mode, DP over thunderbolt, native DP on legacy DP connector or native HDMI on legacy connector.

[Intel-gfx] [PATCH v2 24/25] drm/i915/tgl: Add DPLL registers

On TGL the port programming for combophy is very similar to ICL, so adapt the callers to possibly use the different register values. Cc: Vandita Kulkarni Cc: Rodrigo Vivi Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++

[Intel-gfx] [PATCH v2 11/25] drm/i915/tgl: Add new pll ids

From: Vandita Kulkarni Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL changed, but most registers remained the same, like MGPLL5_ENABLE, MGPLL6_ENABLE. So continue to use the name from ICL. Cc: Madhav Chauhan Cc: Rodrigo Vivi Signed-off-by: Vandita Kulkarni

[Intel-gfx] [PATCH v2 23/25] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization

According to the spec when initializing the display in TGL we should not set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-use the power well hooks from ICL so just check for IS_TIGERLAKE() inside it. Cc: Imre Deak Signed-off-by: Lucas De Marchi ---

[Intel-gfx] [PATCH v2 06/25] x86/gpu: add TGL stolen memory support

From: Michel Thierry Reuse Gen11 stolen memory changes since Tiger Lake uses the same BSM register (and format). Cc: Rodrigo Vivi Signed-off-by: Michel Thierry Signed-off-by: Lucas De Marchi --- arch/x86/kernel/early-quirks.c | 1 + 1 file changed, 1 insertion(+) diff --git

[Intel-gfx] [PATCH v2 09/25] drm/i915/tgl: Add power well support

From: Imre Deak The patch adds the new power wells introduced by TGL (GEN 12) and maps these to existing/new power domains. The changes for GEN 12 wrt to GEN 11 are the following: - Transcoder#EDP removed from power well#1 (Transcoder#A used in low-power mode instead) - Transcoder#A is now

[Intel-gfx] [PATCH v2 25/25] drm/i915/tgl: Update DPLL clock reference register

From: José Roberto de Souza This register definition changed from ICL and has now another meaning. Use the right bits on TGL. Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++-- drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH v2 05/25] drm/i915/tgl: Add TGL PCI IDs

Current list of PCI IDs for Tiger Lake. Cc: Rodrigo Vivi Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_pci.c | 1 + include/drm/i915_pciids.h | 10 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c

[Intel-gfx] [PATCH v2 03/25] drm/i915/tgl: Introduce Tiger Lake PCH

From: Radhakrishna Sripada Add the enum additions to TGP. Cc: Rodrigo Vivi Cc: Joonas Lahtinen Cc: David Weinehall Cc: James Ausmus Signed-off-by: Radhakrishna Sripada Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_drv.c | 4 drivers/gpu/drm/i915/i915_drv.h | 3 +++ 2

[Intel-gfx] [PATCH v2 01/25] drm/i915: Add 4th pipe and transcoder

Add pipe D and transcoder D to prepare for platforms having them. Cc: Rodrigo Vivi Signed-off-by: Lucas De Marchi Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 3 ++- drivers/gpu/drm/i915/display/intel_display.h | 4 drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH v2 14/25] drm/i915/tgl: update ddi/tc clock_off bits

From: Mahesh Kumar In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B, it's at offset 24. Similarly TC port (5/6) clk off bits are at offset 22/23. Extend the macros to cover the additional ports. Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi ---

[Intel-gfx] [PATCH v2 00/25] Initial support for Tiger Lake

v2 of https://patchwork.freedesktop.org/series/62726/ - Remove patches already reviewed - Remove modular FIA - it's handled in a separate series now - Add r-b on some patches - Handle comments on power well definitions Patches are from their original authors, modified as per review on

[Intel-gfx] [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe

From: Mika Kahola Add power well 5 to support 4th pipe and transcoder on TGL. Cc: James Ausmus Cc: Imre Deak Signed-off-by: Mika Kahola Signed-off-by: Lucas De Marchi --- .../drm/i915/display/intel_display_power.c| 30 --- .../drm/i915/display/intel_display_power.h|

Re: [Intel-gfx] [PATCH 8/8] drm/i915/gt: Use intel_gt as the primary object for handling resets

On 7/5/19 12:46 AM, Chris Wilson wrote: Having taken the first step in encapsulating the functionality by moving the related files under gt/, the next step is to start encapsulating by passing around the relevant structs rather than the global drm_i915_private. In this step, we pass intel_gt

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Set igt_spinner.gt for early exit

== Series Details == Series: drm/i915/selftests: Set igt_spinner.gt for early exit URL : https://patchwork.freedesktop.org/series/63414/ State : success == Summary == CI Bug Log - changes from CI_DRM_6433 -> Patchwork_13573 Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Define GuC firmware version for Comet Lake (rev2)

== Series Details == Series: drm/i915/guc: Define GuC firmware version for Comet Lake (rev2) URL : https://patchwork.freedesktop.org/series/62969/ State : success == Summary == CI Bug Log - changes from CI_DRM_6433 -> Patchwork_13572

[Intel-gfx] [PATCH] drm/i915/selftests: Set igt_spinner.gt for early exit

Set up a default gt pointer for an early cleanup of igt_spinnter, before a request is created and igt_spinner.gt set to the active engine's. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/selftests/igt_spinner.c | 1 + 1 file changed, 1 insertion(+) diff --git

[Intel-gfx] PR- GUC v33 (BXT,SKL,GLK.KBL,ICL)

Hi, Can these i915 changes be merged to the linux-firmware.git? The following changes since commit 70e43940b05e8d6e0c5f15b5e2d67760f1581ece: linux-firmware: rsi: add firmware image for redpine 9116 chipset (2019-06-28 07:41:20 -0400) are available in the Git repository at:

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Remove presumption of RCS0

Quoting Summers, Stuart (2019-07-08 22:11:15) > On Fri, 2019-07-05 at 13:43 +0100, Chris Wilson wrote: > > We now track features correctly instead of probing i915->engine[RCS0] > > which is much more flexible and avoids any nasty surprises. > > > > Signed-off-by: Chris Wilson > > Cc: Tvrtko

[Intel-gfx] [PATCH] drm/i915/guc: Define GuC firmware version for Comet Lake

Load GuC for Comet Lake. Depending on the REVID, we load either the KBL firmware or the CML firmware. v2: Use CFL for CML platform check.(Michal) Cc: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_guc_fw.c | 19 ++- 1

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Remove presumption of RCS0

On Fri, 2019-07-05 at 13:43 +0100, Chris Wilson wrote: > We now track features correctly instead of probing i915->engine[RCS0] > which is much more flexible and avoids any nasty surprises. > > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c |

Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Apply RCS workarounds to the render class

On Fri, 2019-07-05 at 13:43 +0100, Chris Wilson wrote: > Treat all render engines to the RCS workarounds, simply to avoid > using > engine->id when we are trying to think in terms of classes. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- > 1 file

Re: [Intel-gfx] [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain

On Mon, Jul 01, 2019 at 08:32:59PM +0300, Ville Syrjälä wrote: On Fri, Jun 28, 2019 at 09:31:04AM -0700, Lucas De Marchi wrote: On Fri, Jun 28, 2019 at 12:55:17PM +0300, Ville Syrjälä wrote: >On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote: >> From: José Roberto de Souza >> >>

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plane cdclk requirements and fp16 for gen4+

== Series Details == Series: drm/i915: Plane cdclk requirements and fp16 for gen4+ URL : https://patchwork.freedesktop.org/series/63373/ State : success == Summary == CI Bug Log - changes from CI_DRM_6429_full -> Patchwork_13562_full

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hdcp: debug logs for sink related failures

== Series Details == Series: drm/i915/hdcp: debug logs for sink related failures URL : https://patchwork.freedesktop.org/series/63406/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13571 Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for HDCP2.2 Phase II (rev11)

== Series Details == Series: HDCP2.2 Phase II (rev11) URL : https://patchwork.freedesktop.org/series/57232/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13570 Summary --- **SUCCESS** No

Re: [Intel-gfx] use exact allocation for dma coherent memory

On Tue, Jul 02, 2019 at 11:48:44AM +0200, Arend Van Spriel wrote: > You made me look ;-) Actually not touching my drivers so I'm off the hook. > However, I was wondering if drivers could know so I decided to look into > the DMA-API.txt documentation which currently states: > > """ > The flag

[Intel-gfx] [PATCH v2] drm/i915/hdcp: debug logs for sink related failures

Adding few more debug logs to identify the sink specific HDCP failures along with a out of mem failure. v2: Capturing the Bug and a-b Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110991 Signed-off-by: Ramalingam C cc: Daniel Vetter Acked-by: Daniel Vetter ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP2.2 Phase II (rev11)

== Series Details == Series: HDCP2.2 Phase II (rev11) URL : https://patchwork.freedesktop.org/series/57232/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4850c38d571b drm: Add Content protection type property -:123: CHECK:LINE_SPACING: Please use a blank line after

[Intel-gfx] [PATCH v9 6/6] drm/hdcp: reference for srm file format

In the kernel documentation, HDCP specifications links are shared as a reference for SRM table format. Signed-off-by: Ramalingam C --- drivers/gpu/drm/drm_hdcp.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c index

[Intel-gfx] [PATCH v9 5/6] drm/i915: update the hdcp state with uevent

drm function to update the content protection property state and to generate a uevent is invoked from the intel hdcp property work. Hence whenever kernel changes the property state, userspace will be updated with a uevent. Need a ACK for uevent generating uAPI from userspace. v2: state update

[Intel-gfx] [PATCH v9 4/6] drm/hdcp: update content protection property with uevent

drm function is defined and exported to update a connector's content protection property state and to generate a uevent along with it. Need ACK for the uevent from userspace consumer. v2: Update only when state is different from old one. v3: KDoc is added [Daniel] v4: KDoc is extended bit

[Intel-gfx] [PATCH v9 3/6] drm: uevent for connector status change

DRM API for generating uevent for a status changes of connector's property. This uevent will have following details related to the status change: HOTPLUG=1, CONNECTOR= and PROPERTY= Need ACK from this uevent from userspace consumer. v2: Minor fixes at KDoc comments [Daniel] v3: Check the

[Intel-gfx] [PATCH v9 0/6] HDCP2.2 Phase II

Adding the uAPI support for the HDCP content type is the main focus here. Along with that uevent is implemented for the "Content Protection" state change that got triggered by kernel. v9: KDoc improvements [pekka] Ramalingam C (6): drm: Add Content protection type property drm/i915: Attach

[Intel-gfx] [PATCH v9 1/6] drm: Add Content protection type property

This patch adds a DRM ENUM property to the selected connectors. This property is used for mentioning the protected content's type from userspace to kernel HDCP authentication. Type of the stream is decided by the protected content providers. Type 0 content can be rendered on any HDCP protected

[Intel-gfx] [PATCH v9 2/6] drm/i915: Attach content type property

Attaches the content type property for HDCP2.2 capable connectors. Implements the update of content type from property and apply the restriction on HDCP version selection. Need ACK for content type property from userspace consumer. v2: s/cp_content_type/content_protection_type [daniel]

[Intel-gfx] ✓ Fi.CI.BAT: success for Modular FIA (rev2)

== Series Details == Series: Modular FIA (rev2) URL : https://patchwork.freedesktop.org/series/63175/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13569 Summary --- **SUCCESS** No regressions

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/oa: Reconfigure contexts on the fly (rev3)

== Series Details == Series: series starting with [1/2] drm/i915/oa: Reconfigure contexts on the fly (rev3) URL : https://patchwork.freedesktop.org/series/63362/ State : success == Summary == CI Bug Log - changes from CI_DRM_6429_full -> Patchwork_13561_full

[Intel-gfx] [PATCH v2 1/4] drm/i915: make new intel_tc.c use uncore accessors

Let's make the just created intel_tc.c already follow the trend of using i915 instead of dev_priv and calling the intel_uncore_*() functions. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_tc.c | 57 ++--- 1 file changed, 31 insertions(+), 26

[Intel-gfx] [PATCH v2 3/4] drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c

PORT_TX_DFLEXDPMLE1 is a FIA register so move it to intel_tc.c where we access other FIA registers. In Tiger Lake we have multiple/modular FIAs so it makes sense to start moving all access to their registers to a common place. While at it, make it clear that we will only ever call this function

[Intel-gfx] [PATCH v2 0/4] Modular FIA

v2: - Fix sparse warning - Do not try to make header self-contained - Fix coding style while moving code Anusha Srivatsa (1): drm/i915: Add modular FIA Lucas De Marchi (3): drm/i915: make new intel_tc.c use uncore accessors drm/i915: fix include order in intel_tc.* drm/i915: move

[Intel-gfx] [PATCH v2 2/4] drm/i915: fix include order in intel_tc.*

Make intel_tc.h the first include so we guarantee it's self-contained. Sort the rest. Same principle applies for includes in the header. v2: don't make intel_tc.h be the first include Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_tc.c | 2 +-

[Intel-gfx] [PATCH v2 4/4] drm/i915: Add modular FIA

From: Anusha Srivatsa Some platforms may have Modular FIA. If Modular FIA is used in the SOC, then Display Driver will access the additional instances of FIA based on pre-assigned offset in GTTMADDR space. Each Modular FIA instance has its own IOSF Sideband Port ID and it houses only 2 Type-C

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Try to fix encoder possible_clones/crtc

== Series Details == Series: drm: Try to fix encoder possible_clones/crtc URL : https://patchwork.freedesktop.org/series/63399/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13568 Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Reorder error cleanup for whitelist checking (rev2)

== Series Details == Series: drm/i915/selftests: Reorder error cleanup for whitelist checking (rev2) URL : https://patchwork.freedesktop.org/series/63394/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13567

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Explicitly track active fw_domain timers (rev3)

== Series Details == Series: drm/i915: Explicitly track active fw_domain timers (rev3) URL : https://patchwork.freedesktop.org/series/63331/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13566 Summary

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Fill in a little more of the dummy fence

== Series Details == Series: drm/i915/selftests: Fill in a little more of the dummy fence URL : https://patchwork.freedesktop.org/series/63365/ State : success == Summary == CI Bug Log - changes from CI_DRM_6429_full -> Patchwork_13560_full

[Intel-gfx] [PATCH v2 12/14] drm/i915: s/crtc_mask/pipe_mask/

From: Ville Syrjälä Rename the encoder->crtc_mask to encoder->pipe_mask to better reflect what it actually contains. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/icl_dsi.c | 2 +- drivers/gpu/drm/i915/display/intel_crt.c | 4 ++--

Re: [Intel-gfx] [PATCH v8 6/6] drm/hdcp: reference for srm file format

On 2019-07-08 at 13:16:23 +0300, Pekka Paalanen wrote: > On Fri, 5 Jul 2019 06:16:42 +0530 > Ramalingam C wrote: > > > In the kernel documentation, HDCP specifications links are shared as a > > reference for SRM table format. > > > > Signed-off-by: Ramalingam C > > --- > >

[Intel-gfx] [PATCH v2 14/14] drm: Validate encoder->possible_crtcs

From: Ville Syrjälä WARN if the encoder possible_crtcs is effectively empty or contains bits for non-existing crtcs. TODO: Or should we perhapst just filter out any bit for a non-exisiting crtc? Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_encoder.c | 18 ++ 1 file

[Intel-gfx] [PATCH v2 13/14] drm: Validate encoder->possible_clones

From: Ville Syrjälä Many drivers are populating encoder->possible_clones wrong. Let's persuade them to get it right by adding some loud WARNs. We'll cross check the bits between any two encoders. So either both encoders can clone with the other, or neither can. We'll also complain about

[Intel-gfx] [PATCH v2 10/14] drm/i915: Clean up encoder->crtc_mask setup

From: Ville Syrjälä Use BIT(pipe) for better legibility when populating the crtc_mask for encoders. Also remove the redundant possible_crtcs setup for the TV encoder. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crt.c | 4 ++--

[Intel-gfx] [PATCH v2 11/14] drm/i915: Simplfy LVDS crtc_mask setup

From: Ville Syrjälä We don't need to special case PCH vs. gen4 when setting up the LVDS crtc_mask. Just claim pipes A|B|C work and intel_encoder_crtcs() drop out any crtc that doesn't exist. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_lvds.c | 4 +--- 1 file changed, 1

[Intel-gfx] [PATCH v2 07/14] drm/i915: Polish possible_clones setup

From: Ville Syrjälä Replace the hand rolled stuff with drm_encoder_mask() when populating possible_clones, and rename the function to intel_encoder_possible_clones() to make it clear what it's used for. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 13

[Intel-gfx] [PATCH v2 09/14] drm/i915: Fix DP-MST crtc_mask

From: Ville Syrjälä Each fake MST encoder is tied to a specific pipe. Fix the encoder's crtc_mask to reflect that fact. Reviewed-by: Dhinakaran Pandiyan Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[Intel-gfx] [PATCH v2 06/14] drm/imx: Remove the bogus possible_clones setup

From: Ville Syrjälä It's not at all clear what cloning options this driver supports. So let's just clear possible_clones instead of setting it to some bogus value. Cc: Philipp Zabel Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/imx/imx-drm-core.c | 2 +- 1 file changed, 1 insertion(+), 1

[Intel-gfx] [PATCH v2 08/14] drm/i915: Populate possible_crtcs correctly

From: Ville Syrjälä Don't advertize non-exisiting crtcs in the encoder possible_crtcs bitmask. Reviewed-by: Dhinakaran Pandiyan Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH v2 05/14] drm/exynos: Use drm_encoder_mask()

From: Ville Syrjälä Replace the hand rolled encoder bitmask thing with drm_encoder_mask() Cc: Inki Dae Cc: Joonyoung Shim Cc: Seung-Woo Kim Cc: Kyungmin Park Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/exynos/exynos_drm_drv.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)

[Intel-gfx] [PATCH v2 04/14] drm/sti: Try to fix up the tvout possible clones

From: Ville Syrjälä The current possible_clones setup doesn't look sensible. I'm assuming the 0 and 1 are supposed to refer to the indexes of the hdmi and hda encoders? So it kinda looks like we want hda+hdmi cloning, but then dvo also claims to be cloneable with hdmi, but hdmi won't

[Intel-gfx] [PATCH v2 03/14] drm/sti: Remove pointless casts

From: Ville Syrjälä There's no point in the cast for accessing the base class. Just take the address of the struct instead. Cc: Benjamin Gaignard Cc: Vincent Abriou Acked-by: Benjamin Gaignard Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/sti/sti_tvout.c | 6 +++--- 1 file changed, 3

[Intel-gfx] [PATCH v2 01/14] drm: Include the encoder itself in possible_clones

From: Ville Syrjälä The docs say possible_clones should always include the encoder itself. Since most drivers don't want to deal with the complexities of cloning let's allow them to set possible_clones=0 and instead we'll fix that up in the core. We can't put this special case into

[Intel-gfx] [PATCH v2 00/14] drm: Try to fix encoder possible_clones/crtc

From: Ville Syrjälä Resurrecting my possible_clones/crtcs cleanup from ~1 year ago. Some prep work from the previous posting did get merged in the meantime. I have a feeling the WARNs from the new validation code may end up triggering on some drivers, but I don't imagine this stuff would get

[Intel-gfx] [PATCH v2 02/14] drm/gma500: Sanitize possible_clones

From: Ville Syrjälä I doubt the DP+DP and SDVO+SDVO cloning works for this driver. i915 at least doesn't do those. Truthfully there could be some very specific circumstances where some of them would do doable, but genereally it's too much pain to deal with so we've chose not to bother. Let's use

Re: [Intel-gfx] [PATCH v8 4/6] drm/hdcp: update content protection property with uevent

On 2019-07-08 at 13:09:14 +0300, Pekka Paalanen wrote: > On Fri, 5 Jul 2019 06:16:40 +0530 > Ramalingam C wrote: > > > drm function is defined and exported to update a connector's > > content protection property state and to generate a uevent along > > with it. > > > > Need ACK for the uevent

Re: [Intel-gfx] [PATCH v8 1/6] drm: Add Content protection type property

On 2019-07-08 at 12:59:59 +0300, Pekka Paalanen wrote: > On Mon, 8 Jul 2019 12:52:17 +0300 > Pekka Paalanen wrote: > > > On Fri, 5 Jul 2019 06:16:37 +0530 > > Ramalingam C wrote: > > > > > This patch adds a DRM ENUM property to the selected connectors. > > > This property is used for

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Reorder error cleanup for whitelist checking

Chris Wilson writes: > Reorder the error paths so that we unwind all the locals from any error > path and so avoid setting off divers alarum in case we find an error in > case we find an error. Divers alarum got past me. But for finding an error in case we find error: It is fitting enough that

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Reorder error cleanup for whitelist checking

== Series Details == Series: drm/i915/selftests: Reorder error cleanup for whitelist checking URL : https://patchwork.freedesktop.org/series/63394/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13565

[Intel-gfx] [CI] drm/i915: Explicitly track active fw_domain timers

Stop guessing over whether we have an extra wakeref held by the delayed fw put, and track it explicitly for the sake of debug. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_uncore.c | 15 ---

Re: [Intel-gfx] [PATCH] drm/i915: Explicitly track active fw_domain timers

Quoting Mika Kuoppala (2019-07-08 16:40:30) > Chris Wilson writes: > > > Stop guessing over whether we have an extra wakeref held by the delayed > > fw put, and track it explicitly for the sake of debug. > > > > Signed-off-by: Chris Wilson > > Cc: Tvrtko Ursulin > > --- > >

  1   2   >