== Series Details ==
Series: series starting with [01/23] drm/i915: Move aliasing_ppgtt underneath
its i915_ggtt
URL : https://patchwork.freedesktop.org/series/64128/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6543_full -> Patchwork_13730_full
== Series Details ==
Series: uC fw path unification + misc clean-up (rev2)
URL : https://patchwork.freedesktop.org/series/64039/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6543 -> Patchwork_13731
Summary
---
== Series Details ==
Series: uC fw path unification + misc clean-up (rev2)
URL : https://patchwork.freedesktop.org/series/64039/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/uc: Unify uC platform check
Okay!
Commit: drm/i915/uc: Unify uC
== Series Details ==
Series: uC fw path unification + misc clean-up (rev2)
URL : https://patchwork.freedesktop.org/series/64039/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eb041c6704a9 drm/i915/uc: Unify uC platform check
e49692394e57 drm/i915/uc: Unify uC FW selection
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/64103/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6543_full -> Patchwork_13729_full
Summary
---
The gt is our new central structure for uc-related code, so we can use
that instead of jumping back to i915 via the fw object. Since we have it
in the upload function it is easy to pass it through the lower levels of
the xfer process instead of continuosly jumping via uc_fw->uc->gt, which
will
All the GuC objects are perma-pinned, so their offset can't change at
runtime. We can therefore set (and log!) the parameters only once during
boot.
Suggested-by: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
---
The way we copy the RSA is the same for GuC and HuC, so we can move the
logic in a common function. this will also make any update needed for
local memory easier.
v2: return the number of copied bytes and check it (Chris)
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson #v1
---
Compared to v1 I've pushed a bith further with the fe selection
unification, moving to a unified list for both GuC and HuC. Checkpatch
isn't however too happy with the macros involved!
Apart for the above I've mainly addressed review feedback.
Cc: Michal Wajdeczko
Cc: Chris Wilson
Daniele
We have several HAS_* checks for GuC and HuC but we mostly use HAS_GUC
and HAS_HUC, with only 1 exception. Since our HW always has either
both uC or neither of them, just replace all the checks with a unified
HAS_UC.
v2: use HAS_GT_UC (Michal)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal
The binary is perma-pinned and the rsa is not going to change, so copy
it only once and not on every load.
v2: onion unwind (Chris)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Fernando Pacheco
Reviewed-by: Chris Wilson #v1
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 27
The way we load the firmwares is the same for both GuC and HuC, the only
difference is in the wopcm destination address and the dma flags, so we
easily can move the logic to a common function and pass in offset and
flags. The only other difference in the uplaod path are some the extra
steps that
We currently track fetch and load status separately, but the 2 are
actually sequential in the uc lifetime (fetch must complete before we
can attempt the load!). Unifying the 2 variables we can better follow
the sequential states and improve our trackng of the uC state.
Also, sprinkle some
Instead of having 2 identical functions for GuC and HuC firmware
selection, we can unify the selection logic and just use different lists
based on FW type.
Note that the revid is not relevant for current blobs, but the upcoming
CML will be identified as CFL rev 5, so by considering the revid
On 07/23/2019 06:37 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-07-23 12:31:57)
>> To enable vgpu pv features, we need to setup a shared memory page
>> which will be used for data exchange directly accessed between both
>> guest and backend i915 driver to avoid emulation trap cost.
>>
>>
On 07/23/2019 05:30 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-07-23 12:31:56)
>> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c
>> b/drivers/gpu/drm/i915/i915_vgpu.c
>> index dbd1fa3..9b37dd1 100644
>> --- a/drivers/gpu/drm/i915/i915_vgpu.c
>> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
>>
Chris Wilson writes:
> Quoting Tvrtko Ursulin (2019-07-22 12:41:36)
>>
>> On 20/07/2019 15:31, Chris Wilson wrote:
>> > Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as
>> > the machine stops responding milliseconds after receipt of the reset
>> > request [GDRT]. By
== Series Details ==
Series: drm/i915/huc: fix status check
URL : https://patchwork.freedesktop.org/series/64102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6541_full -> Patchwork_13728_full
Summary
---
-
-/* For now, anything with a GuC has also HuC */
-#define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
+#define HAS_UC(dev_priv) (INTEL_INFO(dev_priv)->has_uc)
time to use i915 instead of dev_priv
ok
I've decided against this in
== Series Details ==
Series: series starting with [1/4] drm/i915: Move aliasing_ppgtt underneath its
i915_ggtt (rev3)
URL : https://patchwork.freedesktop.org/series/64068/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6541_full -> Patchwork_13727_full
== Series Details ==
Series: series starting with [01/23] drm/i915: Move aliasing_ppgtt underneath
its i915_ggtt
URL : https://patchwork.freedesktop.org/series/64128/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6543 -> Patchwork_13730
== Series Details ==
Series: series starting with [01/23] drm/i915: Move aliasing_ppgtt underneath
its i915_ggtt
URL : https://patchwork.freedesktop.org/series/64128/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Move aliasing_ppgtt
== Series Details ==
Series: series starting with [01/23] drm/i915: Move aliasing_ppgtt underneath
its i915_ggtt
URL : https://patchwork.freedesktop.org/series/64128/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5142c7938082 drm/i915: Move aliasing_ppgtt underneath its
Remove the raw i915_active_request tracking in favour of the higher
level i915_active tracking for the sole purpose of making the lockless
transition easier in later patches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_overlay.c | 129 +--
Move the active tracking for the frontbuffer operations out of the
i915_gem_object and into its own first class (refcounted) object. In the
process of detangling, we switch from low level request tracking to the
easier i915_active -- with the plan that this avoids any potential
atomic callbacks as
Convert the list manipulation of active to use spinlocks so that we can
perform the updates from underneath a quick interrupt callback.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c| 10 --
As every i915_active_request should be serialised by a dedicated lock,
i915_active consists of a tree of locks; one for each node. Markup up
the i915_active_request with what lock is supposed to be guarding it so
that we can verify that the serialised updated are indeed serialised.
Signed-off-by:
Lift moving the timeline to/from the active_list on enter/exit in order
to shorten the active tracking span in comparison to the existing
pin/unpin.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 1 -
drivers/gpu/drm/i915/gt/intel_context.c | 2 +
We use timeline->mutex to protect modifications to
context->active_count, and the associated enable/disable callbacks.
Due to complications with engine-pm barrier there is a path where we used
a "superlock" to provide serialised protect and so could not
unconditionally assert with lockdep that it
In the next patch, we would like to couple into the engine wakeref to
free the batch pool on idling. The caveat here is that we therefore want
to track the engine wakeref more precisely and to hold it instead of the
broader GT wakeref as we process the ioctl.
v2: Avoid introducing odd semantics
Modifying a remote context requires careful serialisation with requests
on that context, and that serialisation requires us to take their
timeline->mutex. Make it so.
Note that while struct_mutex rules, we can't create more than one
request in parallel, but that age is soon coming to an end.
v2:
Skip printing out idle engines that did not contribute to the GPU hang.
As the number of engines gets ever larger, we have increasing noise in
the error state where typically there is only one guilty request on one
engine that we need to inspect.
Signed-off-by: Chris Wilson
---
The shrinker cannot touch objects used by the contexts (logical state
and ring). Currently we mark those as "pin_global" to let the shrinker
skip over them, however, if we remove them from the shrinker lists
entirely, we don't event have to include them in our shrink accounting.
By keeping the
The aliasing_ppgtt provides a PIN_USER alias for the global gtt, so move
it under the i915_ggtt to simplify later transformations to enable
intel_context.vm.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 2
We only compute the lrc_descriptor() on pinning the context, i.e.
infrequently, so we do not benefit from storing the template as the
addressing mode is also fixed for the lifetime of the intel_context.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 28
Track the currently bound address space used by the HW context. Minor
conversions to use the local intel_context.vm are made, leaving behind
some more surgery required to make intel_context the primary through the
selftests.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
Now that we have a compact tree representation for uabi engines, make
use of it for walking all user engines from catchall user interfaces
like debugfs and capabilities.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++---
We were using the last_fence to track the last request that used this
vma that might be interpreted by a fence register and forced ourselves
to wait for this request before modifying any fence register that
overlapped our vma. Due to requirement that we need to track any XY_BLT
command, linear or
Use the same mechanism to determine if a backend engine exists for a
uabi mapping as used internally.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
In preparation for removing struct_mutex from around context retirement,
we need to make timeline pinning safe. Since multiple engines/contexts
can share a single timeline, it needs to be protected by a mutex.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 27
Push the ring creation flags from the outer GEM context to the inner
intel_cotnext to avoid an unsightly back-reference from inside the
backend.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 +--
.../gpu/drm/i915/gem/i915_gem_context_types.h
To maintain a fast lookup from a GT centric irq handler, we want the
engine lookup tables on the intel_gt. To avoid having multiple copies of
the same multi-dimension lookup table, move the generic user engine
lookup into an rbtree (for fast and flexible indexing).
v2: Split uabi_instance cf
This giant switch has tendrils all other the struct and does not fit
into the rest of the driver bring up and control of i915_drv.c. Push it
to one side so that it can grow in peace.
Signed-off-by: Chris Wilson
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile| 1 +
Recently discovered in commit bdae33b8b82b ("drm/i915: Use maximum write
flush for pwrite_gtt") was that we needed to our full write barrier
before changing the GGTT PTE to ensure that our indirect writes through
the GTT landed before the PTE changed (and the writes end up in a
different page).
Forgo the struct_mutex requirement for request retirement as we have
been transitioning over to only using the timeline->mutex for
controlling the lifetime of a request on that timeline.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 183 ++
Switch to tracking activity via i915_active on individual nodes, only
keeping a list of retired objects in the cache, and reaping the cache
when the engine itself idles.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 2 +-
== Series Details ==
Series: series starting with drm/vblank: Document and fix vblank count barrier
semantics (rev2)
URL : https://patchwork.freedesktop.org/series/63949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6540_full -> Patchwork_13725_full
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/64103/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6543 -> Patchwork_13729
Summary
---
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/64103/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4df637a232fe drm/i915: Use variable for debugfs device status
d82073ffa3eb drm/i915: Add function to set
Quoting Chris Wilson (2019-07-23 17:25:17)
> Quoting Chuhong Yuan (2019-07-23 11:39:16)
> > Instead of using to_pci_dev + pci_get_drvdata,
> > use dev_get_drvdata to make code simpler.
> >
> > Signed-off-by: Chuhong Yuan
>
> That cuts out some circumlocution,
> Reviewed-by: Chris Wilson
And
== Series Details ==
Series: mei: Abort writes if incomplete after 1s
URL : https://patchwork.freedesktop.org/series/64073/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6539_full -> Patchwork_13723_full
Summary
---
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Michel Thierry
>
> Enable Small PL for power benefit.
>
> Signed-off-by: Michel Thierry
> Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
>
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Tvrtko Ursulin
>
> Hide the details of MOCS setup from i915_gem by moving both current
> calls
> into one in intel_mocs_init.
>
> Cc: Stuart Summers
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Lucas De Marchi
Quoting Chuhong Yuan (2019-07-23 11:39:16)
> Instead of using to_pci_dev + pci_get_drvdata,
> use dev_get_drvdata to make code simpler.
>
> Signed-off-by: Chuhong Yuan
That cuts out some circumlocution,
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx
Quoting Chris Wilson (2019-07-23 16:41:07)
> Quoting Daniele Ceraolo Spurio (2019-07-23 16:37:33)
> > Fix botched refactoring of the code that uncorrectly split a check on a
> > bool, treating it as a u32.
> >
> > Reported-by: Dan Carpenter
> > Fixes: 84b1ca2f0e68 ("drm/i915/uc: prefer intel_gt
The intent of the test is to exercise that each channel in the engine[]
is an independent context/ring/timeline. It setups 64 channels pointing
to rcs0 and then submits one request to each in turn waiting on a
timeline that will force them to run out of submission order. They can
only run in fence
As we never officially write to the scratch buffer, the kernel will
leave it in the CPU read domain upon execution. Our attempt to
invalidate the CPU cache on !llc is therefore skipped as the kernel
doesn't believe the backing store has been invalidated. Use a WC mmap to
avoid the CPU cache for
== Series Details ==
Series: drm/i915/huc: fix status check
URL : https://patchwork.freedesktop.org/series/64102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6541 -> Patchwork_13728
Summary
---
**SUCCESS**
No
== Series Details ==
Series: series starting with [1/4] drm/i915: Move aliasing_ppgtt underneath its
i915_ggtt (rev3)
URL : https://patchwork.freedesktop.org/series/64068/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6541 -> Patchwork_13727
On Tue, 2019-07-23 at 10:12 +0100, Chris Wilson wrote:
> If the system is already idle, omit the GEM_TRACE saying we are about
> to
> wait for idle. It looks confusing in the logs to see a continual
> stream
> of wait-for-idle, as one immediately assumes it is stuck in a loop.
>
> Signed-off-by:
Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff
Add a new function to determine whether a particular slice
has a given subslice.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 10 ++
drivers/gpu/drm/i915/intel_device_info.c | 9 -
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git
Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.
This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 1 +
Refactor instdone loops to use the new intel_sseu_has_subslice
function.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 ++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice
Add a new function to set a range of subslices for a
specified slice based on a given mask.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 10 +
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gpu/drm/i915/intel_device_info.c | 53
Add a new parameter, ss_stride, to the runtime info
structure. This is used to mirror the userspace concept
of subslice stride, which is a range of subslices per slice.
This patch simply adds the definition and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers
---
Add a new function to allow each platform to set maximum
slice, subslice, and EU information to reduce code duplication.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 8 +
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gpu/drm/i915/i915_debugfs.c
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice
Use a local variable to find SSEU runtime information
in various debugfs functions.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_debugfs.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
== Series Details ==
Series: drm/i915: Use dev_get_drvdata
URL : https://patchwork.freedesktop.org/series/64088/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6541 -> Patchwork_13726
Summary
---
**FAILURE**
Quoting Daniele Ceraolo Spurio (2019-07-23 16:37:33)
> Fix botched refactoring of the code that uncorrectly split a check on a
> bool, treating it as a u32.
>
> Reported-by: Dan Carpenter
> Fixes: 84b1ca2f0e68 ("drm/i915/uc: prefer intel_gt over i915 in GuC/HuC
> paths")
> Signed-off-by:
Fix botched refactoring of the code that uncorrectly split a check on a
bool, treating it as a u32.
Reported-by: Dan Carpenter
Fixes: 84b1ca2f0e68 ("drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths")
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Chris Wilson
---
Hi Andrej.
On Tue, Jul 23, 2019 at 02:44:50PM +0200, Andrzej Pietrasiewicz wrote:
> Hi Sam,
>
> W dniu 23.07.2019 o 11:05, Sam Ravnborg pisze:
> > Hi Andrzej
> >
> > On Thu, Jul 11, 2019 at 01:26:41PM +0200, Andrzej Pietrasiewicz wrote:
> > > Use the ddc pointer provided by the generic
Quoting Daniele Ceraolo Spurio (2019-07-23 16:08:49)
>
>
> On 7/23/2019 8:00 AM, Dan Carpenter wrote:
> > Hello Daniele Ceraolo Spurio,
> >
> > The patch 84b1ca2f0e68: "drm/i915/uc: prefer intel_gt over i915 in
> > GuC/HuC paths" from Jul 13, 2019, leads to the following static
> > checker
On 7/23/2019 8:00 AM, Dan Carpenter wrote:
Hello Daniele Ceraolo Spurio,
The patch 84b1ca2f0e68: "drm/i915/uc: prefer intel_gt over i915 in
GuC/HuC paths" from Jul 13, 2019, leads to the following static
checker warning:
drivers/gpu/drm/i915/gt/uc/intel_huc.c:173
On 7/23/2019 6:22 AM, Michal Wajdeczko wrote:
On Tue, 23 Jul 2019 01:20:42 +0200, Daniele Ceraolo Spurio
wrote:
+
+#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \
+UC_FW_BLOB(prefix_##_guc, major_, minor_, \
+ __MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_))
+
Hello Daniele Ceraolo Spurio,
The patch 84b1ca2f0e68: "drm/i915/uc: prefer intel_gt over i915 in
GuC/HuC paths" from Jul 13, 2019, leads to the following static
checker warning:
drivers/gpu/drm/i915/gt/uc/intel_huc.c:173 intel_huc_check_status()
warn: masking a bool
On 7/23/2019 4:19 AM, Michal Wajdeczko wrote:
On Tue, 23 Jul 2019 01:20:41 +0200, Daniele Ceraolo Spurio
wrote:
We have several HAS_* checks for GuC and HuC but we mostly use HAS_GUC
and HAS_HUC, with only 1 exception. Since our HW always has either
both uC or neither of them, just replace
== Series Details ==
Series: series starting with drm/vblank: Document and fix vblank count barrier
semantics (rev2)
URL : https://patchwork.freedesktop.org/series/63949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6540 -> Patchwork_13725
Push the ring creation flags from the outer GEM context to the inner
intel_cotnext to avoid an unsightly back-reference from inside the
backend.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 +--
.../gpu/drm/i915/gem/i915_gem_context_types.h
On Tue, 23 Jul 2019 01:20:44 +0200, Daniele Ceraolo Spurio
wrote:
We currently track fetch and load status separately, but the 2 are
actually sequential in the uc lifetime (fetch must complete before we
can attempt the load!). Unifying the 2 variables we can better follow
the sequential
Instead of using to_pci_dev + pci_get_drvdata,
use dev_get_drvdata to make code simpler.
Signed-off-by: Chuhong Yuan
---
drivers/gpu/drm/i915/i915_drv.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
On 22/07/2019 17:28, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-07-22 13:33:14)
On 18/07/2019 08:00, Chris Wilson wrote:
@@ -1113,9 +1121,8 @@ static int set_ppgtt(struct drm_i915_file_private
*file_priv,
set_ppgtt_barrier,
== Series Details ==
Series: series starting with drm/vblank: Document and fix vblank count barrier
semantics (rev2)
URL : https://patchwork.freedesktop.org/series/63949/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
371224e762e2 drm/vblank: Document and fix vblank count
Quoting Tvrtko Ursulin (2019-07-23 14:34:27)
>
> On 22/07/2019 22:46, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-07-22 13:16:38)
> >>
> >> On 18/07/2019 13:42, Chris Wilson wrote:
> >>> As our global unpark/park keep track of the number of active users, we
> >>> can simply move the
== Series Details ==
Series: series starting with [1/4] drm/i915: Move aliasing_ppgtt underneath its
i915_ggtt (rev2)
URL : https://patchwork.freedesktop.org/series/64068/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6540 -> Patchwork_13724
On 22/07/2019 22:46, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-07-22 13:16:38)
On 18/07/2019 13:42, Chris Wilson wrote:
As our global unpark/park keep track of the number of active users, we
can simply move the accounting from the GEM layer to the base GT layer.
It was placed
On Tue, 23 Jul 2019 01:20:42 +0200, Daniele Ceraolo Spurio
wrote:
+
+#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \
+UC_FW_BLOB(prefix_##_guc, major_, minor_, \
+ __MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_))
+
+GUC_FW_BLOB(skl, 33, 0, 0);
+GUC_FW_BLOB(bxt, 33, 0, 0);
Noticed while reviewing code. I'm not sure whether this might or might
not explain some of the missed vblank hilarity we've been seeing. I
think those all go through the vblank completion event, which has
unconditional barriers - it always takes the spinlock. Therefore no
cc stable.
v2:
-
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/uc: Gt-fy uc reset
URL : https://patchwork.freedesktop.org/series/64067/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6537_full -> Patchwork_13720_full
== Series Details ==
Series: mei: Abort writes if incomplete after 1s
URL : https://patchwork.freedesktop.org/series/64073/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6539 -> Patchwork_13723
Summary
---
On 23/07/2019 12:47, Chris Wilson wrote:
Cometlake is yet another Skylake refresh and used the same mocs
registers.
Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=37
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
lib/intel_chipset.h| 3 ++-
Hi Sam,
W dniu 23.07.2019 o 11:05, Sam Ravnborg pisze:
Hi Andrzej
On Thu, Jul 11, 2019 at 01:26:41PM +0200, Andrzej Pietrasiewicz wrote:
Use the ddc pointer provided by the generic connector.
Signed-off-by: Andrzej Pietrasiewicz
---
drivers/gpu/drm/tilcdc/tilcdc_tfp410.c | 1 +
1 file
== Series Details ==
Series: mei: Abort writes if incomplete after 1s
URL : https://patchwork.freedesktop.org/series/64073/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
96ad9d2ab876 mei: Abort writes if incomplete after 1s
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible
Push the ring creation flags from the outer GEM context to the inner
intel_cotnext to avoid an unsightly back-reference from inside the
backend.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 16 +
.../gpu/drm/i915/gem/i915_gem_context_types.h | 3
== Series Details ==
Series: drm/i915: Squelch nop wait-for-idle trace
URL : https://patchwork.freedesktop.org/series/64066/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6537_full -> Patchwork_13719_full
Summary
---
== Series Details ==
Series: drm/i915/selftests: Let igt_vma_partial et al breathe
URL : https://patchwork.freedesktop.org/series/64071/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6539 -> Patchwork_13722
Summary
---
== Series Details ==
Series: series starting with [1/4] drm/i915: Move aliasing_ppgtt underneath its
i915_ggtt
URL : https://patchwork.freedesktop.org/series/64068/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6539 -> Patchwork_13721
Quoting Tvrtko Ursulin (2019-07-22 12:41:36)
>
> On 20/07/2019 15:31, Chris Wilson wrote:
> > Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as
> > the machine stops responding milliseconds after receipt of the reset
> > request [GDRT]. By disabling the cached atomics, the
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