On 31/07/2019 01:49, Daniele Ceraolo Spurio wrote:
From: Michel Thierry
In Gen11, only even numbered "logical" VDBoxes are hooked up to a SFC
(Scaler & Format Converter) unit. This is not the case in Tigerlake,
where each VDBox can access a SFC.
We will use this information to decide when
On 30/07/2019 16:48, Chris Wilson wrote:
Teach igt_spinner to only use our internal structs, decoupling the
interface from the GEM contexts. This makes it easier to avoid
requiring ce->gem_context back references for kernel_context that may
have them in future.
Signed-off-by: Chris Wilson
---
On 30/07/2019 17:34, Chris Wilson wrote:
My plan for the future is to have kernel contexts no have a GEM context
backpointer (as they will not belong to any GEM context). In a few
places, we use ce->gem_context to simply obtain the i915 backpointer,
which we can use ce->engine->i915 instead.
== Series Details ==
Series: drm/i915: Avoid ce->gem_context->i915
URL : https://patchwork.freedesktop.org/series/64442/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6582_full -> Patchwork_13805_full
Summary
---
== Series Details ==
Series: drm/i915/icl: Remove DDI IO power domain from PG3 power domains
URL : https://patchwork.freedesktop.org/series/64465/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586 -> Patchwork_13816
== Series Details ==
Series: drm/i915/selftests: Pass intel_context to igt_spinner
URL : https://patchwork.freedesktop.org/series/64440/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6582_full -> Patchwork_13804_full
DDI IO power domain are in IO/PHY/AFE power domains.
Which does not require PG3 power well to be enable.
MIPI DSI dual link gets "DDI B" IO power domain reference
count which enables PG3 since "DDI B" IO power domain is
part of PG3 power domain, that makes power leakage in
MIPI DSI dual link use
== Series Details ==
Series: drm/i915/selftests: Pass intel_context to mock_request
URL : https://patchwork.freedesktop.org/series/64439/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6582_full -> Patchwork_13803_full
== Series Details ==
Series: Initial TGL submission changes
URL : https://patchwork.freedesktop.org/series/64461/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586 -> Patchwork_13815
Summary
---
**SUCCESS**
No
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move aliasing_ppgtt underneath
its i915_ggtt
URL : https://patchwork.freedesktop.org/series/64438/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6581_full -> Patchwork_13802_full
On 7/30/2019 2:34 AM, Daniel Vetter wrote:
> On Tue, Jul 30, 2019 at 08:45:57AM +, Koenig, Christian wrote:
>> Yeah, that looks like a good start. Just a couple of random design
>> comments/requirements.
>>
>> First of all please restructure the changes so that you more or less
>> have the
== Series Details ==
Series: Initial TGL submission changes
URL : https://patchwork.freedesktop.org/series/64461/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
74d80bbbdcd2 drm/i915/tgl: add Gen12 default indirect ctx offset
d43424d8627c drm/i915/tgl: add
On 7/30/2019 3:45 AM, Daniel Vetter wrote:
> On Tue, Jul 30, 2019 at 12:24 PM Koenig, Christian
> wrote:
>>
>> Am 30.07.19 um 11:38 schrieb Daniel Vetter:
>>> On Tue, Jul 30, 2019 at 08:45:57AM +, Koenig, Christian wrote:
Snipped the feedback on struct drm_mem_region.
Will be easier to have
Gen12 uses a new indirect ctx offset.
Cc: Lucas De Marchi
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 +
2 files changed, 5
Like Gen11, Gen12 has 11 available bits for the ctx id field. However,
the last value (0x7FF) is reserved to indicate engine idle, so we
need to reduce the maximum number of contexts by 1 compared to Gen11.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Lucas De Marchi
Cc: Chris Wilson
---
The CSB format has been reworked for Gen12 to include information on
both the context we're switching away from and the context we're
switching to. After the change, some of the events don't have their
own bit anymore and need to be inferred from other values in the csb.
One of the context IDs
From: Michel Thierry
In Gen11, only even numbered "logical" VDBoxes are hooked up to a SFC
(Scaler & Format Converter) unit. This is not the case in Tigerlake,
where each VDBox can access a SFC.
We will use this information to decide when the SFC units need to be reset
and also pass it to the
New lrc-related defines, new csb parser and TGL sfc pairing.
There are required changes for the context image as well, I'll send them
separately as I haven't done the math for the lrc size yet.
Cc: Lucas De Marchi
Daniele Ceraolo Spurio (3):
drm/i915/tgl: add Gen12 default indirect ctx
== Series Details ==
Series: DC3CO Support for TGL.
URL : https://patchwork.freedesktop.org/series/64436/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6581_full -> Patchwork_13801_full
Summary
---
**SUCCESS**
No
== Series Details ==
Series: series starting with [v2,1/5] drm/i915/uc: Don't enable communication
twice on resume
URL : https://patchwork.freedesktop.org/series/64459/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6586 -> Patchwork_13814
== Series Details ==
Series: series starting with [v7,1/4] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/64457/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586 -> Patchwork_13813
== Series Details ==
Series: series starting with [1/3] drm/i915/oa: add content to Makefile
URL : https://patchwork.freedesktop.org/series/64427/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6581_full -> Patchwork_13799_full
== Series Details ==
Series: series starting with [v7,1/4] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/64457/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5a3f9ccb3fc9 drm/i915/bdw+: Move misc display IRQ
== Series Details ==
Series: drm/i915/ehl: Don't forget to handle port C's hotplug interrupts (rev2)
URL : https://patchwork.freedesktop.org/series/64452/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586 -> Patchwork_13812
To be called from the top level runtime functions, to hide the
gt-specific bits (mainly related to intel_uc).
v2: rebased
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 12
uC is a subcomponent of GT, so initialize/clean it as part of it. The
wopcm_init_early doesn't have to be happen before the uC one, but since
in other parts of the code we consider WOPCM first do the same for
consistency.
v2: s/cleanup_early/late_release to match the caller
Signed-off-by:
We don't call the init_early function from within the gem code, so we
shouldn't do it for the cleanup either.
v2: while at it, s/gt_cleanup_early/gt_late_release (Chris)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin #v1
---
When coming out of S3/S4 we sanitize and re-init the HW, which includes
enabling communication during uc_init_hw. We therefore don't want to do
that again in uc_resume and can just tell GuC to reload its state.
v2: split uc_resume and uc_runtime_resume to match the suspend
functions and to
The register we write are not WOPCM regs but uC ones related to how
GuC and HuC are going to use the WOPCM, so it makes logical sense
for them to be programmed as part of uc_init_hw. The WOPCM map on the
other side is not uC-specific (although that is our main use-case), so
keep that separate.
== Series Details ==
Series: drm/i915: Report resv_obj allocation failure
URL : https://patchwork.freedesktop.org/series/64450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586 -> Patchwork_13811
Summary
---
Just moving it to reduce the tabs and avoid break code lines.
No behavior changes intended here.
v2:
- Reading misc display IRQ outside of gen8_de_misc_irq_handler() as
other irq handlers (Dhinakaran)
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
A new macro that is going to be added in a further patch will need to
adjust the offset returned by _MMIO_TRANS2(), so here adding
_TRANS2() and moving most of the implementation of _MMIO_TRANS2() to
it and while at it taking the opportunity to rename pipe to trans.
Cc: Rodrigo Vivi
Cc:
PSR registers are a mess, some have the full address while others just
have the additional offset from psr_mmio_base.
For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET +
0x800 and using it makes more difficult for people with an PSR
register address or PSR register name from from
According to PSR2_CTL definition on BSpec there is only one instance
of PSR2_CTL also ICL display overview state that PSR2 is only
supported in EDP transcoder, so now that is possible to have PSR in
any transcoder lets add this hardware restriction.
BSpec: 7713
BSpec: 20584
Cc: Dhinakaran
== Series Details ==
Series: series starting with [1/3] drm/i915/execlists: Always clear
pending requests on reset
URL : https://patchwork.freedesktop.org/series/64426/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6581_full -> Patchwork_13798_full
On Tue, Jul 30, 2019 at 02:30:26PM +0100, Chris Wilson wrote:
> We only compute the lrc_descriptor() on pinning the context, i.e.
> infrequently, so we do not benefit from storing the template as the
> addressing mode is also fixed for the lifetime of the intel_context.
>
> Signed-off-by: Chris
== Series Details ==
Series: drm/i915: remove dangling forward declaration
URL : https://patchwork.freedesktop.org/series/64447/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586 -> Patchwork_13810
Summary
---
== Series Details ==
Series: Don't sanitize enable_guc
URL : https://patchwork.freedesktop.org/series/64446/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586 -> Patchwork_13809
Summary
---
**SUCCESS**
No
We're mostly re-using ICL's interrupt handling on EHL, but we still need
to remember to account for the extra combo port that EHL has. Use TGP's
mask (which includes combo port C) rather than ICP's mask when
appropriate. Let's also skip reading TC-specific registers on this
platform since EHL
On Tue, 2019-07-30 at 14:35 -0700, Matt Roper wrote:
> We're mostly re-using ICL's interrupt handling on EHL, but we still
> need
> to remember to account for the extra combo port that EHL has. Use
> TGP's
> mask (which includes combo port C) rather than ICP's mask when
> appropriate. Let's also
== Series Details ==
Series: series starting with [1/2] drm/i915/oa: add content to Makefile
URL : https://patchwork.freedesktop.org/series/64424/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6581_full -> Patchwork_13797_full
== Series Details ==
Series: Don't sanitize enable_guc
URL : https://patchwork.freedesktop.org/series/64446/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
26060db5e380 drm/i915/uc: Consider enable_guc modparam during fw selection
-:81: CHECK:UNNECESSARY_PARENTHESES:
On Tue, Jul 30, 2019 at 01:42:45PM -0700, Rodrigo Vivi wrote:
Hi Sasha,
Hello!
On Thu, Jul 18, 2019 at 5:45 PM Sasha Levin wrote:
Hi,
[This is an automated email]
Where did you get this patch from? Since stable needs patches merged
This bot grabs them from various mailing lists.
on
We're mostly re-using ICL's interrupt handling on EHL, but we still need
to remember to account for the extra combo port that EHL has. Use TGP's
mask (which includes combo port C) rather than ICP's mask when
appropriate. Let's also skip reading TC-specific registers on this
platform since EHL
Check for viability of store-dword before use.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_schedule.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 4ccacba41..6e8466299 100644
---
The intent of the test is to exercise that each channel in the engine[]
is an independent context/ring/timeline. It setups 64 channels pointing
to rcs0 and then submits one request to each in turn waiting on a
timeline that will force them to run out of submission order. They can
only run in fence
On 7/30/19 7:39 AM, Michal Wajdeczko wrote:
On Tue, 30 Jul 2019 01:47:22 +0200, Daniele Ceraolo Spurio
wrote:
The register we write are not WOPCM regs but uC ones related to how
GuC and HuC are going to use the WOPCM, so it makes logical sense
for them to be programmed as part of
== Series Details ==
Series: drm/i915: make i915_selftest.h self-contained
URL : https://patchwork.freedesktop.org/series/64445/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6585 -> Patchwork_13808
Summary
---
Since commit 64d6c500a384 ("drm/i915: Generalise GPU activity
tracking"), we have been prepared for i915_vma_move_to_active() to fail.
We can take advantage of this to report the failure for allocating the
shared-fence slot in the reservation_object.
Signed-off-by: Chris Wilson
---
== Series Details ==
Series: drm/i915/execlists: Always clear pending requests on reset
URL : https://patchwork.freedesktop.org/series/64423/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6581_full -> Patchwork_13796_full
== Series Details ==
Series: Tiger Lake: MOCS table handling (rev3)
URL : https://patchwork.freedesktop.org/series/64275/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6585 -> Patchwork_13807
Summary
---
**SUCCESS**
Hi Sasha,
On Thu, Jul 18, 2019 at 5:45 PM Sasha Levin wrote:
>
> Hi,
>
> [This is an automated email]
Where did you get this patch from? Since stable needs patches merged
on Linus tree,
shouldn't your scripts run to try backporting only patches from there?
Thanks,
Rodrigo.
>
> This commit has
Hi Daniele,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.3-rc2 next-20190730]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
Fixes: 6b6fa175ec57 ("drm/i915/uc: move uC WOPCM setup in uc_init_hw")
Signed-off-by: kbuild test robot
---
intel_uc.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index
Quoting Michal Wajdeczko (2019-07-30 19:19:02)
> Instead of relying on enable_guc modparam to represent actual
> GuC submission mode, use dedicated flag and look at modparam
> only to check if submission was explicitly disabled by the user.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Daniele
Quoting Michal Wajdeczko (2019-07-30 19:19:01)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> index fe3362fd7706..c8e5ad9807db 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> @@ -50,8 +50,7 @@
== Series Details ==
Series: tests/i915/gem_exec_async: Update with engine discovery
URL : https://patchwork.freedesktop.org/series/64425/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6580_full -> IGTPW_3308_full
Summary
== Series Details ==
Series: drm/i915/ehl: Ungate DDIC and DDID
URL : https://patchwork.freedesktop.org/series/64443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6583 -> Patchwork_13806
Summary
---
**SUCCESS**
Quoting Lucas De Marchi (2019-07-30 19:26:14)
> Commit 20a7f2fc4d7a ("drm/i915: Convert intel_mocs_init_l3cc_table to
> intel_gt") removed the only user.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Commit 20a7f2fc4d7a ("drm/i915: Convert intel_mocs_init_l3cc_table to
intel_gt") removed the only user.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_mocs.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h
Quoting Lucas De Marchi (2019-07-30 19:17:59)
> Fix build breakage:
>
> In file included from :
> ./drivers/gpu/drm/i915/i915_selftest.h:125:1: error: unknown type name ‘bool’
> 125 | bool __igt_timeout(unsigned long timeout, const char *fmt, ...);
> | ^~~~
>
> Signed-off-by: Lucas De
> -Original Message-
> From: Greg KH [mailto:gre...@linuxfoundation.org]
> Sent: Tuesday, July 30, 2019 10:09 AM
> To: Vivi, Rodrigo
> Cc: Nikula, Jani ; Joonas Lahtinen
> ; Souza, Jose ;
> sas...@kernel.org; intel-gfx@lists.freedesktop.org; sta...@vger.kernel.org;
> Pandiyan,
Quoting Michal Wajdeczko (2019-07-30 19:19:03)
> As we already track GuC/HuC uses by other means than modparam
> there is no point in sanitizing it. Just scan modparam for
> major discrepancies between what was requested vs actual.
Note that igt is using this modparam to discover if guc
As we already track GuC/HuC uses by other means than modparam
there is no point in sanitizing it. Just scan modparam for
major discrepancies between what was requested vs actual.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
We want to stop relying on modparam for runtime uC status
Michal Wajdeczko (3):
drm/i915/uc: Consider enable_guc modparam during fw selection
drm/i915/guc: Use dedicated flag to track submission mode
drm/i915/uc: Stop sanitizing enable_guc modparam
drivers/gpu/drm/i915/gt/uc/intel_guc.c
Instead of relying on enable_guc modparam to represent actual
GuC submission mode, use dedicated flag and look at modparam
only to check if submission was explicitly disabled by the user.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
We can use value of enable_guc modparam during firmware path selection
and start using firmware status to see if GuC/HuC is being used.
This is first step to make enable_guc modparam read-only.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
Fix build breakage:
In file included from :
./drivers/gpu/drm/i915/i915_selftest.h:125:1: error: unknown type name ‘bool’
125 | bool __igt_timeout(unsigned long timeout, const char *fmt, ...);
| ^~~~
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_selftest.h | 2 ++
1 file
On Tue, Jul 30, 2019 at 10:51:21AM -0700, José Roberto de Souza wrote:
> Specification states that DDI_CLK_SEL needs to be mapped to MG clock
> even if MG do not exist on EHL, this will ungate those DDIs.
>
> BSpec: 20845
> Cc: Matt Roper
> Cc: Vivek Kasireddy
> Signed-off-by: José Roberto de
From: Tomasz Lis
The MOCS table is published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.
Two of the 3 legacy entries used for gen9 are no longer expected to
These registers have been removed on gen12.
v2: merge common branch for IS_GEN_RANGE(i915, 6, 11)
Signed-off-by: Lucas De Marchi
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_gpu_error.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git
v3 of https://patchwork.freedesktop.org/series/64275/
Changes:
- Fix checkpatch warning on commit message
- Minor change on "drm/i915/tgl: stop using ERROR_GEN6 and DONE_REG"
- Rebase again to be able to apply
Lucas De Marchi (2):
drm/i915/tgl: Move fault registers to their new offset
From: Tvrtko Ursulin
Hide the details of MOCS setup from i915_gem by moving both current calls
into one in intel_mocs_init.
Cc: Stuart Summers
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
Link:
From: Michel Thierry
Until Icelake, each engine had its own set of 64 MOCS registers. In
order to simplify, Tigerlake moves to only 64 Global MOCS registers,
which are no longer part of the engine context. Since these registers
are now global, they also only need to be initialized once.
From
The fault registers moved to another offset. The old location is now
taken by the global MOCS registers, to be added in a follow up change.
Based on previous patches by Michel Thierry .
Signed-off-by: Lucas De Marchi
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_gt.c
Specification states that DDI_CLK_SEL needs to be mapped to MG clock
even if MG do not exist on EHL, this will ungate those DDIs.
BSpec: 20845
Cc: Matt Roper
Cc: Vivek Kasireddy
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 9 -
1 file changed, 8
== Series Details ==
Series: drm/i915: Avoid ce->gem_context->i915
URL : https://patchwork.freedesktop.org/series/64442/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6582 -> Patchwork_13805
Summary
---
**SUCCESS**
Hi Neil.
> > Signed-off-by: Andrzej Pietrasiewicz
> > ---
> > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 40 +++
> > 1 file changed, 20 insertions(+), 20 deletions(-)
> >
...
>
> Reviewed-by: Neil Armstrong
There is now a much simpler v6 of this patch.
Care to take a
On Tue, Jul 30, 2019 at 09:56:59AM -0700, Rodrigo Vivi wrote:
>
> On Tue, Jul 30, 2019 at 06:27:09PM +0200, Greg KH wrote:
> > On Tue, Jul 30, 2019 at 09:22:07AM -0700, Rodrigo Vivi wrote:
> > > On Tue, Jul 30, 2019 at 05:27:24PM +0200, Greg KH wrote:
> > > > On Tue, Jul 30, 2019 at 08:19:08AM
Quoting Tvrtko Ursulin (2019-07-30 16:20:08)
>
> On 30/07/2019 09:04, Ramalingam C wrote:
> > On 2019-07-30 at 13:05:27 +0100, Tvrtko Ursulin wrote:
> >>
> >> On 30/07/2019 04:58, Ramalingam C wrote:
> >>> +bool gem_eb_flags_are_different_engines(unsigned eb_flag1, unsigned
> >>> eb_flag2)
> >>
On Tue, Jul 30, 2019 at 06:27:09PM +0200, Greg KH wrote:
> On Tue, Jul 30, 2019 at 09:22:07AM -0700, Rodrigo Vivi wrote:
> > On Tue, Jul 30, 2019 at 05:27:24PM +0200, Greg KH wrote:
> > > On Tue, Jul 30, 2019 at 08:19:08AM -0700, Rodrigo Vivi wrote:
> > > > Hi Greg,
> > > >
> > > > On Wed, Jul
== Series Details ==
Series: drm/i915/selftests: Pass intel_context to igt_spinner
URL : https://patchwork.freedesktop.org/series/64440/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6582 -> Patchwork_13804
Summary
---
== Series Details ==
Series: drm/i915/selftests: Pass intel_context to mock_request
URL : https://patchwork.freedesktop.org/series/64439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6582 -> Patchwork_13803
Summary
My plan for the future is to have kernel contexts no have a GEM context
backpointer (as they will not belong to any GEM context). In a few
places, we use ce->gem_context to simply obtain the i915 backpointer,
which we can use ce->engine->i915 instead.
Signed-off-by: Chris Wilson
---
On Tue, Jul 30, 2019 at 09:22:07AM -0700, Rodrigo Vivi wrote:
> On Tue, Jul 30, 2019 at 05:27:24PM +0200, Greg KH wrote:
> > On Tue, Jul 30, 2019 at 08:19:08AM -0700, Rodrigo Vivi wrote:
> > > Hi Greg,
> > >
> > > On Wed, Jul 24, 2019 at 10:40:29AM -0700, Rodrigo Vivi wrote:
> > > > On Wed, Jul
On Thu, Jun 27, 2019 at 09:55:59PM +0100, Matthew Auld wrote:
> Support basic eviction for regions.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
So from a very high level this looks like it was largely modelled after
i915_gem_shrink.c and not i915_gem_evict.c
== Series Details ==
Series: drm/i915/selftests: Pass intel_context to igt_spinner
URL : https://patchwork.freedesktop.org/series/64440/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b93d1639435b drm/i915/selftests: Pass intel_context to igt_spinner
-:469: ERROR:SPACING: space
On Tue, Jul 30, 2019 at 03:28:11PM +0100, Matthew Auld wrote:
> On 30/07/2019 10:49, Daniel Vetter wrote:
> > On Thu, Jun 27, 2019 at 09:56:25PM +0100, Matthew Auld wrote:
> > > From: Abdiel Janulgue
> > >
> > > Add a new CPU mmap implementation that allows multiple fault handlers
> > > that
On Tue, Jul 30, 2019 at 05:27:24PM +0200, Greg KH wrote:
> On Tue, Jul 30, 2019 at 08:19:08AM -0700, Rodrigo Vivi wrote:
> > Hi Greg,
> >
> > On Wed, Jul 24, 2019 at 10:40:29AM -0700, Rodrigo Vivi wrote:
> > > On Wed, Jul 24, 2019 at 05:27:42PM +, Souza, Jose wrote:
> > > > On Wed, 2019-07-24
On Thu, Jun 27, 2019 at 09:56:30PM +0100, Matthew Auld wrote:
> From: Abdiel Janulgue
>
> This call will specify which memory region an object should be placed.
>
> Note that changing the object's backing storage should be immediately
> done after an object is created or if it's not yet in use,
Quoting Daniele Ceraolo Spurio (2019-07-30 17:05:19)
>
>
> On 7/30/19 1:14 AM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2019-07-29 23:28:00)
> >> When coming out of S3/S4 we sanitize and re-init the HW, which includes
> >> enabling communication during uc_init_hw. We therefore
On 7/30/19 1:14 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-07-29 23:28:00)
When coming out of S3/S4 we sanitize and re-init the HW, which includes
enabling communication during uc_init_hw. We therefore don't want to do
that again in uc_resume and can just tell GuC to reload
Teach igt_spinner to only use our internal structs, decoupling the
interface from the GEM contexts. This makes it easier to avoid
requiring ce->gem_context back references for kernel_context that may
have them in future.
Signed-off-by: Chris Wilson
---
On Tue, Jul 30, 2019 at 08:19:08AM -0700, Rodrigo Vivi wrote:
> Hi Greg,
>
> On Wed, Jul 24, 2019 at 10:40:29AM -0700, Rodrigo Vivi wrote:
> > On Wed, Jul 24, 2019 at 05:27:42PM +, Souza, Jose wrote:
> > > On Wed, 2019-07-24 at 14:06 +0200, Greg KH wrote:
> > > > On Mon, Jul 22, 2019 at
On 30/07/2019 09:04, Ramalingam C wrote:
On 2019-07-30 at 13:05:27 +0100, Tvrtko Ursulin wrote:
On 30/07/2019 04:58, Ramalingam C wrote:
Legacy execbuf abi tests are prefixed with legacy. New test are added to
run on physical engines accessed through engine discovery.
So legacy tests run on
Hi Greg,
On Wed, Jul 24, 2019 at 10:40:29AM -0700, Rodrigo Vivi wrote:
> On Wed, Jul 24, 2019 at 05:27:42PM +, Souza, Jose wrote:
> > On Wed, 2019-07-24 at 14:06 +0200, Greg KH wrote:
> > > On Mon, Jul 22, 2019 at 04:13:25PM -0700, Dhinakaran Pandiyan wrote:
> > > > A single 32-bit PSR2
On Tue, Jul 30, 2019 at 12:05:13PM +0300, Jani Nikula wrote:
On Mon, 29 Jul 2019, Lucas De Marchi wrote:
Commit e846f0dc57f4 ("kbuild: add support for ensuring headers are
self-contained") replaced the old mechanism we had in i915 to test the
header files are self-contained, but later commits
Quoting Daniele Ceraolo Spurio (2019-07-30 15:56:57)
>
>
> On 7/30/19 1:01 AM, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-07-30 08:19:18)
> >>
> >> On 30/07/2019 00:47, Daniele Ceraolo Spurio wrote:
> >>> We don't call the init_early function from within the gem code, so we
> >>>
Modernise the mock_request factory to take intel_context not a (GEM
context, intel_engine_cs) tuple.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_request.c | 38 +++
drivers/gpu/drm/i915/selftests/mock_request.c | 6 +--
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move aliasing_ppgtt underneath
its i915_ggtt
URL : https://patchwork.freedesktop.org/series/64438/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6581 -> Patchwork_13802
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