== Series Details ==
Series: drm/i915/tgl: Lower cdclk for sub 4k resolutions
URL : https://patchwork.freedesktop.org/series/65475/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6748_full -> Patchwork_14100_full
Summary
== Series Details ==
Series: drm/i915/gtt: Relax assertion for pt_used
URL : https://patchwork.freedesktop.org/series/65518/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14116
Summary
---
On 2019-08-20 at 15:33:23 -0700, José Roberto de Souza wrote:
> PSR registers are a mess, some have the full address while others just
> have the additional offset from psr_mmio_base.
>
> For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET +
> 0x800 and using it makes more difficult
When inserting the final level PTE, we check that we are not overflowing
the page table (checking that pt_used does not exceed the size of the
table). However, we have to allow for every other PTE to be pinned by a
simultaneous removal thread (as on remove we bump the pt_used counter
before
Hi all,
Today's linux-next merge of the iommu tree got a conflict in:
drivers/gpu/drm/panfrost/panfrost_mmu.c
between commit:
187d2929206e ("drm/panfrost: Add support for GPU heap allocations")
from the drm-misc tree and commit:
a2d3a382d6c6 ("iommu/io-pgtable: Pass struct
On 2019-08-20 at 15:33:24 -0700, José Roberto de Souza wrote:
> According to PSR2_CTL definition in BSpec there is only one instance
> of PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2
> on TRANSCODER_EDP while on TGL PSR2 is only supported by
> TRANSCODER_A.
>
> Since BDW PSR
== Series Details ==
Series: series starting with [1/2] drm/i915: Don't deballoon unused ggtt
drm_mm_node in linux guest (rev2)
URL : https://patchwork.freedesktop.org/series/65450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14115
On 2019.08.20 13:46:17 +0800, Xiong Zhang wrote:
> The following call trace may exist in linux guest dmesg when guest i915
> driver is unloaded.
> [ 90.776610] [drm:vgt_deballoon_space.isra.0 [i915]] deballoon space: range
> [0x0 - 0x0] 0 KiB.
> [ 90.776621] BUG: unable to handle kernel NULL
vgpu ballon info consists of four drm_mm_node which is used to reserve
ggtt space, then linux guest won't use these reserved ggtt space.
Each vgpu has its own ballon info, so move ballon info into
i915_virtual_gpu structure.
v2: Fix dim PARENTHESIS_ALIGNMENT check warning
Signed-off-by: Xiong
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65509/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14114
Summary
---
On Mon, Aug 19, 2019 at 06:23:27PM -0700, Daniele Ceraolo Spurio wrote:
> First uc firmware release for EHL.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Matt Roper
> Cc: Anusha Srivatsa
> Cc: Michal Wajdeczko
The new firmwares load properly with this patch.
Tested-by: Matt Roper
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65509/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Use variable for debugfs device status
Okay!
Commit: drm/i915: Add
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65509/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f87889b5f343 drm/i915: Use variable for debugfs device status
c0f971db0755 drm/i915: Add function to set
== Series Details ==
Series: drm/dp/dsc: Add Support for all BPCs supported by TGL (rev5)
URL : https://patchwork.freedesktop.org/series/63526/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14113
Summary
== Series Details ==
Series: series starting with [v8,1/3] drm/i915/psr: Make PSR registers relative
to transcoders
URL : https://patchwork.freedesktop.org/series/65507/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14112
On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote:
> From: Michel Thierry
>
> Workaround no longer needed (plus L3_LRA_1_GPGPU doesn't exist).
Took a look at this one today and I can at least say this register is
not present at the previous location. I didn't have any luck finding a
== Series Details ==
Series: series starting with [v8,1/3] drm/i915/psr: Make PSR registers relative
to transcoders
URL : https://patchwork.freedesktop.org/series/65507/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
180c73435134 drm/i915/psr: Make PSR registers relative to
On Tue, Aug 20, 2019 at 03:01:38PM -0700, José Roberto de Souza wrote:
> On TGL some registers moved from DDI to transcoder and the
> DisplayPort training sequence has a separate BSpec page.
>
> I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but
> it was becoming really hard to
Refactor instdone loops to use the new intel_sseu_has_subslice
function.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 ++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
Use a local variable to find SSEU runtime information
in various debugfs functions.
v2: Remove extra line breaks per feedback from Chris
Signed-off-by: Stuart Summers
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 +++---
1 file changed, 11
When setting up subslice_mask, instead of operating on the slice
array directly, use a local variable to start bits per slice, then
use this to set the per slice array in one step.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/intel_device_info.c | 49 +---
1 file
Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.
This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers
Reviewed-by: Chris Wilson
---
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice
Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_debugfs.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git
Add a subslice stride calculation when setting subslices. This
aligns more closely with the userspace expectation of the subslice
mask structure.
v2: Use local variable for subslice_mask on HSW and
clean up a few other subslice_mask local variable
changes
v3: Add GEM_BUG_ON for ss_stride
Add a new parameter, ss_stride, to the runtime info
structure. This is used to mirror the userspace concept
of subslice stride, which is a range of subslices per slice.
This patch simply adds the definition and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers
Add a new function to determine whether a particular slice
has a given subslice.
Signed-off-by: Stuart Summers
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 16
drivers/gpu/drm/i915/intel_device_info.c | 9 -
2 files changed, 20
Add a new function to allow each platform to set maximum
slice, subslice, and EU information to reduce code duplication.
Signed-off-by: Stuart Summers
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 8 +
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
Add a new function to set a set of subslices for a given
slice.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 6 ++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +++
drivers/gpu/drm/i915/intel_device_info.c | 18 +++---
3 files changed, 20
Reviewed-by: Lyude Paul
On Tue, 2019-08-20 at 19:16 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're not allowed to create new properties after device registration
> so for MST connectors we need to either create the max_bpc property
> earlier, or we reuse one we already have. Let's
On Tue, Aug 20, 2019 at 03:33:25PM -0700, Jose Souza wrote:
No need to unmask PSR interrutpion if PSR is not enabled, better move
the call to intel_psr_enable_source().
v2: Renamed intel_psr_irq_control() to psr_irq_control() (Lucas)
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Signed-off-by:
Sent the patch again with CI tag, to check the results.
Anusha
> -Original Message-
> From: Navare, Manasi D
> Sent: Monday, August 19, 2019 4:06 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha
> Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp/dsc: Add Support
DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.
v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
and use the value directly.(More such defines can be
PSR registers are a mess, some have the full address while others just
have the additional offset from psr_mmio_base.
For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET +
0x800 and using it makes more difficult for people with an PSR
register address or PSR register name from from
No need to unmask PSR interrutpion if PSR is not enabled, better move
the call to intel_psr_enable_source().
v2: Renamed intel_psr_irq_control() to psr_irq_control() (Lucas)
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
According to PSR2_CTL definition in BSpec there is only one instance
of PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2
on TRANSCODER_EDP while on TGL PSR2 is only supported by
TRANSCODER_A.
Since BDW PSR is allowed on any port, but we need to restrict by
transcoder.
v8:
== Series Details ==
Series: Tiger Lake batch 3 (rev4)
URL : https://patchwork.freedesktop.org/series/65290/
State : failure
== Summary ==
Applying: drm/i915/tgl: disable DDIC
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_display.c
Falling back to
On Tue, 2019-08-20 at 13:29 -0700, Lucas De Marchi wrote:
> On Sat, Aug 17, 2019 at 02:38:29AM -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza
> >
> > No need to unmask PSR interrutpion if PSR is not enabled, better
> > move
> > the call to intel_psr_enable_source().
> >
> > Cc:
On TGL some registers moved from DDI to transcoder and the
DisplayPort training sequence has a separate BSpec page.
I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but
it was becoming really hard to follow, so a new and cleaner function
for TGL was added with comments of all
On Tue, 2019-08-20 at 13:16 -0700, Lucas De Marchi wrote:
> On Sat, Aug 17, 2019 at 02:38:27AM -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza
> >
> > PSR registers are a mess, some have the full address while others
> > just
> > have the additional offset from psr_mmio_base.
> >
== Series Details ==
Series: drm/i915: disable set/get_tiling ioctl on gen12+ (rev2)
URL : https://patchwork.freedesktop.org/series/65495/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14110
Summary
Hi Maarten,
For this patch, you want me to modify it such that if (slave && needs_modeset)
then
dont do anything since the slave update crtc and pipe an dplane updates will
happen with master.
So if(master && needs_modeset) {
obtain slaves from slave_mask
obtain corresponding slave crtc state
== Series Details ==
Series: drm/i915: Be defensive when starting vma activity
URL : https://patchwork.freedesktop.org/series/65471/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14098_full
Summary
On 8/20/19 12:54 PM, Daniel Vetter wrote:
The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
supported any of the fancy new tiling formats, which means userspace
also stopped using the magic side-channel this provides.
This would totally break a lot of the igts, but
On Sat, Aug 17, 2019 at 02:38:43AM -0700, Lucas De Marchi wrote:
From: Michel Thierry
HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_WAKEUP properly to
wake up proper subwell.
During driver load, init_clock_gating
== Series Details ==
Series: drm/i915: disable set/get_tiling ioctl on gen12+ (rev2)
URL : https://patchwork.freedesktop.org/series/65495/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5281445913b8 drm/i915: disable set/get_tiling ioctl on gen12+
-:56:
On Sat, Aug 17, 2019 at 02:38:53AM -0700, Lucas De Marchi wrote:
From: Michel Thierry
GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.
HSD: 399379
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by:
On Sat, Aug 17, 2019 at 02:38:29AM -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
No need to unmask PSR interrutpion if PSR is not enabled, better move
the call to intel_psr_enable_source().
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
On Tue, Aug 20, 2019 at 10:19:01AM +0200, Daniel Vetter wrote:
> In some special cases we must not block, but there's not a
> spinlock, preempt-off, irqs-off or similar critical section already
> that arms the might_sleep() debug checks. Add a non_block_start/end()
> pair to annotate these.
>
>
On Sat, Aug 17, 2019 at 02:38:28AM -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
According to PSR2_CTL definition in BSpec there is only one instance of
PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2 on
TRANSCODER_EDP while on TGL PSR2 is only supported by
On Sat, Aug 17, 2019 at 02:38:27AM -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
PSR registers are a mess, some have the full address while others just
have the additional offset from psr_mmio_base.
For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET +
0x800 and
== Series Details ==
Series: drm/i915: Serialize insertion into the file->mm.request_list
URL : https://patchwork.freedesktop.org/series/65468/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14097_full
The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
supported any of the fancy new tiling formats, which means userspace
also stopped using the magic side-channel this provides.
This would totally break a lot of the igts, but they're already broken
for the same reasons as
== Series Details ==
Series: drm/i915: disable set/get_tiling ioctl on gen12+
URL : https://patchwork.freedesktop.org/series/65495/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6749 -> Patchwork_14109
Summary
---
== Series Details ==
Series: drm/i915: disable set/get_tiling ioctl on gen12+
URL : https://patchwork.freedesktop.org/series/65495/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7f41e4bbdc3a drm/i915: disable set/get_tiling ioctl on gen12+
-:48: WARNING:NO_AUTHOR_SIGN_OFF:
Quoting Daniel Vetter (2019-08-20 20:06:19)
> On Tue, Aug 20, 2019 at 8:55 PM Chris Wilson wrote:
> >
> > Quoting Daniel Vetter (2019-08-20 18:06:31)
> > > The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
> > > supported any of the fancy new tiling formats, which means
== Series Details ==
Series: drm/i915: Do not create a new max_bpc prop for MST connectors
URL : https://patchwork.freedesktop.org/series/65493/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6749 -> Patchwork_14108
Summary
Quoting Summers, Stuart (2019-08-20 20:01:05)
> On Tue, 2019-08-20 at 11:53 +0100, Chris Wilson wrote:
> > Quoting Stuart Summers (2019-08-19 22:50:00)
> > > Add a new function to determine whether a particular slice
> > > has a given subslice.
> > >
> > > Signed-off-by: Stuart Summers
> > > ---
On Tue, Aug 20, 2019 at 8:55 PM Chris Wilson wrote:
>
> Quoting Daniel Vetter (2019-08-20 18:06:31)
> > The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
> > supported any of the fancy new tiling formats, which means userspace
> > also stopped using the magic side-channel
== Series Details ==
Series: RFC/T: dma_resv vs. mmap_sem
URL : https://patchwork.freedesktop.org/series/65488/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6749 -> Patchwork_14107
Summary
---
**FAILURE**
== Series Details ==
Series: series starting with [1/3] drm/i915: Switch obj->mm.lock lockdep
annotations on its head
URL : https://patchwork.freedesktop.org/series/65467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14096_full
On Tue, 2019-08-20 at 11:53 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-19 22:50:00)
> > Add a new function to determine whether a particular slice
> > has a given subslice.
> >
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 10
Quoting Daniel Vetter (2019-08-20 18:06:31)
> The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
> supported any of the fancy new tiling formats, which means userspace
> also stopped using the magic side-channel this provides.
>
> This would totally break a lot of the igts,
== Series Details ==
Series: RFC/T: dma_resv vs. mmap_sem
URL : https://patchwork.freedesktop.org/series/65488/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4823a79936e3 dma_resv: prime lockdep annotations
-:65: WARNING:BAD_SIGN_OFF: email address '"VMware Graphics"
' might
== Series Details ==
Series: series starting with [1/6] drm/i915/gtt: Relax pd_used assertion
URL : https://patchwork.freedesktop.org/series/65486/
State : failure
== Summary ==
Applying: drm/i915/gtt: Relax pd_used assertion
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: series starting with [1/5] drm/i915/dp: stylistic cleanup around
hdcp2_msg_data
URL : https://patchwork.freedesktop.org/series/65481/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6749 -> Patchwork_14103
== Series Details ==
Series: drm/i915/gtt: Relax pd_used assertion
URL : https://patchwork.freedesktop.org/series/65484/
State : failure
== Summary ==
Applying: drm/i915/gtt: Relax pd_used assertion
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_gem_gtt.c
== Series Details ==
Series: drm/i915: Serialise the fill BLT with the vma pinning (rev2)
URL : https://patchwork.freedesktop.org/series/65482/
State : failure
== Summary ==
Applying: drm/i915: Serialise the fill BLT with the vma pinning
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: mmu notifier debug annotations/checks
URL : https://patchwork.freedesktop.org/series/65465/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14095_full
Summary
---
== Series Details ==
Series: series starting with [PATCHv2,1/2] fs: export put_filesystem()
URL : https://patchwork.freedesktop.org/series/65478/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6748 -> Patchwork_14102
On 8/20/19 8:42 AM, Michal Wajdeczko wrote:
On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio
wrote:
diff --git a/drivers/gpu/drm/i915/intel_reg_types.h
b/drivers/gpu/drm/i915/intel_reg_types.h
new file mode 100644
index ..87bce80dd5ed
--- /dev/null
+++
== Series Details ==
Series: Tiger Lake batch 3 (rev3)
URL : https://patchwork.freedesktop.org/series/65290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14094_full
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/tgl: Lower cdclk for sub 4k resolutions
URL : https://patchwork.freedesktop.org/series/65475/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6748 -> Patchwork_14100
Summary
---
== Series Details ==
Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev4)
URL : https://patchwork.freedesktop.org/series/63432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14093_full
Summary
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: 5ca0ef8a56b8 drm/i915: Add max_bpc property for DP MST.
The bot has tested the following trees: v5.2.9.
v5.2.9: Failed to apply! Possible dependencies:
Unable to calculate
The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
supported any of the fancy new tiling formats, which means userspace
also stopped using the magic side-channel this provides.
This would totally break a lot of the igts, but they're already broken
for the same reasons as
On Tue, 2019-08-20 at 19:16 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're not allowed to create new properties after device registration
> so for MST connectors we need to either create the max_bpc property
> earlier, or we reuse one we already have. Let's do the latter
> apporach
== Series Details ==
Series: series starting with [PATCHv2,1/2] fs: export put_filesystem()
URL : https://patchwork.freedesktop.org/series/65478/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9be2a741432b fs: export put_filesystem()
-:23: WARNING:NO_AUTHOR_SIGN_OFF: Missing
== Series Details ==
Series: dmabuf: Mark up onstack timer for selftests
URL : https://patchwork.freedesktop.org/series/65477/
State : failure
== Summary ==
Applying: dmabuf: Mark up onstack timer for selftests
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: drm/i915/tgl: Lower cdclk for sub 4k resolutions
URL : https://patchwork.freedesktop.org/series/65475/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0fb206f34d2d drm/i915/tgl: Lower cdclk for sub 4k resolutions
-:6: WARNING:COMMIT_LOG_LONG_LINE:
== Series Details ==
Series: drm/i915/tgl: Lower cdclk for sub 4k resolutions
URL : https://patchwork.freedesktop.org/series/65475/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Lower cdclk for sub 4k resolutions
== Series Details ==
Series: drm/i915/tgl: Gen12 csb support (rev3)
URL : https://patchwork.freedesktop.org/series/62890/
State : failure
== Summary ==
Applying: drm/i915/tgl: Gen12 csb support
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/gt/intel_lrc.c
Falling
From: Ville Syrjälä
We're not allowed to create new properties after device registration
so for MST connectors we need to either create the max_bpc property
earlier, or we reuse one we already have. Let's do the latter apporach
since the corresponding SST connector already has the prop and its
Am 20.08.19 um 17:41 schrieb Daniel Vetter:
> On Tue, Aug 20, 2019 at 5:34 PM Koenig, Christian
> wrote:
>> Am 20.08.19 um 17:21 schrieb Daniel Vetter:
>>> On Tue, Aug 20, 2019 at 5:16 PM Koenig, Christian
>>> wrote:
Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> With nouveau fixed all
On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio
wrote:
diff --git a/drivers/gpu/drm/i915/intel_reg_types.h
b/drivers/gpu/drm/i915/intel_reg_types.h
new file mode 100644
index ..87bce80dd5ed
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_reg_types.h
+
+typedef
On Tue, Aug 20, 2019 at 5:34 PM Koenig, Christian
wrote:
>
> Am 20.08.19 um 17:21 schrieb Daniel Vetter:
> > On Tue, Aug 20, 2019 at 5:16 PM Koenig, Christian
> > wrote:
> >> Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> >>> With nouveau fixed all ttm-using drives have the correct nesting of
>
Am 20.08.19 um 17:21 schrieb Daniel Vetter:
> On Tue, Aug 20, 2019 at 5:16 PM Koenig, Christian
> wrote:
>> Am 20.08.19 um 16:53 schrieb Daniel Vetter:
>>> With nouveau fixed all ttm-using drives have the correct nesting of
>>> mmap_sem vs dma_resv, and we can just lock the buffer.
>>>
>>>
On Tue, Aug 20, 2019 at 5:16 PM Koenig, Christian
wrote:
>
> Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> > With nouveau fixed all ttm-using drives have the correct nesting of
> > mmap_sem vs dma_resv, and we can just lock the buffer.
> >
> > Assuming I didn't screw up anything with my audit of
On Tue, Aug 20, 2019 at 10:34:18AM -0300, Jason Gunthorpe wrote:
> On Tue, Aug 20, 2019 at 10:19:02AM +0200, Daniel Vetter wrote:
> > We need to make sure implementations don't cheat and don't have a
> > possible schedule/blocking point deeply burried where review can't
> > catch it.
> >
> > I'm
Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> With nouveau fixed all ttm-using drives have the correct nesting of
> mmap_sem vs dma_resv, and we can just lock the buffer.
>
> Assuming I didn't screw up anything with my audit of course.
>
> Signed-off-by: Daniel Vetter
> Cc: Christian Koenig
>
>> >-Original Message-
>> >From: Kahola, Mika
>> >Sent: Tuesday, August 20, 2019 4:37 PM
>> >To: intel-gfx@lists.freedesktop.org
>> >Cc: Shankar, Uma ; Kahola, Mika
>> >
>> >Subject: [PATCH] drm/i915/tgl: Lower cdclk for sub 4k resolutions
>> >
>> >In order to achieve improved power
== Series Details ==
Series: drm/i915: Be defensive when starting vma activity
URL : https://patchwork.freedesktop.org/series/65471/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743 -> Patchwork_14098
Summary
---
Quoting Daniel Vetter (2019-08-20 15:53:34)
> Full audit of everyone:
>
> - i915, radeon, amdgpu should be clean per their maintainers.
>
> - vram helpers should be fine, they don't do command submission, so
> really no business holding struct_mutex while doing copy_*_user. But
> I haven't
Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> Full audit of everyone:
>
> - i915, radeon, amdgpu should be clean per their maintainers.
>
> - vram helpers should be fine, they don't do command submission, so
>really no business holding struct_mutex while doing copy_*_user. But
>I haven't
Full audit of everyone:
- i915, radeon, amdgpu should be clean per their maintainers.
- vram helpers should be fine, they don't do command submission, so
really no business holding struct_mutex while doing copy_*_user. But
I haven't checked them all.
- panfrost seems to dma_resv_lock only
With nouveau fixed all ttm-using drives have the correct nesting of
mmap_sem vs dma_resv, and we can just lock the buffer.
Assuming I didn't screw up anything with my audit of course.
Signed-off-by: Daniel Vetter
Cc: Christian Koenig
Cc: Huang Rui
Cc: Gerd Hoffmann
Cc: "VMware Graphics"
Cc:
Hi all,
As part of all the recent discussions around ttm and dma_resv I started
looking into this. The goal (at least somewhen in the near future) is to
have it all documented and the cross-driver semantics locked down as much
as possible.
One of the biggest issues there is how the dma_resv
We can't copy_*_user while holding reservations, that will (soon even
for nouveau) lead to deadlocks. And it breaks the cross-driver
contract around dma_resv.
Fix this by adding a slowpath for when we need relocations, and by
pushing the writeback of the new presumed offsets to the very end.
On Wed, 14 Aug 2019, Animesh Manna wrote:
> Yes, have missed and local build also could not catch as maybe object
> files were present in that directory.
> Fixed the issue and latest trybot link -
> https://patchwork.freedesktop.org/series/65161/
I don't have the patches. I'm not subscribed to
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