== Series Details ==
Series: series starting with [1/2] drm/i915: Remove link to missing
"Batchbuffer Pools" documentation
URL : https://patchwork.freedesktop.org/series/66046/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6807_full -> Patchwork_14234_full
Hi Lionel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3-rc6 next-20190830]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev13)
URL : https://patchwork.freedesktop.org/series/58039/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6807_full -> Patchwork_14233_full
== Series Details ==
Series: drm/i915: add Type-C port to encoder name (rev2)
URL : https://patchwork.freedesktop.org/series/65986/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6807_full -> Patchwork_14232_full
Summary
== Series Details ==
Series: series starting with [01/21] drm/i915/gtt: Downgrade Baytrail back to
aliasing-ppgtt
URL : https://patchwork.freedesktop.org/series/66033/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6806_full -> Patchwork_14231_full
== Series Details ==
Series: drm/i915: Prefer encoder->name over port_name()
URL : https://patchwork.freedesktop.org/series/66073/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6813 -> Patchwork_14247
Summary
---
On Fri, Aug 30, 2019 at 09:47:24PM +, Patchwork wrote:
> == Series Details ==
>
> Series: New cdclk values for gen11+ (rev2)
> URL : https://patchwork.freedesktop.org/series/65838/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6805_full -> Patchwork_14230_full
>
Most gen7 and gen8 platforms can't do plane scaling, so we need to
ensure the test doesn't try to do plane scaling on those platforms. The
legacy non-atomic subtest bakes these platform characteristics into the
test itself since legacy modesetting interfaces don't provide a way to
probe platform
== Series Details ==
Series: New cdclk values for gen11+ (rev2)
URL : https://patchwork.freedesktop.org/series/65838/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6805_full -> Patchwork_14230_full
Summary
---
Hi Lionel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.3-rc6 next-20190830]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
Hi Lionel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.3-rc6 next-20190830]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
Pushed to dinq, thanks for the patch and reviews
Manasi
On Fri, Aug 30, 2019 at 12:16:44PM +0200, Maarten Lankhorst wrote:
> When we moved the code to disable crtc's to a separate patch,
> we forgot to ensure that for_each_oldnew_intel_crtc_in_state_reverse()
> was moved as well.
>
>
On 30/08/2019 18:48, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-08-30 15:47:23)
err_unpin:
- __i915_vma_unpin(vma);
+ mutex_lock(>drm.struct_mutex);
+ i915_vma_unpin_and_release(, 0);
+ mutex_unlock(>drm.struct_mutex);
Strangely unpin_and_release() doesn't
On 30/08/2019 18:32, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-08-30 15:47:24)
+static int
+get_execbuf_oa_config(struct i915_execbuffer *eb)
+{
+ int err = 0;
+
+ eb->perf_file = NULL;
+ eb->oa_config = NULL;
+ eb->oa_vma = NULL;
+ eb->oa_bo = NULL;
+
+
Hi Lionel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.3-rc6 next-20190830]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
== Series Details ==
Series: drm/i915/perf: Assert locking for i915_init_oa_perf_state() (rev4)
URL : https://patchwork.freedesktop.org/series/66060/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6811 -> Patchwork_14246
Quoting Ville Syrjala (2019-08-30 19:27:19)
> From: Ville Syrjälä
>
> enum port is a mess now because it no longer matches the spec
> at all. Let's start to dig ourselves out of this hole by
> reducing our reliance on port_name(). This should at least make
> a bunch of debug messages a bit more
== Series Details ==
Series: drm/i915: Use RCU for unlocked vm_idr lookup
URL : https://patchwork.freedesktop.org/series/66071/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6811 -> Patchwork_14245
Summary
---
== Series Details ==
Series: drm/i915/gen9: Increase DPLL lock timeout
URL : https://patchwork.freedesktop.org/series/66025/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6805_full -> Patchwork_14229_full
Summary
---
On Thu, 2019-08-29 at 02:25 -0700, Lucas De Marchi wrote:
> SAGV is not currently working for Tiger Lake. We better disable it
> until
> the implementation is stabilized and we can enable it.
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> ---
>
On Fri, 2019-08-30 at 12:16 +0200, Maarten Lankhorst wrote:
> When we moved the code to disable crtc's to a separate patch,
> we forgot to ensure that
> for_each_oldnew_intel_crtc_in_state_reverse()
> was moved as well.
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Maarten Lankhorst
>
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gtt: Downgrade gen7 (ivb, byt,
hsw) back to aliasing-ppgtt
URL : https://patchwork.freedesktop.org/series/66070/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6811 -> Patchwork_14243
On Fri, Aug 30, 2019 at 12:16:44PM +0200, Maarten Lankhorst wrote:
> When we moved the code to disable crtc's to a separate patch,
> we forgot to ensure that for_each_oldnew_intel_crtc_in_state_reverse()
> was moved as well.
>
Oops yes I missed mving the
== Series Details ==
Series: DC3CO Support for TGL (rev4)
URL : https://patchwork.freedesktop.org/series/64923/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6811 -> Patchwork_14242
Summary
---
**FAILURE**
== Series Details ==
Series: DC3CO Support for TGL (rev4)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d909365d6e24 drm/i915/tgl: Add DC3CO required register and bits
d2cbdbad0e6b drm/i915/tgl: Add DC3CO mask to
From: Ville Syrjälä
enum port is a mess now because it no longer matches the spec
at all. Let's start to dig ourselves out of this hole by
reducing our reliance on port_name(). This should at least make
a bunch of debug messages a bit more sensible while we think how
to fill the the hole
We use the context->pin_mutex to serialise updates to the OA config and
the registers values written into each new context. Document this
relationship and assert we do hold the context->pin_mutex as used by
gen8_configure_all_contexts() to serialise updates to the OA config
itself.
v2: Add a
== Series Details ==
Series: drm/i915/perf: Assert locking for i915_init_oa_perf_state() (rev3)
URL : https://patchwork.freedesktop.org/series/66060/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6810 -> Patchwork_14241
On Fri, 2019-08-30 at 17:33 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/4] drm/i915: parameterize south hpd
> macros
> URL : https://patchwork.freedesktop.org/series/66023/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
On Thu, 2019-08-29 at 16:05 -0700, Matt Roper wrote:
> On Thu, Aug 29, 2019 at 02:15:24PM -0700, José Roberto de Souza
> wrote:
> > From: Lucas De Marchi
> >
> > The differences are only on the pins, trigger and long_detect
> > function.
> > The MCC handling is already partially merged, so merge
Since i915_address_space is now RCU protected, we can do the vm_idr lookup
without taking the vm_idr_mutex, just with the rcu_read_lock() instead.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 11 ---
1 file changed, 4
This is no longer used anywhere and so can be removed. However, tracking
the dirty status on the ppgtt doesn't work very well if the ppgtt is
shared, so perhaps for the best that it is no longer required.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
With the upcoming change in timing (dramatically reducing the latency
between manipulating the ppGTT and execution), no amount of tweaking
could save Cherryview, it would always fail to invalidate its TLB.
Signed-off-by: Chris Wilson
Acked-by: Matthew Auld
---
With the upcoming change in timing (dramatically reducing the latency
between manipulating the ppGTT and execution), no amount of tweaking
could save Baytrail, it would always fail to invalidate its TLB. Ville
was right, Baytrail is beyond hope.
v2: Rollback on all gen7; same timing instability
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
DC5 and DC6 saves more power, but can't be entered during video
playback because there are not enough idle frames in a row to
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset
Add max_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
max_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait
This is a new design proposal for DC3CO feature after disscussing
it with Ville and Imre.
This design uses a API tgl_set_target_dc_state() API
to switch between DC3CO and DC5 by using "DC off"
power well. Another major change in this design using page flip
frontbuffer flush call to allow DC3CO.
Add dc3co helper functions to enable/disable psr2 deep sleep.
Adhere B.Specs by disallow DC3CO state before PSR2 exit.
Enable PSR2 exitline event and program the desired scanlines
to exit DC3CO in intel_psr_enable function at modeset path.
v1: moved calling of
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
== Series Details ==
Series: series starting with [1/4] drm/i915: parameterize south hpd macros
URL : https://patchwork.freedesktop.org/series/66023/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6804_full -> Patchwork_14228_full
On Fri, 30 Aug 2019 at 07:14, Chris Wilson wrote:
>
> Since i915_address_space is now RCU protected, we can do the vm_idr lookup
> without taking the vm_idr_mutex, just with the rcu_read_lock() instead.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
We use the context->pin_mutex to serialise updates to the OA config and
the registers values written into each new context. Document this
relationship and assert we do hold the context->pin_mutex as used by
gen8_configure_all_contexts() to serialise updates to the OA config
itself.
v2: Add a
== Series Details ==
Series: drm/i915/perf: Assert locking for i915_init_oa_perf_state() (rev2)
URL : https://patchwork.freedesktop.org/series/66060/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6810 -> Patchwork_14240
On Fri, 30 Aug 2019 at 07:12, Chris Wilson wrote:
>
> This is no longer used anywhere and so can be removed. However, tracking
> the dirty status on the ppgtt doesn't work very well if the ppgtt is
> shared, so perhaps for the best that it is no longer required.
>
> Signed-off-by: Chris Wilson
On Fri, 30 Aug 2019 at 07:12, Chris Wilson wrote:
>
> With the upcoming change in timing (dramatically reducing the latency
> between manipulating the ppGTT and execution), no amount of tweaking
> could save Cherryview, it would always fail to invalidate its TLB.
>
> Signed-off-by: Chris Wilson
On Fri, 30 Aug 2019 at 07:12, Chris Wilson wrote:
>
> With the upcoming change in timing (dramatically reducing the latency
> between manipulating the ppGTT and execution), no amount of tweaking
> could save Baytrail, it would always fail to invalidate its TLB. Ville
> was right, Baytrail is
We use the context->pin_mutex to serialise updates to the OA config and
the registers values written into each new context. Document this
relationship and assert we do hold the context->pin_mutex as used by
gen8_configure_all_contexts() to serialise updates to the OA config
itself.
v2: Add a
== Series Details ==
Series: drm/i915/perf: Assert locking for i915_init_oa_perf_state()
URL : https://patchwork.freedesktop.org/series/66060/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6810 -> Patchwork_14238
Summary
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev13)
URL : https://patchwork.freedesktop.org/series/60916/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
On Fri, Aug 30, 2019 at 12:29:25AM -0700, Ser, Simon wrote:
> On Thu, 2019-08-29 at 13:52 -0700, Matt Roper wrote:
> > When choosing a low resolution mode to switch to, we search the
> > connector's mode list for a mode that's small enough that a plane
> > positioned in the bottom left corner of
On Fri, Aug 30, 2019 at 12:27:45AM -0700, Ser, Simon wrote:
> On Thu, 2019-08-29 at 09:47 -0700, Matt Roper wrote:
> > This test performs display updates via COMMIT_ATOMIC, but fails to check
> > that the platform being tested actually supports atomic. This causes
> > failures on some of our
Quoting Lionel Landwerlin (2019-08-30 15:47:23)
> err_unpin:
> - __i915_vma_unpin(vma);
> + mutex_lock(>drm.struct_mutex);
> + i915_vma_unpin_and_release(, 0);
> + mutex_unlock(>drm.struct_mutex);
Strangely unpin_and_release() doesn't need the mutex. But I can clean
that
Quoting Lionel Landwerlin (2019-08-30 15:47:24)
> +static int
> +get_execbuf_oa_config(struct i915_execbuffer *eb)
> +{
> + int err = 0;
> +
> + eb->perf_file = NULL;
> + eb->oa_config = NULL;
> + eb->oa_vma = NULL;
> + eb->oa_bo = NULL;
> +
> + if
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. This requires the process
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_perf.c | 7 +++
2 files changed, 12 insertions(+)
diff --git
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and given
the hard time we already have making everything work with the
submission side, there is no real point having this list of 1 element
around.
Signed-off-by:
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v1)
Hi all,
This moves locking a bit, hopefully in the right direction so that it
helps dropping the use of struct_mutex.
Cheers,
Lionel Landwerlin (11):
drm/i915: introduce a mechanism to extend execbuf2
drm/i915: add syncobj timeline support
drm/i915/perf: drop list of streams
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_getparam.c | 4
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not be powered when we poke
On 30/08/2019 17:40, Chris Wilson wrote:
We use the context->pin_mutex to serialise updates to the OA config and
the registers values written into each new context. Document this
relationship and assert we do hold the context->pin_mutex as used by
gen8_configure_all_contexts() to serialise
We use the context->pin_mutex to serialise updates to the OA config and
the registers values written into each new context. Document this
relationship and assert we do hold the context->pin_mutex as used by
gen8_configure_all_contexts() to serialise updates to the OA config
itself.
Signed-off-by:
== Series Details ==
Series: drm/i915: s/for_each_sgt_dma/for_each_sgt_daddr/
URL : https://patchwork.freedesktop.org/series/66021/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6803_full -> Patchwork_14227_full
Summary
== Series Details ==
Series: DSB enablement. (rev4)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6808 -> Patchwork_14237
Summary
---
**SUCCESS**
No
On Fri, 30 Aug 2019, Animesh Manna wrote:
> This patch adds a function, which will internally get the gem buffer
> for DSB engine. The GEM buffer is from global GTT, and is mapped into
> CPU domain, contains the data + opcode to be feed to DSB engine.
>
> v1: Initial version.
>
> v2:
> - removed
On Fri, 30 Aug 2019, Animesh Manna wrote:
> Gamma lut programming can be programmed using DSB
> where bulk register programming can be done using indexed
> register write which takes number of data and the mmio offset
> to be written.
>
> v1: Initial version.
> v2: Directly call dsb-api at
On Fri, 30 Aug 2019, Swati Sharma wrote:
> For ilk, add hw read out to create hw blob of gamma
> lut values.
>
> v4: -No need to initialize *blob [Jani]
> -Removed right shifts [Jani]
> -Dropped dev local var [Jani]
> v5: -Returned blob instead of assigning it internally within the
>
On Fri, 30 Aug 2019, Swati Sharma wrote:
> For cherryview, add hw read out to create hw blob of gamma
> lut values.
>
> v4: -No need to initialize *blob [Jani]
> -Removed right shifts [Jani]
> -Dropped dev local var [Jani]
> v5: -Returned blob instead of assigning it internally within the
On Fri, 30 Aug 2019, Swati Sharma wrote:
> For i965, add hw read out to create hw blob of gamma
> lut values.
>
> v4: -No need to initialize *blob [Jani]
> -Removed right shifts [Jani]
> -Dropped dev local var [Jani]
> v5: -Returned blob instead of assigning it internally
> within
== Series Details ==
Series: DSB enablement. (rev4)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsb: feature flag added for display state buffer.
Okay!
== Series Details ==
Series: DSB enablement. (rev4)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d4d1dfe5ffbf drm/i915/dsb: feature flag added for display state buffer.
726f4aedf3ef drm/i915/dsb: DSB context creation.
On Fri, 30 Aug 2019, Swati Sharma wrote:
> For the legacy(gen < 4) gamma, add hw read out to create hw blob of gamma
> lut values. Also, add function intel_color_lut_pack to convert hw value
> with given bit precision to lut property val.
>
> v4: -No need to initialize *blob [Jani]
> -Removed
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALIGN(). (Chris)
v3: ascii table added as code
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
v1: Initial version.
v2: Directly call dsb-api at callsites. (Jani)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v2: POSTING_READ added after writing control
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index
Display State Buffer (DSB) is hardware capability which allows driver
to batch submit HW programming.
As part of initial enablement common api created which currently used
to program gamma lut proramming.
Going forwad DSB support can be added for HDR and flip related operation.
HSDES:
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted code. (Chris)
- Used
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
On Fri, 30 Aug 2019, Swati Sharma wrote:
> Add func intel_color_lut_equal() to compare hw/sw gamma
> lut values. Since hw/sw gamma lut sizes and lut entries comparison
> will be different for different gamma modes, add gamma mode dependent
> checks.
>
> v3: -Rebase
> v4: -Renamed
On Fri, Aug 30, 2019 at 09:57:00AM +0300, Jani Nikula wrote:
> On Thu, 29 Aug 2019, Simon Ser wrote:
> > This patch adds the Type-C port number to the encoder name. This is an
> > alternative to [1].
> >
> > [1]: https://patchwork.freedesktop.org/series/65695/
> >
> > Signed-off-by: Simon Ser
>
On Thu, Aug 29, 2019 at 09:09:14AM -0400, Alex Deucher wrote:
> On Wed, Aug 28, 2019 at 10:27 AM Ville Syrjälä
> wrote:
> >
> > On Mon, Aug 26, 2019 at 04:22:13PM +0300, Oleg Vasilev wrote:
> > > Since DP-specific information is stored in driver's structures, every
> > > driver needs to implement
== Series Details ==
Series: drm/i915: Document locking guidelines
URL : https://patchwork.freedesktop.org/series/66052/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6807 -> Patchwork_14236
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Fix regression with crtc disable ordering
URL : https://patchwork.freedesktop.org/series/66050/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6807 -> Patchwork_14235
Summary
---
On Fri, 30 Aug 2019, Swati Sharma wrote:
> Add debug log for color related parameters like gamma_mode, gamma_enable,
> csc_enable, etc inside intel_dump_pipe_config().
>
> v6: -Added debug log for color para in intel_dump_pipe_config [Jani]
> v7: -Split patch 3 into 4 patches
> v8: -Corrected
On Fri, 30 Aug 2019, Jani Nikula wrote:
> On Fri, 30 Aug 2019, Jani Nikula wrote:
>> On Fri, 30 Aug 2019, Swati Sharma wrote:
>>> Each platform supports different gamma modes and each gamma mode
>>> has different bit precision. Here bit precision corresponds
>>> to number of bits the hw LUT
On Fri, 30 Aug 2019, Jani Nikula wrote:
> On Fri, 30 Aug 2019, Swati Sharma wrote:
>> Each platform supports different gamma modes and each gamma mode
>> has different bit precision. Here bit precision corresponds
>> to number of bits the hw LUT supports.
>>
>> Add func per platform to return
On Fri, 30 Aug 2019, Swati Sharma wrote:
> Each platform supports different gamma modes and each gamma mode
> has different bit precision. Here bit precision corresponds
> to number of bits the hw LUT supports.
>
> Add func per platform to return bit precision corresponding to gamma mode
> which
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