== Series Details ==
Series: DC3CO Support for TGL (rev8)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6850 -> Patchwork_14319
Summary
---
**SUCCESS**
No regr
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL (rev3)
URL : https://patchwork.freedesktop.org/series/66365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6850_full -> Patchwork_14318_full
Summary
--
== Series Details ==
Series: DC3CO Support for TGL (rev8)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Add DC3CO required register and bits
Okay!
Commit: drm/i915/tgl: Add DC3CO mas
== Series Details ==
Series: DC3CO Support for TGL (rev8)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5f6bfdba251e drm/i915/tgl: Add DC3CO required register and bits
0d688fd512cf drm/i915/tgl: Add DC3CO mask to allowed_dc_
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL (rev3)
URL : https://patchwork.freedesktop.org/series/66365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6850 -> Patchwork_14318
Summary
---
*
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL (rev3)
URL : https://patchwork.freedesktop.org/series/66365/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
27511b1a3ffa drm/i915: Consolidate bxt/cnl/icl cdclk readout
-:72: CHECK:CAMELCASE: Avoid CamelCase
The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
dividers in an easy-to-read table for most recent platforms. We've been
translating the data from that table into platform-specific code logic,
but it's easy to overlook an area we need to update when adding new
cdclk values or enabl
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL (rev2)
URL : https://patchwork.freedesktop.org/series/66365/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
dividers in an easy-to-read table for most recent platforms. We've been
translating the data from that table into platform-specific code logic,
but it's easy to overlook an area we need to update when adding new
cdclk values or enabl
On Wed, Aug 21, 2019 at 7:55 AM Thierry Reding wrote:
>
> On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote:
> > On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann wrote:
> > >
> > > Hi,
> > >
> > > > > Changing the order doesn't look hard. Patch attached (untested, have
> > > > > no
> > >
On Sat, Sep 7, 2019 at 7:20 PM Mun, Gwan-gyeong
wrote:
>
> On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > wrote:
> > > On Fri, Sep 06, 2019 at 11:31:55AM +, Shankar, Uma wrote:
> > > >
> > > > > -Original Message-
> > > > > F
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev5)
URL : https://patchwork.freedesktop.org/series/65656/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6850_full -> Patchwork_14316_full
Summary
-
On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> wrote:
> > On Fri, Sep 06, 2019 at 11:31:55AM +, Shankar, Uma wrote:
> > >
> > > > -Original Message-
> > > > From: Ilia Mirkin
> > > > Sent: Tuesday, September 3, 2019 6:12 PM
> >
Support for HDR10 video was introduced in DisplayPort 1.4.
On GLK+ platform, in order to use DisplayPort HDR10, we need to support
BT.2020 colorimetry and HDR Static metadata.
It implements the CTA-861-G standard for transport of static HDR metadata.
It enables writing of HDR metadata infoframe SDP
When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. It adds output_colorspace to
intel_crtc_state struct as a place holder of pipe's output colorspace.
In order to distinguish needed colorimetry for VSC SDP, it adds
intel_dp_needs_vsc_sdp functi
It refactors and renames a function which handled vsc sdp header and data
block setup for supporting colorimetry format.
Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block
setup for pixel encoding / colorimetry format.
In order to use colorspace information of a connector, it add
Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
sta
According to Bspec, GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for
GEN11. And it makes handle different register size for
HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
platforms. It addresses Um
In order to use colorspace property to Display Port connectors, it extends
DRM_MODE_CONNECTOR_DisplayPort connector_type on
drm_mode_create_colorspace_property function.
v3: Addressed review comments from Ville
- Add new colorimetry options for DP 1.4a spec.
- Separate set of colorimetry e
It attaches HDR metadata property to DP connector on GLK+.
It enables HDR metadata infoframe sdp on GLK+ to be used to send
HDR metadata to DP sink.
v2: Minor style fix
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +
1 file changed
It attaches the colorspace connector property to a DisplayPort connector.
Based on colorspace change, modeset will be triggered to switch to a new
colorspace.
Based on colorspace property value create a VSC SDP packet with appropriate
colorspace. This would help to enable wider color gamut like BT
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev5)
URL : https://patchwork.freedesktop.org/series/65656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6850 -> Patchwork_14316
Summary
---
**SU
Hi,
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.2.13, v4.19.71, v4.14.142, v4.9.191,
v4.4.191.
v5.2.13: Failed to apply! Possib
== Series Details ==
Series: DC3CO Support for TGL (rev7)
URL : https://patchwork.freedesktop.org/series/64923/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6849_full -> Patchwork_14315_full
Summary
---
**FAILURE**
The curse of using libigt where it is not wanted; in this case calling
drop-caches while we hold the forcewake is a recipe for a long wait.
Signed-off-by: Chris Wilson
---
tools/intel_l3_parity.c | 50 -
1 file changed, 29 insertions(+), 21 deletions(-)
d
Signed-off-by: Chris Wilson
---
meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/meson.build b/meson.build
index 478869eb6..aeecf0dc6 100644
--- a/meson.build
+++ b/meson.build
@@ -44,6 +44,7 @@ cc_args = [
'-Wno-maybe-uninitialized',
'-Wno-missing-field-initializer
== Series Details ==
Series: DC3CO Support for TGL (rev7)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6849 -> Patchwork_14315
Summary
---
**SUCCESS**
No regr
== Series Details ==
Series: DC3CO Support for TGL (rev7)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Add DC3CO required register and bits
Okay!
Commit: drm/i915/tgl: Add DC3CO mas
== Series Details ==
Series: DC3CO Support for TGL (rev7)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b9b649158ff7 drm/i915/tgl: Add DC3CO required register and bits
d747f1009d07 drm/i915/tgl: Add DC3CO mask to allowed_dc_
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
DC5 and DC6 saves more power, but can't be entered during video
playback because there are not enough idle frames in a row to meet
Add max_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
max_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for
Add dc3co helper functions to enable/disable psr2 deep sleep.
Adhere B.Specs by disallow DC3CO state before PSR2 exit.
Enable PSR2 exitline event and program the desired scanlines
to exit DC3CO in intel_psr_enable function at modeset path.
Disable the DC3CO exitline in order to maintian consistent
DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset as
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/disp
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
d
This is a new design proposal for DC3CO feature after discussing
it with Ville and Imre.
Unlike v6 this v7 version has a cleaner solution to froce the
modeset at bootup by using a crtc_state state bool
has_dc3co_exitline in order to configure and enable dc3co exitline.
Suggestion and feedback are
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file cha
== Series Details ==
Series: drm/i915/execlists: Remove incorrect BUG_ON for schedule-out
URL : https://patchwork.freedesktop.org/series/66372/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6849_full -> Patchwork_14313_full
== Series Details ==
Series: drm/i915: Perform GGTT restore much earlier during resume (rev3)
URL : https://patchwork.freedesktop.org/series/66369/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6849_full -> Patchwork_14312_full
=
If the object needs to be migrated, it may will need GPU relocs and so
have an exclusive fence showing up in the write domain.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_balancer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_exec_balancer.c b/t
Check that we can run a second request even if an equal priority spinner
is hogging the engine.
Extend the testing with some undying timeslice behaviour that requires
hangcheck to intervene.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
---
tests/i9
When using a spinner to trigger a hang, make it unpreemptable so that it
appears like a true hang.
References: https://bugs.freedesktop.org/show_bug.cgi?id=109661
Signed-off-by: Chris Wilson
---
tests/i915/gem_eio.c| 4 +++-
tests/i915/gem_exec_fence.c | 3 ++-
tests/kms_busy.c
Use an explicit fence to circumvent the [i915] GPU hang detection rather
than tweak the i915 specific modparam (and remove the assertion that
such a param exists). Note, that with a bit more work, the fence could
be used be directly rather than via dirtying the fb with a dummyload.
Signed-off-by:
== Series Details ==
Series: DSB enablement. (rev5)
URL : https://patchwork.freedesktop.org/series/63013/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6849 -> Patchwork_14314
Summary
---
**FAILURE**
Serious unkno
== Series Details ==
Series: DSB enablement. (rev5)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsb: feature flag added for display state buffer.
Okay!
_
== Series Details ==
Series: DSB enablement. (rev5)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0f9bce67daf4 drm/i915/dsb: feature flag added for display state buffer.
41a4427c2474 drm/i915/dsb: DSB context creation.
-:56:
== Series Details ==
Series: drm/i915/execlists: Remove incorrect BUG_ON for schedule-out
URL : https://patchwork.freedesktop.org/series/66372/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6849 -> Patchwork_14313
Summary
-
== Series Details ==
Series: drm/i915/execlists: Ignore lost completion events (rev2)
URL : https://patchwork.freedesktop.org/series/66084/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6848_full -> Patchwork_14310_full
Sum
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Currently enabled for 12-bit gamma LUT which is enabled by
default and later 8-bit/10-bit will be enabled in futu
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i9
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized code
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9 +++
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v2: POSTING_READ added after writing control r
The lifetime of command buffer can be controlled by the dsb user
throuh refcount. Added refcount mechanism is dsb get/put call
which create/destroy dsb context.
Cc: Jani Nikula
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 22 --
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
drivers/gp
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted code. (Chris)
- Used i915_gem_object_create_
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALIGN(). (Chris)
v3: ascii table added as code c
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/dr
Display State Buffer (DSB) is hardware capability which allows driver
to batch submit HW programming.
As part of initial enablement common api created which currently used
to program gamma lut proramming.
Going forwad DSB support can be added for HDR and flip related operation.
HSDES: 1209978241
== Series Details ==
Series: drm/i915: Perform GGTT restore much earlier during resume (rev3)
URL : https://patchwork.freedesktop.org/series/66369/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6849 -> Patchwork_14312
Summa
As we may unwind incomplete requests (for preemption) prior to
processing the CSB and the schedule-out events, we may update rq->engine
(resetting it to point back to the parent virtual engine) prior to
calling execlists_schedule_out(), invalidating the assertion that the
request still points to th
== Series Details ==
Series: series starting with [1/2] drm/framebuffer: Format modifier for Intel
Gen-12 render compression
URL : https://patchwork.freedesktop.org/series/66367/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6848_full -> Patchwork_14309_full
=
As soon as we re-enable the various functions within the HW, they may go
off and read data via a GGTT offset. Hence, if we have not yet restored
the GGTT PTE before then, they may read and even *write* random locations
in memory.
Detected by DMAR faults during resume.
Signed-off-by: Chris Wilson
== Series Details ==
Series: drm/i915: Perform GGTT restore much earlier during resume (rev2)
URL : https://patchwork.freedesktop.org/series/66369/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6848 -> Patchwork_14311
Summa
== Series Details ==
Series: drm/i915/execlists: Ignore lost completion events (rev2)
URL : https://patchwork.freedesktop.org/series/66084/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6848 -> Patchwork_14310
Summary
-
== Series Details ==
Series: drm/i915/execlists: Ignore lost completion events (rev2)
URL : https://patchwork.freedesktop.org/series/66084/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fac5dabbedb9 drm/i915/execlists: Ignore lost completion events
-:11: WARNING:COMMIT_LOG_LONG
As soon as we re-enable the various functions within the HW, they may go
off and read data via a GGTT offset. Hence, if we have not yet restored
the GGTT PTE before then, they may read and even *write* random locations
in memory.
Detected by DMAR faults during resume.
Signed-off-by: Chris Wilson
Icelake hit an issue where it missed reporting a completion event and
instead jumped straight to a idle->active event (skipping over the
active->idle and not even hitting the lite-restore preemption).
661497511us : process_csb: rcs0 cs-irq head=11, tail=0
661497512us : process_csb: rcs0 csb[0]: st
Quoting Daniele Ceraolo Spurio (2019-09-06 23:28:05)
>
>
> On 9/5/19 2:09 AM, Janusz Krzysztofik wrote:
> > When trying to reset a device with reset capability disabled or not
> > supported while rings are full of requests, it has been observed when
> > running in execlists submission mode that c
As soon as we re-enable the various functions within the HW, they may go
off and read data via a GGTT offset. Hence, if we have not yet restored
the GGTT PTE before then, they may read and even *write* random locations
in memory.
Detected by DMAR faults during resume.
Signed-off-by: Chris Wilson
== Series Details ==
Series: drm/i915/tgl: Implement Wa_1409142259
URL : https://patchwork.freedesktop.org/series/66364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6848_full -> Patchwork_14307_full
Summary
---
**S
== Series Details ==
Series: series starting with [1/2] drm/framebuffer: Format modifier for Intel
Gen-12 render compression
URL : https://patchwork.freedesktop.org/series/66367/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6848 -> Patchwork_14309
===
On Sat, 2019-09-07 at 00:21 -0700, Dhinakaran Pandiyan wrote:
> Gen-12 has a new compression format, add a new modifier to indicate that.
>
> Cc: Ville Syrjälä
> Cc: Matt Roper
> Cc: Nanley G Chery
> Cc: Jason Ekstrand
Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Dhinakaran Pandiyan
Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so make use of a new
modifier to
Gen-12 has a new compression format, add a new modifier to indicate that.
Cc: Ville Syrjälä
Cc: Matt Roper
Cc: Nanley G Chery
Cc: Jason Ekstrand
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
include/uapi/drm/drm_fourcc.h | 11 +++
1 file changed, 11 insertion
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