When LMEM is supported, dumb buffer preferred to be created from LMEM.
This is developed on top of v3 LMEM series
https://patchwork.freedesktop.org/series/56683/.
v2:
Parameters are reshuffled. [Chris]
Signed-off-by: Ramalingam C
cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 18
If Local memory is supported by hardware, we want framebuffer backing
gem objects out of local memory.
If local memory is supported and gem object if not from local memory we
migrate the obj into local memory. And once framebuffer is created we
block the migration of the associated object out of
Each GEM object is initialized with allowed memory regions for
it's migration across memory region.
In future patch we are restricting the memory regions or few objects.
This is developed on top of v3 LMEM series
https://patchwork.freedesktop.org/series/56683/
CC: Matthew Auld
Signed-off-by:
On Fri, Sep 20, 2019 at 01:42:24PM +0200, Maarten Lankhorst wrote:
> Make vdsc work when no output is enabled. The big joiner needs VDSC
> on the slave, so enable it and set the appropriate bits.
> Also update timestamping constants, because slave crtc's are not
> updated in
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14548
Summary
---
**FAILURE**
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Add DC3CO required register and bits
Okay!
Commit: drm/i915/tgl: Add DC3CO
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
805a6f5f1e23 drm/i915/tgl: Add DC3CO required register and bits
5e43f1ddfa09 drm/i915/tgl: Add DC3CO mask to
== Series Details ==
Series: drm/i915: Small joiner RAM buffer size is platform-specific (rev3)
URL : https://patchwork.freedesktop.org/series/67195/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14547
On 2019/9/25 下午9:21, Michael S. Tsirkin wrote:
On Wed, Sep 25, 2019 at 08:45:21PM +0800, Jason Wang wrote:
On 2019/9/25 下午5:09, Tian, Kevin wrote:
From: Jason Wang [mailto:jasow...@redhat.com]
Sent: Tuesday, September 24, 2019 9:54 PM
This patch implements basic support for mdev driver that
Add target_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to
On Fri, Sep 20, 2019 at 01:42:23PM +0200, Maarten Lankhorst wrote:
> When the clock is higher than the dotclock, try with 2 pipes enabled.
> If we can enable 2, then we will go into big joiner mode, and steal
> the adjacent crtc.
>
> This only links the crtc's in software, no hardware or plane
>
On Thu, Sep 26, 2019 at 01:26:22AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Small joiner RAM buffer size is platform-specific (rev2)
> URL : https://patchwork.freedesktop.org/series/67195/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
== Series Details ==
Series: series starting with [v11,1/2] drm/i915: Introduce async plane update
to i915
URL : https://patchwork.freedesktop.org/series/67254/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6961 -> Patchwork_14546
== Series Details ==
Series: drm/i915: Small joiner RAM buffer size is platform-specific (rev2)
URL : https://patchwork.freedesktop.org/series/67195/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6961 -> Patchwork_14545
From: Gustavo Padovan
Replace the legacy cursor implementation by the async callbacks
Signed-off-by: Gustavo Padovan
Signed-off-by: Enric Balletbo i Serra
Signed-off-by: Helen Koike
---
Changes in v11: None
Changes in v10: None
Changes in v9:
- v8:
From: Gustavo Padovan
Add implementation for async plane update callbacks
Signed-off-by: Gustavo Padovan
Signed-off-by: Enric Balletbo i Serra
Signed-off-by: Tina Zhang
Signed-off-by: Helen Koike
Tested-by: Tina Zhang
---
Hi,
I ran the following tests and no regressions were found:
== Series Details ==
Series: TGL TC enabling (rev4)
URL : https://patchwork.freedesktop.org/series/66695/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6961 -> Patchwork_14544
Summary
---
**SUCCESS**
No
== Series Details ==
Series: series starting with [01/27] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
URL : https://patchwork.freedesktop.org/series/67206/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6954_full -> Patchwork_14527_full
> From: Jason Wang
> Sent: Wednesday, September 25, 2019 8:45 PM
>
>
> On 2019/9/25 下午5:09, Tian, Kevin wrote:
> >> From: Jason Wang [mailto:jasow...@redhat.com]
> >> Sent: Tuesday, September 24, 2019 9:54 PM
> >>
> >> This patch implements basic support for mdev driver that supports
> >> virtio
Reviewed-by: Lyude Paul
Cc: Mikita Lipski - figured you'd want to know ahead of time you'll need to
update your changes to drm_dp_calc_pbn_mode() to match
On Wed, 2019-09-25 at 17:14 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Get rid of the drm_fixp_from_fraction() usage and just
Reviewed-by: Lyude Paul
On Wed, 2019-09-25 at 17:14 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make drm_dp_get_vc_payload() tolerate arbitrary DP_LINK_BW_*
> values, just like drm_dp_bw_code_to_link_rate() does since commit
> 57a1b0893782 ("drm: Make the bw/link rate calculations
From: Clinton A Taylor
BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
now taking in consideration the pin assignment and allowing us to
optimize power by shutting down available but not needed lanes.
It was tested on ICL and TGL, with adaptors that used pin assignment
C and
According to the bspec, GLK/CNL have a smaller small joiner RAM buffer
than ICL+. This feels like something that could easily change again on
future platforms, so let's just add a function to return the proper
per-platform buffer size. That may also slightly simplify the upcoming
bigjoiner
TGL TC enabling v4
v1: https://patchwork.freedesktop.org/series/66695/#rev1
v2: https://patchwork.freedesktop.org/series/66695/#rev2
v2 patches merged: https://patchwork.freedesktop.org/series/67022/
v3: https://patchwork.freedesktop.org/series/66695/#rev3
v3 patches merged:
Link training is failling when running link at 2.7GHz and 1.62GHz and
following BSpec pll algorithm.
Comparing the values calculated and the ones from the reference table
it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set
to 5. For DP ports ICL mg pll algorithm sets it to 10 or
From: Lucas De Marchi
Now that TC support was added, initialize DDIs.
Reviewed-by: José Roberto de Souza
Acked-by: Lucas De Marchi
Signed-off-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
1 file changed, 6
From: Clinton A Taylor
Added DKL Phy sequences and helpers functions to program voltage
swing, clock gating and dp mode.
It is not written in DP enabling sequence but "PHY Clockgating
programming" states that clock gating should be enabled after the
link training but doing so causes all the
== Series Details ==
Series: GuC engine reset support
URL : https://patchwork.freedesktop.org/series/67251/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958 -> Patchwork_14543
Summary
---
**SUCCESS**
No
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Fix dsc bpp calculations, v5.
URL : https://patchwork.freedesktop.org/series/67203/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6954_full -> Patchwork_14526_full
== Series Details ==
Series: drm/i915/huc: fix version parsing from CSS header
URL : https://patchwork.freedesktop.org/series/67248/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958 -> Patchwork_14541
Summary
---
Another attempt at providing GuC a list of registers to
save/restore during engine resets [1].
The list we provide GuC should mirror, with possibly some exceptions,
the list of registers applied during execlists_resume/enable_execlists.
Any ideas on how to flag any discrepancies (yet flexible
The driver must provide GuC with a list of mmio registers
that should be saved/restored during a GuC-based engine reset.
We provide a minimal set of registers that should get things
working and extend as needed.
Signed-off-by: Fernando Pacheco
---
drivers/gpu/drm/i915/gt/intel_workarounds.c |
== Series Details ==
Series: Panel rotation patches (rev8)
URL : https://patchwork.freedesktop.org/series/61870/
State : failure
== Summary ==
Applying: drm/panel: Add helper for reading DT rotation
Applying: drm/panel: set display info in panel attach
error: sha1 information is lacking or
On Wed, 2019-09-25 at 15:21 -0700, Daniele Ceraolo Spurio wrote:
> The HuC FW has silently switched to encoding the version the same way
> as
> the GuC FW does, i.e. major.minor.patch instead of just major.minor.
> All
> the current blobs follow the new scheme, but since minor and patch
> are
>
Not every platform needs quirk detection for panel orientation, so
split the drm_connector_init_panel_orientation_property into two
functions. One for platforms without the need for quirks, and the
other for platforms that need quirks.
Signed-off-by: Derek Basehore
Acked-by: Sam Ravnborg
---
This inits the panel orientation property for the mediatek dsi driver
if the panel orientation (connector.display_info.panel_orientation) is
not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
Signed-off-by: Derek Basehore
Acked-by: Sam Ravnborg
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_dsi.c |
This adds the plumbing for reading panel rotation from the devicetree
and sets up adding a panel property for the panel orientation on
Mediatek SoCs when a rotation is present.
v8 changes:
-added reviewed-by tags
-fixed conflict with i915 patch that recently landed
-Added additional documentation
This adds a helper function for reading the rotation (panel
orientation) from the device tree.
Signed-off-by: Derek Basehore
Reviewed-by: Sam Ravnborg
---
drivers/gpu/drm/drm_panel.c | 43 +
include/drm/drm_panel.h | 9
2 files changed, 52
Devicetree systems can set panel orientation via a panel binding, but
there's no way, as is, to propagate this setting to the connector,
where the property need to be added.
To address this, this patch sets orientation, as well as other fixed
values for the panel, in the drm_panel_attach function.
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: d9218c8f6cf4 drm/i915/dp: Add helpers for Compressed BPP and
Slice Count for DSC.
The bot has tested the following trees: v5.3.1, v5.2.17.
v5.3.1: Build OK!
v5.2.17: Failed to
On Wed, Sep 25, 2019 at 03:35:28PM -0700, Summers, Stuart wrote:
> On Wed, 2019-09-25 at 08:35 -0700, James Ausmus wrote:
> > On Wed, Sep 25, 2019 at 07:33:38AM -0700, Summers, Stuart wrote:
> > > On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote:
> > > > The memory type values have changed in
On Wed, 2019-09-25 at 08:35 -0700, James Ausmus wrote:
> On Wed, Sep 25, 2019 at 07:33:38AM -0700, Summers, Stuart wrote:
> > On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote:
> > > The memory type values have changed in TGL, so we need to
> > > translate
> > > them
> > > differently than
The HuC FW has silently switched to encoding the version the same way as
the GuC FW does, i.e. major.minor.patch instead of just major.minor. All
the current blobs follow the new scheme, but since minor and patch are
both zero there is no difference in the end results and we happily load
them. New
Hi Maarten,
Could you hold off on merging this patch and big joiner enabling patch else
my 2p2p series which is almost ready to merge except for the final r-b from you
on the HW state patch will need to rebased and that will delay the landing of
the
series.
Manasi
On Fri, Sep 20, 2019 at
== Series Details ==
Series: drm/i915: Add feature flag for platforms with DRAM
URL : https://patchwork.freedesktop.org/series/67244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958 -> Patchwork_14540
Summary
---
On Tue, Sep 24, 2019 at 10:53:11PM -0700, Matt Roper wrote:
> According to the bspec, GLK/CNL have a smaller small joiner RAM buffer
> than ICL+. This feels like something that could easily change again on
> future platforms, so let's just add a function to return the proper
> per-platform buffer
On Tue, Sep 24, 2019 at 10:30:39PM -0700, Matt Roper wrote:
> On Fri, Sep 20, 2019 at 01:42:22PM +0200, Maarten Lankhorst wrote:
> > Small changes to intel_dp_mode_valid(), allow listing modes that
> > can only be supported in the bigjoiner configuration, which is
> > not supported yet.
> >
> >
== Series Details ==
Series: drm/i915: Add feature flag for platforms with DRAM
URL : https://patchwork.freedesktop.org/series/67244/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
099fb95d6ff3 drm/i915: Add feature flag for platforms with DRAM
-:7: WARNING:COMMIT_MESSAGE:
On Wed, Sep 25, 2019 at 04:59:00PM +0200, Maarten Lankhorst wrote:
> Now that we separated everything into uapi and hw, it's
> time to make the split definitive. Remove the union and
> make a copy of the hw state on modeset and fastset.
>
> Color blobs are copied in crtc atomic_check(), right
>
On Wed, Sep 25, 2019 at 04:59:01PM +0200, Maarten Lankhorst wrote:
> This can all be done from the intel_update_crtc function. Split out the
> pipe update into a separate function, just like is done for the planes.
> Pull in all the changes done during fastset as well. It makes no sense
> for it
== Series Details ==
Series: series starting with [1/3] drm/i915: Extract SAGV block time function
URL : https://patchwork.freedesktop.org/series/67240/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958 -> Patchwork_14539
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git
On 9/21/19 4:00 PM, Patchwork wrote:
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/67009/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6929_full ->
== Series Details ==
Series: series starting with [1/3] drm/i915: Extract SAGV block time function
URL : https://patchwork.freedesktop.org/series/67240/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
45bac93b7379 drm/i915: Extract SAGV block time function
fffc1235b9c0
== Series Details ==
Series: drm/i915/dmc: Update ICL DMC version to v1.09 (rev2)
URL : https://patchwork.freedesktop.org/series/66560/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958 -> Patchwork_14538
Summary
---
== Series Details ==
Series: drm/i915: Small joiner RAM buffer size is platform-specific
URL : https://patchwork.freedesktop.org/series/67195/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6952_full -> Patchwork_14525_full
For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
active. Update intel_can_enable_sagv to allow this, and loop through all
active planes on all active crtcs to check against the interlaced and
latency restrictions.
BSpec: 49325
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc:
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
In prep for newer platforms having more complicated ways to determine
the SAGV block time, extract the setting to a separate function. While
we're at it, update the if ladder to follow the new gen -> old gen order
preference, and warn on any non-specified gen.
Cc: Ville Syrjälä
Cc: Stanislav
Even though we can't actually turn on SAGV for TGL until HSDES
1409542895 is resolved, these patches prepare the code for enabling
SAGV, so that once the HSDES is resolved, all we have to do is revert
8ffa4392a32e ("drm/i915/tgl: disable SAGV temporarily") to turn it on.
== Series Details ==
Series: drm/i915/selftests: Exercise concurrent submission to all engines
URL : https://patchwork.freedesktop.org/series/67237/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958 -> Patchwork_14537
From: Anusha Srivatsa
We have a new version of DMC for ICL - v1.09.
This version adds the Half Refresh Rate capability
into DMC.
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Reviewed-by: José Roberto de Souza
Signed-off-by: Daniele Ceraolo Spurio
Link:
== Series Details ==
Series: drm/i915/selftests: Exercise concurrent submission to all engines
URL : https://patchwork.freedesktop.org/series/67237/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
92cc309e8be5 drm/i915/selftests: Exercise concurrent submission to all engines
== Series Details ==
Series: drm/i915/dp: Fix DP MST error after unplugging TypeC cable (rev3)
URL : https://patchwork.freedesktop.org/series/66837/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6952_full -> Patchwork_14524_full
The simplest and most maximal submission we can do, a thread to submit
requests unto each engine.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/selftests/i915_request.c | 125 ++
1 file changed, 125 insertions(+)
diff --git
On Wed, 2019-09-25 at 16:22 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/6] drm/i915/tgl: Add initial dkl
> pll support
> URL : https://patchwork.freedesktop.org/series/67181/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from
Reviewed-by: Lyude Paul
On Wed, 2019-09-25 at 17:14 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the nested ifs with a single if and a logical AND.
>
> Cc: Lyude Paul
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 10 +-
> 1 file
== Series Details ==
Series: DC3CO Support for TGL (rev10)
URL : https://patchwork.freedesktop.org/series/64923/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR
== Series Details ==
Series: drm/i915/tgl: Add memory type decoding for bandwidth checking
URL : https://patchwork.freedesktop.org/series/67186/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6952_full -> Patchwork_14522_full
On Wed, Sep 25, 2019 at 01:08:23PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 24, 2019 at 10:59:57AM -0700, Manasi Navare wrote:
> > On Tue, Sep 24, 2019 at 05:38:00PM +0200, Maarten Lankhorst wrote:
> > > Op 22-09-2019 om 19:08 schreef Manasi Navare:
> > > > After the state is committed, we
== Series Details ==
Series: drm/i915: Don't skip debug messages when dp link config fails
URL : https://patchwork.freedesktop.org/series/67232/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956 -> Patchwork_14535
Summary
On Wed, Sep 25, 2019 at 10:59:32AM -0700, Daniele Ceraolo Spurio wrote:
+ Matt
I've reviewed this patch and this affects some of the work I'm doing on the new
GuC interface. For the new GuC interface I have two patches that rework the HW
ID assignment.
The first patch moves ownership of the
Disallow DC3CO state before PSR2 exit.
Store dc3co_exitline from crtc state to psr dev_priv
structure to use it easily whenever it requires.
v1: Moved calling of tgl_enable_psr2_transcoder_exitline() to
intel_psr_enable(). [Imre]
v2: Moved tgl_psr2_deep_sleep_enable/disable function to
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently. [Animesh]
v2: Using a switch statement for cleaner code. [Animesh]
Cc: Jani Nikula
Cc: Imre Deak
Cc:
DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset
v9 revision is a rework of series, which has fixed the review comments
provided by Imre and added Animesh's RB on following two patches.
1.Add DC3CO required register and bits
2.Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Anshuman Gupta (7):
drm/i915/tgl: Add DC3CO required register and
Add target_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
DC3CO enable bit will be used by driver to make DC3CO
ready for DMC f/w and status bit will be used as DC3CO
entry status.
2. Transcoder EXITLINE register and its bit fields and mask.
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
B.Specs:49196 has a restriction to enable DC3CO only for Video Playback.
It will be worthy to enable DC3CO after completion of
== Series Details ==
Series: drm/i915/tgl: Swap rps disable for rc6 disable (rev2)
URL : https://patchwork.freedesktop.org/series/67214/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956 -> Patchwork_14534
Summary
---
+ Matt
On 9/25/19 5:41 AM, Tvrtko Ursulin wrote:
[+ Daniele, I think he might want to have a look at this.]
On 25/09/2019 11:01, Chris Wilson wrote:
With the introduction of ctx->engines[] we allow multiple logical
contexts to be used on the same engine (e.g. with virtual engines). Each
On Wed, Sep 25, 2019 at 10:39:32AM -0700, Matt Roper wrote:
> If we don't have enough link bandwidth to support the requested mode, we
> bail out of intel_dp_compute_link_config() early before the point it
> prints the helpful debug messages containing the available/necessary
> link bandwidth.
If we don't have enough link bandwidth to support the requested mode, we
bail out of intel_dp_compute_link_config() early before the point it
prints the helpful debug messages containing the available/necessary
link bandwidth. Since failures are when these messages are most useful,
let the
== Series Details ==
Series: series starting with [1/4] drm/i915: Prepare to split crtc state in
uapi and hw state
URL : https://patchwork.freedesktop.org/series/67227/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956 -> Patchwork_14533
== Series Details ==
Series: series starting with [1/4] drm/i915: Prepare to split crtc state in
uapi and hw state
URL : https://patchwork.freedesktop.org/series/67227/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4cc35a6ea9c7 drm/i915: Prepare to split crtc state in uapi
== Series Details ==
Series: drm/edid: Add new modes from CTA-861-G (rev2)
URL : https://patchwork.freedesktop.org/series/63554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956 -> Patchwork_14532
Summary
---
On Wed, 25 Sep 2019 10:11:00 -0400
Rob Miller wrote:
> > > On Tue, 24 Sep 2019 21:53:29 +0800
> > > Jason Wang wrote:
> > > > diff --git a/drivers/vfio/mdev/vfio_mdev.c
> > > b/drivers/vfio/mdev/vfio_mdev.c
> > > > index 891cf83a2d9a..95efa054442f 100644
> > > > ---
== Series Details ==
Series: series starting with [CI,1/6] drm/i915/tgl: Add initial dkl pll support
URL : https://patchwork.freedesktop.org/series/67181/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6952_full -> Patchwork_14521_full
== Series Details ==
Series: drm/edid: Add new modes from CTA-861-G (rev2)
URL : https://patchwork.freedesktop.org/series/63554/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
196fa0d4dcc0 drm/edid: Abstract away cea_edid_modes[]
-:131: CHECK:COMPARISON_TO_NULL: Comparison to
== Series Details ==
Series: series starting with [1/3] drm/dp/mst: Reduce nested ifs
URL : https://patchwork.freedesktop.org/series/67222/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956 -> Patchwork_14531
Summary
On Wed, Sep 25, 2019 at 7:14 AM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Replace the nested ifs with a single if and a logical AND.
>
> Cc: Lyude Paul
> Signed-off-by: Ville Syrjälä
Reviewed-by: Lucas De Marchi
Lucas De Marchi
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 10
On Tue, Sep 24, 2019 at 4:21 PM Souza, Jose wrote:
>
> On Tue, 2019-09-24 at 16:00 +0300, Imre Deak wrote:
> > On Mon, Sep 23, 2019 at 03:02:54PM -0700, Lucas De Marchi wrote:
> One odd thing that I notice is that we use port instead of tc_port in
> most MG registers, those MG registers uses a
On 25/09/2019 09:23, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-23 09:10:26)
On 20/09/2019 17:35, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-20 17:22:42)
On 02/09/2019 05:02, Chris Wilson wrote:
Since we cannot allocate underneath the vm->mutex (it is used in the
== Series Details ==
Series: series starting with [1/3] drm/dp/mst: Reduce nested ifs
URL : https://patchwork.freedesktop.org/series/67222/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
598d7ec6c643 drm/dp/mst: Reduce nested ifs
9105e49ef308 drm/dp/mst: Handle arbitrary
== Series Details ==
Series: drm/i915/execlists: Simplify gen12_csb_parse
URL : https://patchwork.freedesktop.org/series/67216/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956 -> Patchwork_14530
Summary
---
On Wed, Sep 25, 2019 at 07:33:38AM -0700, Summers, Stuart wrote:
> On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote:
> > The memory type values have changed in TGL, so we need to translate
> > them
> > differently than ICL. While we're moving it, fix up the ICL
> > translation
> > for LPDDR4.
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL : https://patchwork.freedesktop.org/series/67043/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6952_full ->
On Wed, Sep 25, 2019 at 02:59:02AM +0300, Souza, Jose wrote:
> On Tue, 2019-09-24 at 18:58 +0300, Imre Deak wrote:
> > On Mon, Sep 23, 2019 at 12:55:11PM -0700, José Roberto de Souza
> > wrote:
> > > Link training is failling when running link at 2.7GHz and 1.62GHz
> > > and
> > > following BSpec
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