Quoting Chris Wilson (2019-11-21 09:10:40)
> From inside an active timeline in the execbuf ioctl, we may try to
> reclaim some space in the GGTT. We need GGTT space for all objects on
> !full-ppgtt platforms, and for context images everywhere. However, to
> free up space in the GGTT we may need to
Quoting Liu, Chuansheng (2019-11-21 01:34:24)
> Thanks for reviewing the patch, please see below comments.
>
> > > So here we install the proper handler for signal SIGTERM in the
> > > similar way. Without this patch, the GT may keep busy after
> > > running this subtest. Enabling rps should be
== Series Details ==
Series: series starting with [1/5] Revert "drm/i915/gt: Wait for new requests
in intel_gt_retire_requests()"
URL : https://patchwork.freedesktop.org/series/69802/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
283130fc48cd Revert "drm/i915/gt: Wait for new
Quoting john.c.harri...@intel.com (2019-11-21 00:31:42)
> From: John Harrison
>
> Added gen & GT info to the error capture.
>
> Signed-off-by: John Harrison
> CC: Matthew Brost
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git
From inside an active timeline in the execbuf ioctl, we may try to
reclaim some space in the GGTT. We need GGTT space for all objects on
!full-ppgtt platforms, and for context images everywhere. However, to
free up space in the GGTT we may need to remove some pinned objects
(e.g. context images)
Bonded request submission is designed to allow requests to execute in
parallel as laid out by the user. If the master request is already
finished before its bonded pair is submitted, the pair were not destined
to run in parallel and we lose the information about the master engine
to dictate
Whenever we wait on a request, make sure we actually hold a reference to
it and that it cannot be retired/freed on another CPU!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 87 +++---
1 file changed, 66 insertions(+), 21 deletions(-)
diff --git
Since retirement may be running in a worker on another CPU, it may be
skipped in the local intel_gt_wait_for_idle(). To ensure the state is
consistent for our sanity checks upon load, serialise with the remote
retirer by waiting on the timeline->mutex.
Outside of this use case, e.g. on suspend or
The major drawback of commit 7e34f4e4aad3 ("drm/i915/gen8+: Add RC6 CTX
corruption WA") is that it disables RC6 while Skylake (and friends) is
active, and we do not consider the GPU idle until all outstanding
requests have been retired and the engine switched over to the kernel
context. If
== Series Details ==
Series: Wa_1604555607 implementation and verification skip (rev3)
URL : https://patchwork.freedesktop.org/series/69763/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7395 -> Patchwork_15367
Summary
== Series Details ==
Series: Wa_1604555607 implementation and verification skip (rev3)
URL : https://patchwork.freedesktop.org/series/69763/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
915cc6805f08 drm/i915/tgl: Implement Wa_1604555607
d0118d6c3e90 drm/i915: Skip the
At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.
Helper function called wa_write_masked_or_no_verify is defined for the
same purpose.
v2:
i915 ptr retrieved from engine. [Tvrtko]
Signed-off-by: Ramalingam C
cc: Tvrtko Ursulin
---
== Series Details ==
Series: drm/i915: Add Gen/GT info to GPU error state
URL : https://patchwork.freedesktop.org/series/69793/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7394 -> Patchwork_15366
Summary
---
== Series Details ==
Series: drm/i915 / LPSS / mfd: Select correct PWM controller to use based on
VBT (rev2)
URL : https://patchwork.freedesktop.org/series/69686/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7383_full -> Patchwork_15341_full
== Series Details ==
Series: drm/i915/uc: Extra info notice about FW version mis-match vs overrides
(rev2)
URL : https://patchwork.freedesktop.org/series/69791/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7394 -> Patchwork_15365
== Series Details ==
Series: series starting with [1/3] drm/i915/bios: do not discard address space
URL : https://patchwork.freedesktop.org/series/69790/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7394 -> Patchwork_15364
== Series Details ==
Series: drm/i915/guc: CTB improvements
URL : https://patchwork.freedesktop.org/series/69788/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7394 -> Patchwork_15363
Summary
---
**SUCCESS**
No
On 2019/11/20 下午9:49, Jason Gunthorpe wrote:
On Wed, Nov 20, 2019 at 10:14:26AM +0800, Jason Wang wrote:
I don't quite get the question here.
In the driver model the bus_type and foo_device are closely
linked.
I don't get the definition of "closely linked" here. Do you think the bus
and
== Series Details ==
Series: drm/i915/guc: CTB improvements
URL : https://patchwork.freedesktop.org/series/69788/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3db17158f33d drm/i915/guc: Add non blocking CTB send function
-:6: WARNING:TYPO_SPELLING: 'fuction' may be misspelled
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Refactor
intel_commit_modeset_disables()
URL : https://patchwork.freedesktop.org/series/69787/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7393 -> Patchwork_15362
== Series Details ==
Series: drm/i915: Disable display interrupts during SDE IRQ handler
URL : https://patchwork.freedesktop.org/series/69786/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7393 -> Patchwork_15361
Summary
Please ignore this patch for now, it is missing one step in the
connector config compute phase.
On Wed, 2019-11-20 at 15:48 -0800, José Roberto de Souza wrote:
> On TGL the blending of all the streams have moved from DDI to
> transcoder, so now every transcoder working over the same MST port
>
== Series Details ==
Series: drm/i915/selftests: Always hold a reference on a waited upon request
(rev2)
URL : https://patchwork.freedesktop.org/series/69759/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7393 -> Patchwork_15360
== Series Details ==
Series: drm/i915: Disable display interrupts during SDE IRQ handler
URL : https://patchwork.freedesktop.org/series/69786/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a5c9bf9a98ce drm/i915: Disable display interrupts during SDE IRQ handler
-:27:
Thanks for reviewing the patch, please see below comments.
> > So here we install the proper handler for signal SIGTERM in the
> > similar way. Without this patch, the GT may keep busy after
> > running this subtest. Enabling rps should be tracked on the
> > other side.
> >
> > Signed-off-by:
== Series Details ==
Series: drm/i915: Use intel_gt_pm_put_async in GuC submission path
URL : https://patchwork.freedesktop.org/series/69781/
State : failure
== Summary ==
Applying: drm/i915: Use intel_gt_pm_put_async in GuC submission path
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev2)
URL : https://patchwork.freedesktop.org/series/69540/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR
== Series Details ==
Series: drm/i915/gem: Reduce flush_ggtt() from a wait-for-idle to a mere
barrier flush (rev3)
URL : https://patchwork.freedesktop.org/series/69752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7393 -> Patchwork_15357
== Series Details ==
Series: drm/i915/gem: Reduce flush_ggtt() from a wait-for-idle to a mere
barrier flush (rev3)
URL : https://patchwork.freedesktop.org/series/69752/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e0572642aeca Revert "drm/i915/gt: Wait for new requests in
== Series Details ==
Series: drm/i915: Mark intel_wakeref_get() as a sleeper
URL : https://patchwork.freedesktop.org/series/69776/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7393 -> Patchwork_15356
Summary
---
Oops. Ignore this email. Accidentally sent the same thing twice.
On 11/20/2019 16:31, john.c.harri...@intel.com wrote:
From: John Harrison
If a FW override is present then a version mis-match is actually
ignored. The warning message was still being printed, though. Which
could confuse people
From: John Harrison
Added gen & GT info to the error capture.
Signed-off-by: John Harrison
CC: Matthew Brost
---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index
From: John Harrison
If a FW override is present then a version mis-match is actually
ignored. The warning message was still being printed, though. Which
could confuse people by implying that the load had failed due to the
mis-match when actually something else had failed.
This patch adds an
From: John Harrison
If a FW override is present then a version mis-match is actually
ignored. The warning message was still being printed, though. Which
could confuse people by implying that the load had failed due to the
mis-match when actually something else had failed.
This patch adds an
On Wed, Nov 20, 2019 at 2:56 AM Daniel Vetter wrote:
>
> For locking semantics it really doesn't matter when we grab the
> ticket. But for lockdep validation it does: the acquire ctx is a fake
> lockdep. Since other drivers might want to do a full multi-lock dance
> in their fault-handler, not
We don't need to keep the pci rom mapped during the entire
intel_bios_init() anymore. Move it to the previous copy_vbt() function
and rename it to oprom_get_vbt() since now it's responsible to to all
operations related to get the vbt from the oprom.
v2: fix double __iomem attribute detected by
The unaligned ioread32() will make us read byte by byte looking for the
vbt. We could just as well have done a ioread8() + a shift and avoid the
extra confusion on how we are looking for "$VBT".
However when using ACPI it's guaranteed the VBT is 4-byte aligned
per spec, so we can probably assume
When we map the VBT through pci_map_rom() we may not be allowed
to simply discard the address space and go on reading the memory.
That doesn't work on my test system, but by dumping the rom via
sysfs I can can get the correct vbt. So change our find_vbt() to do
the same as done by pci_read_rom(),
On 11/20/19 6:11 PM, Ville Syrjälä wrote:
> On Wed, Nov 20, 2019 at 05:43:40PM +0100, Daniel Vetter wrote:
>> On Wed, Nov 20, 2019 at 06:25:12PM +0200, Ville Syrjala wrote:
>>> From: Ville Syrjälä
>>>
>>> Now that we've constrained the clipped source rectangle such
>>> that it can't have
Hi Jani,
On Wed, Nov 20, 2019 at 7:11 AM Jani Nikula wrote:
>
> On Tue, 12 Nov 2019, Rajat Jain wrote:
> > On Mon, Nov 4, 2019 at 11:41 AM Rajat Jain wrote:
> >>
> >> Certain laptops now come with panels that have integrated privacy
> >> screens on them. This patch adds support for such panels
== Series Details ==
Series: drm/i915: Extend reset modparam to domain resets
URL : https://patchwork.freedesktop.org/series/69773/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7393 -> Patchwork_15354
Summary
---
== Series Details ==
Series: drm/i915/gt: Fixup config ifdeffery for pm_suspend_target_state
URL : https://patchwork.freedesktop.org/series/69775/
State : failure
== Summary ==
Applying: drm/i915/gt: Fixup config ifdeffery for pm_suspend_target_state
error: sha1 information is lacking or
From: Matthew Brost
CTB writes are now in the path of command submission and should be
optimized for performance. Rather than reading CTB descriptor values
(e.g. head, tail, size) which could result in accesses across the PCIe
bus, store shadow local copies and only read/write the descriptor
From: Matthew Brost
With the introduction of non-blocking CTBs more than one CTB can be in
flight at a time. Increasing the size of the CTBs should reduce how
often software hits the case where no space is available in the CTB
buffer.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
From: John Harrison
These patches improve the CTB infrastructure - Command Transport
Buffer, the communication mechanism between i915 and GuC.
They are part of the (large) series for updating the i915 GuC
implementation to support the new GuC API. That series is still in
progress (but getting
From: Matthew Brost
Add non blocking CTB send fuction, intel_guc_send_nb. In order to
support a non blocking CTB send fuction a spin lock is needed to
protect the CTB descriptors fields. Also the non blocking call must not
update the fence value as this value is owned by the blocking call
Commit 9c722e17c1b9 ("drm/i915: Disable pipes in reverse order")
reverted the order that pipes gets disabled because of TGL
master/slave relationship between transcoders in MST mode.
But as stated in a comment in skl_commit_modeset_enables() the
enabling order is not always crescent, possibly
If the CRTC is going from enabled to disabled and it is a port sync
slave, it needs to check to the old state to be disabled before the
port sync master.
Cc: Manasi Navare
Cc: Matt Roper
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.
A previous approach was using the lowest pipe/transcoder as master
== Series Details ==
Series: Wa_1604555607 implementation and verification skip (rev2)
URL : https://patchwork.freedesktop.org/series/69763/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7393 -> Patchwork_15353
Summary
From: Clint Taylor
During the Display Interrupt Service routine the Display Interrupt
Enable bit must be disabled, The interrupts handled, then the
Display Interrupt Enable bit must be set to prevent possible missed
interrupts.
Bspec: 49212
Cc: Lucas De Marchi
Cc: Aditya Swarup
Signed-off-by:
== Series Details ==
Series: Wa_1604555607 implementation and verification skip (rev2)
URL : https://patchwork.freedesktop.org/series/69763/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7b2598e9881d drm/i915/tgl: Implement Wa_1604555607
004af1827d3a drm/i915: Skip the
== Series Details ==
Series: drm/i915/gt: Declare timeline.lock to be irq-free
URL : https://patchwork.freedesktop.org/series/69769/
State : failure
== Summary ==
Applying: drm/i915/gt: Declare timeline.lock to be irq-free
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: linux-next: Tree for Nov 19 (i915)
URL : https://patchwork.freedesktop.org/series/69766/
State : failure
== Summary ==
Applying: linux-next: Tree for Nov 19 (i915)
error: corrupt patch at line 12
error: could not build fake ancestor
hint: Use 'git am
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Close race between
engine_park and intel_gt_retire_requests
URL : https://patchwork.freedesktop.org/series/69765/
State : failure
== Summary ==
Applying: drm/i915/gt: Close race between engine_park and
On Wed, 2019-11-20 at 17:14 +, Summers, Stuart wrote:
> On Wed, 2019-11-20 at 17:44 +0100, Janusz Krzysztofik wrote:
> > As we've agreed that using I915_GEM_PREAD/PWRITE IOCTLs on dma-buf
> > objects doesn't make much sense, we are not going to extend their
> > handlers in the i915 driver with
== Series Details ==
Series: series starting with [1/2] drm/rect: Keep the scaled clip bounded
URL : https://patchwork.freedesktop.org/series/69760/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7391 -> Patchwork_15349
On Mon, Nov 20, 2019 at 09:18:48PM +, Ville Syrjälä wrote:
> >
> > I'm not reenabling it - this is code is out there right now.
>
> > It's _dead_ code, and it's like that on purpose. You're now attempting
> > to re-enable it without fixing the underlying issues.
>
> Sounds like some sacred
On 11/20/19 8:56 AM, Chris Wilson wrote:
> Quoting Jani Nikula (2019-11-20 16:15:08)
>> On Tue, 19 Nov 2019, Randy Dunlap wrote:
>>> On 11/19/19 12:46 AM, Stephen Rothwell wrote:
Hi all,
Changes since 20191118:
>>>
>>>
>>> on x86_64:
>>>
>>> ERROR: "pm_suspend_target_state"
Whenever we wait on a request, make sure we actually hold a reference to
it and that it cannot be retired/freed on another CPU!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 87 +++---
1 file changed, 66 insertions(+), 21 deletions(-)
diff --git
Quoting Stuart Summers (2019-11-20 21:13:21)
> GuC submission path can be called from an interrupt context
> and so should use a worker to avoid holding a mutex.
I completely forgot there was still the vestigial GuC submission code...
Ah, I was looking more carefully for engine_put in the wrong
GuC submission path can be called from an interrupt context
and so should use a worker to avoid holding a mutex.
References: 07779a76ee1f ("drm/i915: Mark up the calling context for
intel_wakeref_put()")
Signed-off-by: Stuart Summers
Cc: Chris Wilson
---
I haven't narrowed down when this started, other than "sometime between
10/23 and 11/13". Looks to me like something in the i915/DRM arena doesn't
play nice with mutex debugging.
The system still acts fine, but my /var partition filled up due to gigabytes
of the following two warning calls
FIXME: To be squashed to another patch.
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
FIXME: To be squashed to another patch.
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
== Series Details ==
Series: drm/i915/selftests: Always hold a reference on a waited upon request
URL : https://patchwork.freedesktop.org/series/69759/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7390 -> Patchwork_15348
== Series Details ==
Series: series starting with [1/2] drm/i915: Serialise with remote retirement
URL : https://patchwork.freedesktop.org/series/69757/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7390 -> Patchwork_15347
Hi Dave & Daniel,
Just one patch this week which fixes the bo refcounts when mmap'ing ttm buffers
using the new ->mmap() hook.
drm-misc-next-fixes-2019-11-20:
- Fix ttm bo refcnt when using the new gem obj mmap hook (Thomas)
Cc: Gerd Hoffmann
Cheers, Sean
The following changes since commit
Hi Dave & Daniel,
NOTE: CI shard results are delayed, bu I'm sending this
already because I'll travel tomorrow. I'll let you know
if the results look OK or not. Or you can look up
CI_DINF_162 results check at:
https://intel-gfx-ci.01.org/tree/drm-intel-next-fixes/combined-alt.html
This was
On Wed, 20 Nov 2019, "Kulkarni, Vandita" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Friday, November 15, 2019 9:04 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Kulkarni, Vandita
>> ; ville.syrj...@linux.intel.com
>> Subject: [PATCH v2 10/10]
Quoting Chris Wilson (2019-11-20 20:22:09)
> pm_suspend_target_state is declared under CONFIG_PM_SLEEP but only
> defined under CONFIG_SUSPEND. Play safe and only use the symbol if it is
> both declared and defines.
>
> Reported-by: kbuild-...@lists.01.org
> Signed-off-by: Chris Wilson
> Fixes:
From inside an active timeline in the execbuf ioctl, we may try to
reclaim some space in the GGTT. We need GGTT space for all objects on
!full-ppgtt platforms, and for context images everywhere. However, to
free up space in the GGTT we may need to remove some pinned objects
(e.g. context images)
On Mon, Nov 18, 2019 at 08:25:48PM +, Lisovskiy, Stanislav wrote:
> Hi,
>
> > > > > >
> > > > > > - /* If 2nd DBuf slice is no more required disable it */
> > > > > > - if (INTEL_GEN(dev_priv) >= 11 && required_slices <
> > > > > > hw_enabled_slices)
> > > > > > -
Quoting Chris Wilson (2019-11-20 13:41:13)
> Since we use barriers, we need only explicitly flush those barriers to
> ensure tha we can reclaim the available ggtt for ourselves. The barrier
> flush was implicit inside the intel_gt_wait_for_idle() -- except because
> we use i915_gem_evict from
Assume that intel_wakereg_get() may take the mutex, and perform other
sleeping actions in the course of its callbacks and so use might_sleep()
to ensure that all callers abide. Anything that cannot sleep has to use
e.g. intel_wakeref_get_if_active() to avoid hitting the non-atomic
paths.
== Series Details ==
Series: drm/i915: Enable second dbuf slice for ICL and TGL (rev6)
URL : https://patchwork.freedesktop.org/series/69124/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7389 -> Patchwork_15346
Summary
== Series Details ==
Series: drm/i915: Do not initialize display BW when display not available
URL : https://patchwork.freedesktop.org/series/69714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7380_full -> Patchwork_15339_full
pm_suspend_target_state is declared under CONFIG_PM_SLEEP but only
defined under CONFIG_SUSPEND. Play safe and only use the symbol if it is
both declared and defines.
Reported-by: kbuild-...@lists.01.org
Signed-off-by: Chris Wilson
Fixes: a70a9e998e8e ("drm/i915: Defer rc6 shutdown to
== Series Details ==
Series: drm/i915: Enable second dbuf slice for ICL and TGL (rev6)
URL : https://patchwork.freedesktop.org/series/69124/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
580295b9b8c3 drm/i915: Enable second dbuf slice for ICL and TGL
-:281:
On 2019-11-20 at 17:50:51 +, Tvrtko Ursulin wrote:
>
> On 20/11/2019 17:31, Ramalingam C wrote:
> > At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> > disabling the WA verification.
> >
> > Helper function called wa_write_masked_or_no_verify is defined for the
> > same
On Wed, Nov 20, 2019 at 05:50:51PM +, Tvrtko Ursulin wrote:
On 20/11/2019 17:31, Ramalingam C wrote:
At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.
Helper function called wa_write_masked_or_no_verify is defined for the
same purpose.
On 20/11/2019 17:31, Ramalingam C wrote:
At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.
Helper function called wa_write_masked_or_no_verify is defined for the
same purpose.
Signed-off-by: Ramalingam C
cc: Tvrtko Ursulin
---
On Wed, 2019-11-20 at 17:45 +, Chris Wilson wrote:
> Quoting Stuart Summers (2019-11-20 17:36:42)
> > In the event a platform does not properly implement reset,
> > do not go through reset flows for engine domains to avoid
> > an unlikely situation where writes are accepted but register
> >
On Wed, 2019-11-20 at 17:45 +, Chris Wilson wrote:
> Quoting Stuart Summers (2019-11-20 17:36:42)
> > In the event a platform does not properly implement reset,
> > do not go through reset flows for engine domains to avoid
> > an unlikely situation where writes are accepted but register
> >
Quoting Stuart Summers (2019-11-20 17:36:42)
> In the event a platform does not properly implement reset,
> do not go through reset flows for engine domains to avoid
> an unlikely situation where writes are accepted but register
> values are never cleared, as this can result in GPU wedges
> in
Quoting Stuart Summers (2019-11-20 17:36:42)
> In the event a platform does not properly implement reset,
> do not go through reset flows for engine domains to avoid
> an unlikely situation where writes are accepted but register
> values are never cleared, as this can result in GPU wedges
> in
In the event a platform does not properly implement reset,
do not go through reset flows for engine domains to avoid
an unlikely situation where writes are accepted but register
values are never cleared, as this can result in GPU wedges
in these cases.
Signed-off-by: Stuart Summers
---
On 2019-11-20 at 16:55:35 +, Tvrtko Ursulin wrote:
>
> On 20/11/2019 16:40, Ramalingam C wrote:
> > At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> > disabling the WA verification.
> >
> > Signed-off-by: Ramalingam C
> > cc: Tvrtko Ursulin
> > ---
> >
From: Michel Thierry
Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.
v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
uncore read is used
At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.
Helper function called wa_write_masked_or_no_verify is defined for the
same purpose.
Signed-off-by: Ramalingam C
cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 20
Implements the Wa_1604555607 and skips its verification as the FF_MODES2
register is writeonly till TGL B0.
Test-with: 20191120145712.27496-1-ramalinga...@intel.com
Michel Thierry (1):
drm/i915/tgl: Implement Wa_1604555607
Ramalingam C (1):
drm/i915: Skip the Wa_1604555607 verification
== Series Details ==
Series: Skip MCHBAR queries when display is not available
URL : https://patchwork.freedesktop.org/series/69712/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7380_full -> Patchwork_15338_full
Summary
On Wed, 2019-11-20 at 17:44 +0100, Janusz Krzysztofik wrote:
> As we've agreed that using I915_GEM_PREAD/PWRITE IOCTLs on dma-buf
> objects doesn't make much sense, we are not going to extend their
> handlers in the i915 driver with new processing paths required for
> them
> to work correctly with
On Wed, Nov 20, 2019 at 05:43:40PM +0100, Daniel Vetter wrote:
> On Wed, Nov 20, 2019 at 06:25:12PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Now that we've constrained the clipped source rectangle such
> > that it can't have negative dimensions doing the same for the
> > dst
Now that we never allow the intel_wakeref callbacks to be invoked from
interrupt context, we do not need the irqsafe spinlock for the timeline.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gt_requests.c | 9 -
Quoting Jani Nikula (2019-11-20 16:15:08)
> On Tue, 19 Nov 2019, Randy Dunlap wrote:
> > On 11/19/19 12:46 AM, Stephen Rothwell wrote:
> >> Hi all,
> >>
> >> Changes since 20191118:
> >
> >
> > on x86_64:
> >
> > ERROR: "pm_suspend_target_state" [drivers/gpu/drm/i915/i915.ko] undefined!
> >
> >
The general concept was that intel_timeline.active_count was locked by
the intel_timeline.mutex. The exception was for power management, where
the engine->kernel_context->timeline could be manipulated under the
global wakeref.mutex.
This was quite solid, as we always manipulated the timeline only
On 20/11/2019 16:40, Ramalingam C wrote:
At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.
Signed-off-by: Ramalingam C
cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
In commit a79ca656b648 ("drm/i915: Push the wakeref->count deferral to
the backend"), I erroneously concluded that we last modify the engine
inside __i915_request_commit() meaning that we could enable concurrent
submission for userspace as we enqueued this request. However, this
falls into a trap
Quoting Chris Wilson (2019-11-20 16:42:46)
> Since we use barriers, we need only explicitly flush those barriers to
> ensure tha we can reclaim the available ggtt for ourselves. The barrier
> flush was implicit inside the intel_gt_wait_for_idle() -- except because
> we use i915_gem_evict from
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