[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,v6,1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset

2019-12-27 Thread Patchwork
== Series Details == Series: series starting with [CI,v6,1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset URL : https://patchwork.freedesktop.org/series/71445/ State : success == Summary == CI Bug Log - changes from CI_DRM_7644_full ->

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v6,1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset

2019-12-27 Thread Patchwork
== Series Details == Series: series starting with [CI,v6,1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset URL : https://patchwork.freedesktop.org/series/71445/ State : success == Summary == CI Bug Log - changes from CI_DRM_7644 -> Patchwork_15936

[Intel-gfx] [CI v6 2/3] drm/i915/dp: Make port sync mode assignments only if all tiles present

2019-12-27 Thread Manasi Navare
Add an extra check before making master slave assignments for tiled displays to make sure we make these assignments only if all tiled connectors are present. If not then initialize the state to defaults so it does a normal non tiled modeset without transcoder port sync. v4: deafulat port sync

[Intel-gfx] [CI v6 3/3] drm/i915/dp: Disable Port sync mode correctly on teardown

2019-12-27 Thread Manasi Navare
While clearing the Ports ync mode enable and master select bits we need to clear the register completely instead of using disable masks v3: * Remove reg variable (Matt) v2: * Just write 0 to the reg (Ville) * Rebase Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5 Cc: Ville Syrjälä

[Intel-gfx] [CI v6 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset

2019-12-27 Thread Manasi Navare
In case of tiled displays, all the tiles are linke dto each other for transcoder port sync. So in intel_atomic_check() we need to make sure that we add all the tiles to the modeset and if one of the tiles needs a full modeset then mark all other tiles for a full modeset. We also need to force

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915: Add support for non-power-of-2 FB plane alignment (rev2)

2019-12-27 Thread Patchwork
== Series Details == Series: series starting with [v2,1/3] drm/i915: Add support for non-power-of-2 FB plane alignment (rev2) URL : https://patchwork.freedesktop.org/series/71444/ State : success == Summary == CI Bug Log - changes from CI_DRM_7644_full -> Patchwork_15935_full

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915: Add support for non-power-of-2 FB plane alignment (rev2)

2019-12-27 Thread Patchwork
== Series Details == Series: series starting with [v2,1/3] drm/i915: Add support for non-power-of-2 FB plane alignment (rev2) URL : https://patchwork.freedesktop.org/series/71444/ State : success == Summary == CI Bug Log - changes from CI_DRM_7644 -> Patchwork_15935

[Intel-gfx] [PATCH v2 1/3] drm/i915: Add support for non-power-of-2 FB plane alignment

2019-12-27 Thread Imre Deak
At least one framebuffer plane on TGL - the UV plane of YUV semiplanar FBs - requires a non-power-of-2 alignment, so add support for this. This new alignment restriction applies only to an offset within an FB, so the GEM buffer itself containing the FB must still be power-of-2 aligned. Add a check

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Add support for non-power-of-2 FB plane alignment

2019-12-27 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm/i915: Add support for non-power-of-2 FB plane alignment URL : https://patchwork.freedesktop.org/series/71444/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7644 -> Patchwork_15934

Re: [Intel-gfx] [PATCH v5 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset

2019-12-27 Thread Matt Roper
On Fri, Dec 27, 2019 at 03:49:15PM -0800, Manasi Navare wrote: > On Fri, Dec 27, 2019 at 03:17:07PM -0800, Matt Roper wrote: > > On Fri, Dec 27, 2019 at 02:51:28PM -0800, Manasi Navare wrote: > > > On Fri, Dec 27, 2019 at 12:03:33PM -0800, Matt Roper wrote: > > > > On Fri, Dec 27, 2019 at

[Intel-gfx] [PATCH 1/3] drm/i915: Add support for non-power-of-2 FB plane alignment

2019-12-27 Thread Imre Deak
At least one framebuffer plane on TGL - the UV plane of YUV semiplanar FBs - requires a non-power-of-2 alignment, so add support for this. This new alignment restriction applies only to an offset within an FB, so the GEM buffer itself containing the FB must still be power-of-2 aligned. Add a check

[Intel-gfx] [PATCH 3/3] drm/i915: Add debug message for FB plane[0].offset!=0 error

2019-12-27 Thread Imre Deak
Print a debug message if the FB plane[0] offset is not 0 as expected, to help understainding an add FB IOCTL fail. Cc: Chris Wilson Cc: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_display.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned

2019-12-27 Thread Imre Deak
Currently the start address of a UV plane in a semiplanar YUV FB is tile size (4kB) aligned. I noticed, that enforcing only this alignment leads oddly to random memory corruptions on TGL while scanning out Y-tiled FBs. This issue can be easily reproduced with a UV plane that is not aligned to the

Re: [Intel-gfx] [PATCH v5 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset

2019-12-27 Thread Manasi Navare
On Fri, Dec 27, 2019 at 03:17:07PM -0800, Matt Roper wrote: > On Fri, Dec 27, 2019 at 02:51:28PM -0800, Manasi Navare wrote: > > On Fri, Dec 27, 2019 at 12:03:33PM -0800, Matt Roper wrote: > > > On Fri, Dec 27, 2019 at 11:27:50AM -0800, Manasi Navare wrote: > > > > On Fri, Dec 27, 2019 at

Re: [Intel-gfx] [PATCH v5 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset

2019-12-27 Thread Matt Roper
On Fri, Dec 27, 2019 at 02:51:28PM -0800, Manasi Navare wrote: > On Fri, Dec 27, 2019 at 12:03:33PM -0800, Matt Roper wrote: > > On Fri, Dec 27, 2019 at 11:27:50AM -0800, Manasi Navare wrote: > > > On Fri, Dec 27, 2019 at 10:36:52AM -0800, Matt Roper wrote: > > > > On Mon, Dec 23, 2019 at

Re: [Intel-gfx] [PATCH v5 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset

2019-12-27 Thread Manasi Navare
On Fri, Dec 27, 2019 at 12:03:33PM -0800, Matt Roper wrote: > On Fri, Dec 27, 2019 at 11:27:50AM -0800, Manasi Navare wrote: > > On Fri, Dec 27, 2019 at 10:36:52AM -0800, Matt Roper wrote: > > > On Mon, Dec 23, 2019 at 02:44:27PM -0800, Manasi Navare wrote: > > > > In case of tiled displays, all

Re: [Intel-gfx] [PATCH v5 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset

2019-12-27 Thread Matt Roper
On Fri, Dec 27, 2019 at 11:27:50AM -0800, Manasi Navare wrote: > On Fri, Dec 27, 2019 at 10:36:52AM -0800, Matt Roper wrote: > > On Mon, Dec 23, 2019 at 02:44:27PM -0800, Manasi Navare wrote: > > > In case of tiled displays, all the tiles are linke dto each other > > > for transcoder port sync. So

Re: [Intel-gfx] [PATCH v5 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset

2019-12-27 Thread Manasi Navare
On Fri, Dec 27, 2019 at 10:36:52AM -0800, Matt Roper wrote: > On Mon, Dec 23, 2019 at 02:44:27PM -0800, Manasi Navare wrote: > > In case of tiled displays, all the tiles are linke dto each other > > for transcoder port sync. So in intel_atomic_check() we need to make > > sure that we add all the

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/lmem: debugfs for LMEM details (rev5)

2019-12-27 Thread Patchwork
== Series Details == Series: drm/i915/lmem: debugfs for LMEM details (rev5) URL : https://patchwork.freedesktop.org/series/71211/ State : success == Summary == CI Bug Log - changes from CI_DRM_7642_full -> Patchwork_15933_full Summary

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Workaround updates (rev3)

2019-12-27 Thread Matt Roper
On Fri, Dec 27, 2019 at 10:35:58AM +, Patchwork wrote: > == Series Details == > > Series: Workaround updates (rev3) > URL : https://patchwork.freedesktop.org/series/71337/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_7633_full -> Patchwork_15917_full >

Re: [Intel-gfx] [PATCH v5 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset

2019-12-27 Thread Matt Roper
On Mon, Dec 23, 2019 at 02:44:27PM -0800, Manasi Navare wrote: > In case of tiled displays, all the tiles are linke dto each other > for transcoder port sync. So in intel_atomic_check() we need to make > sure that we add all the tiles to the modeset and if one of the > tiles needs a full modeset

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add support for mipi dsi cmd mode (rev3)

2019-12-27 Thread Patchwork
== Series Details == Series: Add support for mipi dsi cmd mode (rev3) URL : https://patchwork.freedesktop.org/series/69290/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7642_full -> Patchwork_15931_full Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/lmem: debugfs for LMEM details (rev5)

2019-12-27 Thread Patchwork
== Series Details == Series: drm/i915/lmem: debugfs for LMEM details (rev5) URL : https://patchwork.freedesktop.org/series/71211/ State : success == Summary == CI Bug Log - changes from CI_DRM_7642 -> Patchwork_15933 Summary ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Err out on coherency if initialisation failed

2019-12-27 Thread Patchwork
== Series Details == Series: drm/i915/selftests: Err out on coherency if initialisation failed URL : https://patchwork.freedesktop.org/series/71433/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7642 -> Patchwork_15932

[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for mipi dsi cmd mode (rev3)

2019-12-27 Thread Patchwork
== Series Details == Series: Add support for mipi dsi cmd mode (rev3) URL : https://patchwork.freedesktop.org/series/69290/ State : success == Summary == CI Bug Log - changes from CI_DRM_7642 -> Patchwork_15931 Summary ---

Re: [Intel-gfx] [PATCH 3/3] drm/i915/selftests: Add selftest for memory region PF handling

2019-12-27 Thread kbuild test robot
Hi Abdiel, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip next-20191220] [cannot apply to v5.5-rc3] [if your patch is applied to the wrong git tree, please drop us a note to help improve the

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Assume future platforms will inherit TGL's SFC capability (rev2)

2019-12-27 Thread Patchwork
== Series Details == Series: drm/i915/tgl: Assume future platforms will inherit TGL's SFC capability (rev2) URL : https://patchwork.freedesktop.org/series/71371/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7637_full -> Patchwork_15927_full

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/lmem: debugfs for LMEM details (rev5)

2019-12-27 Thread Patchwork
== Series Details == Series: drm/i915/lmem: debugfs for LMEM details (rev5) URL : https://patchwork.freedesktop.org/series/71211/ State : warning == Summary == $ dim checkpatch origin/drm-tip 98a202b99116 drm/i915/lmem: debugfs for LMEM details -:110: CHECK:MACRO_ARG_REUSE: Macro argument

[Intel-gfx] [PATCH v5] drm/i915/lmem: debugfs for LMEM details

2019-12-27 Thread Ramalingam C
From: Lukasz Fiedorowicz Debugfs i915_gem_object is extended to enable the IGTs to detect the LMEM's availability and the total size of LMEM. v2: READ_ONCE is used [Chris] v3: %pa is used for printing the resource [Chris] v4: All regions' details added to debugfs [Chris] v5: Macro

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsb: Increase log level if DSB engine gets busy

2019-12-27 Thread Patchwork
== Series Details == Series: drm/i915/dsb: Increase log level if DSB engine gets busy URL : https://patchwork.freedesktop.org/series/71379/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7634_full -> Patchwork_15923_full

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for mipi dsi cmd mode (rev3)

2019-12-27 Thread Patchwork
== Series Details == Series: Add support for mipi dsi cmd mode (rev3) URL : https://patchwork.freedesktop.org/series/69290/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/dsi: Configure transcoder operation for command mode. Okay! Commit:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for mipi dsi cmd mode (rev3)

2019-12-27 Thread Patchwork
== Series Details == Series: Add support for mipi dsi cmd mode (rev3) URL : https://patchwork.freedesktop.org/series/69290/ State : warning == Summary == $ dim checkpatch origin/drm-tip b55a84ce9635 drm/i915/dsi: Configure transcoder operation for command mode. fa9a3ef77fd2 drm/i915/dsi: Add

Re: [Intel-gfx] [PATCH v4] drm/i915/lmem: debugfs for LMEM details

2019-12-27 Thread Chris Wilson
Quoting Ramalingam C (2019-12-24 08:43:00) > From: Lukasz Fiedorowicz > > Debugfs i915_gem_object is extended to enable the IGTs to > detect the LMEM's availability and the total size of LMEM. > > v2: READ_ONCE is used [Chris] > v3: %pa is used for printing the resource [Chris] > v4: All

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,01/10] drm/i915: simplify prefixes on device_info (rev3)

2019-12-27 Thread Patchwork
== Series Details == Series: series starting with [CI,01/10] drm/i915: simplify prefixes on device_info (rev3) URL : https://patchwork.freedesktop.org/series/71341/ State : success == Summary == CI Bug Log - changes from CI_DRM_7633_full -> Patchwork_15919_full

[Intel-gfx] ✓ Fi.CI.IGT: success for Workaround updates (rev3)

2019-12-27 Thread Patchwork
== Series Details == Series: Workaround updates (rev3) URL : https://patchwork.freedesktop.org/series/71337/ State : success == Summary == CI Bug Log - changes from CI_DRM_7633_full -> Patchwork_15917_full Summary --- **SUCCESS**

[Intel-gfx] [PATCH] drm/i915/selftests: Err out on coherency if initialisation failed

2019-12-27 Thread Chris Wilson
If gt initialisation failed, we are left with no engines to use for coherency testing. Currently we bug out, which makes the actual error, so fail more gracefully instead. Closes: https://gitlab.freedesktop.org/drm/intel/issues/896 Signed-off-by: Chris Wilson ---

[Intel-gfx] [V4 7/8] drm/i915/dsi: Add TE handler for dsi cmd mode.

2019-12-27 Thread Vandita Kulkarni
In case of dual link, we get the TE on slave. So clear the TE on slave DSI IIR. v2: Pass only relevant masked bits to the handler (Jani) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/i915_irq.c | 64 + 1 file changed, 64 insertions(+) diff --git

[Intel-gfx] [V4 6/8] drm/i915/dsi: Configure TE interrupt for cmd mode

2019-12-27 Thread Vandita Kulkarni
We need to configure TE interrupt in two places. Port interrupt and DSI interrupt mask registers. v2: Hide the private flags check inside configure_te (Jani) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/i915_irq.c | 55 +++-- 1 file changed, 53

[Intel-gfx] [V4 3/8] drm/i915/dsi: Add cmd mode flags in display mode private flags

2019-12-27 Thread Vandita Kulkarni
Adding TE flags and periodic command mode flags as part of private flags to indicate what TE interrupts we would be getting instead of vblanks in case of mipi dsi command mode. v2: Add TE flag description (Jani) Reviewed-by: Jani Nikula Signed-off-by: Vandita Kulkarni ---

[Intel-gfx] [V4 1/8] drm/i915/dsi: Configure transcoder operation for command mode.

2019-12-27 Thread Vandita Kulkarni
Configure the transcoder to operate in TE GATE command mode and take TE events from GPIO. Also disable the periodic command mode, that GOP would have programmed. v2: Disable util pin (Jani) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 52

[Intel-gfx] [V4 2/8] drm/i915/dsi: Add vblank calculation for command mode

2019-12-27 Thread Vandita Kulkarni
Transcoder timing calculation differ for command mode. v2: Use is_vid_mode, and use same I915_WRITE (Jani) v3: Adjust the calculations to reflect dsc compression ratio Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 52 +- 1 file changed, 35

[Intel-gfx] [V4 8/8] drm/i915/dsi: Initiate fame request in cmd mode

2019-12-27 Thread Vandita Kulkarni
In TE Gate mode, on every flip we need to set the frame update request bit. After this bit is set transcoder hardware will automatically send the frame data to the panel when it receives the TE event. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 22

[Intel-gfx] [V4 5/8] drm/i915/dsi: Use private flags to indicate TE in cmd mode

2019-12-27 Thread Vandita Kulkarni
On dsi cmd mode we do not receive vblanks instead we would get TE and these flags indicate TE is expected on which port. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 14 ++ 1 file changed, 14 insertions(+) diff --git

[Intel-gfx] [V4 4/8] drm/i915/dsi: Add check for periodic command mode

2019-12-27 Thread Vandita Kulkarni
If the GOP has programmed periodic command mode, we need to disable that which would need a deconfigure and configure sequence. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 23 +++ 1 file changed, 23 insertions(+) diff --git

[Intel-gfx] [V4 0/8] Add support for mipi dsi cmd mode

2019-12-27 Thread Vandita Kulkarni
Address the comments on v2 and rebase v3 on top of vdsc mipi dsi patches. Vandita Kulkarni (8): drm/i915/dsi: Configure transcoder operation for command mode. drm/i915/dsi: Add vblank calculation for command mode drm/i915/dsi: Add cmd mode flags in display mode private flags drm/i915/dsi:

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/lmem: debugfs for LMEM details (rev4)

2019-12-27 Thread Patchwork
== Series Details == Series: drm/i915/lmem: debugfs for LMEM details (rev4) URL : https://patchwork.freedesktop.org/series/71211/ State : success == Summary == CI Bug Log - changes from CI_DRM_7632_full -> Patchwork_15915_full Summary

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Introduce remap_io_sg() to prefault discontiguous objects

2019-12-27 Thread kbuild test robot
Hi Abdiel, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip v5.5-rc3 next-20191220] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we