== Series Details ==
Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer.
URL : https://patchwork.freedesktop.org/series/72729/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7838_full -> Patchwork_16316_full
== Series Details ==
Series: drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
URL : https://patchwork.freedesktop.org/series/72724/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7838_full -> Patchwork_16315_full
== Series Details ==
Series: drm/i915/gt: Skip rmw for masked registers (rev4)
URL : https://patchwork.freedesktop.org/series/72776/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16371
Summary
---
== Series Details ==
Series: drm/i915/tgl: Implement Wa_1606931601 (rev4)
URL : https://patchwork.freedesktop.org/series/72433/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16370
Summary
---
== Series Details ==
Series: drm/i915/tgl: Add Wa_1606054188:tgl (rev2)
URL : https://patchwork.freedesktop.org/series/72839/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16369
Summary
---
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs
URL : https://patchwork.freedesktop.org/series/72853/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16368
== Series Details ==
Series: drm/i915/tgl: Add Wa_1606054188:tgl (rev2)
URL : https://patchwork.freedesktop.org/series/72839/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e0d47ccc6c89 drm/i915/tgl: Add Wa_1606054188:tgl
-:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs
URL : https://patchwork.freedesktop.org/series/72853/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
974c950dba68 drm: add DP 1.4 VSC SDP Payload related enums
b5932d8b337a drm/i915: Add
== Series Details ==
Series: drm: Add support for DP 1.4 Compliance edid corruption test (rev4)
URL : https://patchwork.freedesktop.org/series/70530/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16367
== Series Details ==
Series: series starting with [1/4] drm/i915/display: Wake the power well during
resume
URL : https://patchwork.freedesktop.org/series/72849/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16366
== Series Details ==
Series: drm: Add support for DP 1.4 Compliance edid corruption test (rev4)
URL : https://patchwork.freedesktop.org/series/70530/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bd9dc1267ab5 drm: Add support for DP 1.4 Compliance edid corruption test
-:51:
== Series Details ==
Series: series starting with [1/4] drm/i915/display: Wake the power well during
resume
URL : https://patchwork.freedesktop.org/series/72849/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ced9ffb2a020 drm/i915/display: Wake the power well during resume
A masked register does not need rmw to update, and it is best not to use
such a sequence.
Reported-by: Ville Syrjälä
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 63 ++-
== Series Details ==
Series: series starting with [1/2] drm/i915: Initialise basic fence before
acquiring seqno
URL : https://patchwork.freedesktop.org/series/72845/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16365
Disable Early Read and Src Swap (bit 14) by setting the chicken
register.
BSpec: 46045,52890
v2: Follow the Bspec implementation for the WA.
v3: Have 2 separate defines for bit 14 and 15.
- Rename register definitions with TGL_ prefix
v4: Bspec changed. Again. Add WA to rcs_ WA list.
Cc:
On Tiger Lake we do not support source keying in the pixel formats P010,
P012, P016.
v2: Move WA to end of function. Create helper function for format
check. Less verbose debugging messaging.
v3: whitespace
Bspec: 52890
Cc: Matt Roper
Cc: Manasi Navare
CC: Ville Syrjälä
Signed-off-by: Matt
== Series Details ==
Series: drm/i915/tgl: Add Wa_1606054188:tgl
URL : https://patchwork.freedesktop.org/series/72839/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16364
Summary
---
**SUCCESS**
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked
registers (rev2)
URL : https://patchwork.freedesktop.org/series/72804/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16362
== Series Details ==
Series: drm/i915/tgl: Add Wa_1606054188:tgl
URL : https://patchwork.freedesktop.org/series/72839/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
53bdc3c76702 drm/i915/tgl: Add Wa_1606054188:tgl
-:31: ERROR:SWITCH_CASE_INDENT_LEVEL: switch and case should be
== Series Details ==
Series: series starting with [1/3] drm/i915: Introduce
encoder->compute_config_late()
URL : https://patchwork.freedesktop.org/series/72836/
State : failure
== Summary ==
Applying: drm/i915: Introduce encoder->compute_config_late()
Applying: drm/i915/dp: Compute port sync
== Series Details ==
Series: drm/i915/guc: Introduce guc_is_ready (rev2)
URL : https://patchwork.freedesktop.org/series/72825/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16361
Summary
---
Dump out the DP VSC SDP in the normal crtc state dump
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
Added state readout for DP HDR Metadata Infoframe SDP.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a
In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.
Before applying it, routines of program SDP always calculated configs when
they
Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp()
to make sure not to send VSC SDP and HDR Metadata Infoframe SDP.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 43
2 files changed, 44 insertions(+)
diff --git
Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump.
HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata
Infoframe SDP use the same member variable in infoframes of crtc state.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display.c
Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the
normal crtc state dump.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
Call intel_dp_set_infoframes() function on pipe updates to make sure
that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable)
on fastsets.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
1 file changed, 1 insertion(+)
diff --git
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own intel_dp_vsc_sdp structure
member variable on struct i915_psr.
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 173
drivers/gpu/drm/i915/display/intel_dp.h | 4 +
2 files changed, 177 insertions(+)
It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.
It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header
It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.
In contrast to
It stores computed dp hdr metadata infoframe sdp to infoframes.drm of
crtc state. It referenced intel_hdmi_compute_drm_infoframe().
While computing, we'll also fill out the inforames.enable bitmask
appropriately.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 21
It stores computed dp vsc sdp to infoframes.vsc of crtc state.
While computing we'll also fill out the inforames.enable bitmask
appropriately.
The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
Signed-off-by: Gwan-gyeong Mun
---
It adds new enumeration definitions for VSC SDP Payload for Pixel
Encoding/Colorimetry Format.
enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
And enum dp_content_type corresponds "Content Type"
All
It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to pack DP HDR Metadata
In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
It adds new compute routines for DP HDR Metadata Infoframe SDP
and DP VSC SDP.
And new writing routines of DP SDPs (Secondary Data Packet) that uses
computed
In order to support state readout for DP VSC SDP, we need to have a
structure which holds DP VSC SDP payload data such as
"union hdmi_infoframe drm" which is used for DRM infoframe.
And In order to support DP HDR10, we have to support VSC SDP and
HDR Metadata Infoframe SDP. As we will use drm
Hi!
I use GPUVis and now Intel Vtune Profiler. These tools don't work
out-of-the-box on all Linux based systems for Intel integrated graphics.
It is needed to rebuild at least i915 module. And each time when the kernel
is updated it is needed to rebuild i915 module again.
> No numbers from
On 2020-01-31 3:24 p.m., Jerry (Fangzhi) Zuo wrote:
> Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
> real CRC value of the last edid data block, and write it back.
> Current edid CRC calculates routine adds the last CRC byte,
> and check if non-zero.
>
> This behavior is not
Hi!
I use GPUVis and now Intel Vtune Profiler. These tools don't work
out-of-the-box on all Linux based systems for Intel integrated graphics.
It is needed to rebuild at least i915 module. And each time when the
kernel is updated it is needed to rebuild i915 module again.
> No numbers from
Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
real CRC value of the last edid data block, and write it back.
Current edid CRC calculates routine adds the last CRC byte,
and check if non-zero.
This behavior is not accurate; actually, we need to return
the actual CRC value when
Hi!I use GPUVis and now Intel Vtune Profiler. These tools don't work out-of-the-box on all Linux based systems for Intel integrated graphics.It is needed to rebuild at least i915 module. And each time when the kernel is updated it is needed to rebuild i915 module again. > No numbers from
Hi!
I use GPUVis and now Intel Vtune Profiler. These tools don't work
out-of-the-box on all Linux based systems for Intel integrated graphics.
It is needed to rebuild at least i915 module. And each time when the kernel
is updated it is needed to rebuild i915 module again.
> No numbers from
Hi!
I use GPUVis and now Intel Vtune Profiler. These tools don't work
out-of-the-box on all Linux based systems for Intel integrated graphics.
It is needed to rebuild at least i915 module. And each time when the
kernel is updated it is needed to rebuild i915 module again.
> No numbers from
On Fri, Jan 31, 2020 at 01:00:54PM +0200, Lionel Landwerlin wrote:
On 31/01/2020 01:54, Umesh Nerlige Ramappa wrote:
On Mon, Jan 27, 2020 at 11:16:32AM +0200, Lionel Landwerlin wrote:
[snip]
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1323,7 +1323,12 @@
On Fri, Jan 31, 2020 at 10:05:03PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 31, 2020 at 11:46:25AM -0800, Manasi Navare wrote:
> > On Fri, Jan 31, 2020 at 07:53:23PM +0200, Ville Syrjälä wrote:
> > > On Fri, Jan 31, 2020 at 09:15:47AM -0800, Manasi Navare wrote:
> > > > If one of the synced crtcs
Inside the intel_timeline_get_seqno(), we currently track the retirement
of the old cachelines by listening to the new request. This requires
that the new request is ready to be used and so requires a minimum bit
of initialisation prior to getting the new seqno.
Signed-off-by: Chris Wilson
Cc:
Acquire the power well before writing the setup during resume so that
our mmio are not dropped. E.g. on Braswell we see,
<4> [135.959703] i915 :00:02.0: Unclaimed write to register 0x1e0100
<4> [135.959936] WARNING: CPU: 1 PID: 3085 at
drivers/gpu/drm/i915/intel_uncore.c:1166
Exercise the seqno wrap paths on the kernel context to provide a small
amount of sanity checking and ensure that they are visible to lockdep.
Signed-off-by: Chris Wilson
Cc: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 171
1 file changed, 171
On seqno rollover, we need to allocate ourselves a new cacheline. This
might incur grabbing a new page and pinning it into the GGTT, with some
rather unfortunate lockdep implications.
To avoid a mutex, and more specifically pinning in the GGTT from inside
the kernel context being used to flush
Inside the intel_timeline_get_seqno(), we currently track the retirement
of the old cachelines by listening to the new request. This requires
that the new request is ready to be used and so requires a minimum bit
of initialisation prior to getting the new seqno.
Signed-off-by: Chris Wilson
Cc:
On seqno rollover, we need to allocate ourselves a new cacheline. This
might incur grabbing a new page and pinning it into the GGTT, with some
rather unfortunate lockdep implications.
To avoid a mutex, and more specifically pinning in the GGTT from inside
the kernel context being used to flush
== Series Details ==
Series: drm/i915/guc: Stop using mutex while sending CTB messages
URL : https://patchwork.freedesktop.org/series/72827/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16359
Summary
== Series Details ==
Series: disable drm_global_mutex for most drivers (rev4)
URL : https://patchwork.freedesktop.org/series/72711/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16357
Summary
---
On Fri, Jan 31, 2020 at 11:46:25AM -0800, Manasi Navare wrote:
> On Fri, Jan 31, 2020 at 07:53:23PM +0200, Ville Syrjälä wrote:
> > On Fri, Jan 31, 2020 at 09:15:47AM -0800, Manasi Navare wrote:
> > > If one of the synced crtcs needs a full modeset, we need
> > > to make sure all the synced crtcs
On Fri, Jan 31, 2020 at 07:53:23PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 31, 2020 at 09:15:47AM -0800, Manasi Navare wrote:
> > If one of the synced crtcs needs a full modeset, we need
> > to make sure all the synced crtcs are forced a full
> > modeset.
> >
> > Suggested-by: Ville Syrjälä
>
On Fri, Jan 31, 2020 at 10:19:51PM -0500, Matt Atwood wrote:
> On Tiger Lake we do not support source keying in the pixel formats P010,
> P012, P016.
>
> v2: Move WA to end of function. Create helper function for format
> check. Less verbose debugging messaging.
>
> Bspec: 52890
> Cc: Matt Roper
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Also use async bind for
PIN_USER into bsw/bxt ggtt (rev3)
URL : https://patchwork.freedesktop.org/series/72809/
State : failure
== Summary ==
Applying: drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt
== Series Details ==
Series: disable drm_global_mutex for most drivers (rev4)
URL : https://patchwork.freedesktop.org/series/72711/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ec6b1085531d drm: Complain if drivers still use the ->load callback
-:48:
== Series Details ==
Series: drm/i915/selftests: Disable heartbeat around hang tests
URL : https://patchwork.freedesktop.org/series/72821/
State : failure
== Summary ==
Applying: drm/i915/selftests: Disable heartbeat around hang tests
Using index info to reconstruct a base tree...
M
On 1/31/20 2:45 AM, Chris Wilson wrote:
We want to separate the utility functions for controlling the logical
ring context from the execlists submission mechanism (which is an
overgrown scheduler).
This is similar to Daniele's work to split up the files, but being
selfish I wanted to base it
== Series Details ==
Series: drm/i915: Add missing HDMI audio pixel clocks for gen12 (rev2)
URL : https://patchwork.freedesktop.org/series/72617/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7835_full -> Patchwork_16310_full
On Tiger Lake we do not support source keying in the pixel formats P010,
P012, P016.
v2: Move WA to end of function. Create helper function for format
check. Less verbose debugging messaging.
Bspec: 52890
Cc: Matt Roper
Cc: Manasi Navare
CC: Ville Syrjälä
Signed-off-by: Matt Atwood
---
On Fri, Jan 31, 2020 at 09:15:47AM -0800, Manasi Navare wrote:
> If one of the synced crtcs needs a full modeset, we need
> to make sure all the synced crtcs are forced a full
> modeset.
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
>
On Fri, Jan 31, 2020 at 09:15:46AM -0800, Manasi Navare wrote:
> This patch pushes out the computation of master and slave
> transcoders in crtc states after encoder's compute_config hook.
> This ensures that the assigned master slave crtcs have exact same
> mode and timings which is a requirement
On 31-01-2020 17:33, Ville Syrjälä wrote:
On Fri, Jan 31, 2020 at 05:12:58PM +0530, Animesh Manna wrote:
If lmem is supported DSB should use local memeory instead
of system memory. Using local memory surely bring performance
improvement as local memory is close to gpu. Also want to avoid
From: Ville Syrjälä
Add an optional secondary encoder state compute hook. This gets
called after the normak .compute_config() has been called for
all the encoders in the state. Thus in the new hook we can rely
on all derived state populated by .compute_config() to be already
set up. Should be
If one of the synced crtcs needs a full modeset, we need
to make sure all the synced crtcs are forced a full
modeset.
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 88 +
This patch pushes out the computation of master and slave
transcoders in crtc states after encoder's compute_config hook.
This ensures that the assigned master slave crtcs have exact same
mode and timings which is a requirement for Port sync mode
to be enabled.
Suggested-by: Ville Syrjälä
Cc:
On Fri, 31 Jan 2020 17:40:12 +0100, Matthew Brost
wrote:
On Fri, Jan 31, 2020 at 03:33:55PM +, Chris Wilson wrote:
Quoting Michal Wajdeczko (2020-01-31 14:58:34)
While we are always using CT "send" buffer to send request messages
to GuC, we usually don't ask GuC to use CT "receive"
On Fri, 31 Jan 2020 16:33:55 +0100, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2020-01-31 14:58:34)
While we are always using CT "send" buffer to send request messages
to GuC, we usually don't ask GuC to use CT "receive" buffer to send
back response messages, since almost all returned
On Fri, Jan 31, 2020 at 03:33:55PM +, Chris Wilson wrote:
Quoting Michal Wajdeczko (2020-01-31 14:58:34)
While we are always using CT "send" buffer to send request messages
to GuC, we usually don't ask GuC to use CT "receive" buffer to send
back response messages, since almost all returned
Reducing audience as this series is of high interest externally.
I fully agree with Joonas' suggestion here, and we have been looking at doing
just that. But can we iterate as a follow up patch series? Putting in the infra
to support igt assembly from source will take a little time (igt
Quoting Michal Wajdeczko (2020-01-31 15:37:06)
> We already have guc_is_running function, but it only reflects
> firmware status, while to fully use GuC we need to know if we've
> already established communication with it.
>
> v2: also s/intel_guc_is_running/intel_guc_is_fw_running (Chris)
>
>
We already have guc_is_running function, but it only reflects
firmware status, while to fully use GuC we need to know if we've
already established communication with it.
v2: also s/intel_guc_is_running/intel_guc_is_fw_running (Chris)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Quoting Michal Wajdeczko (2020-01-31 14:58:34)
> While we are always using CT "send" buffer to send request messages
> to GuC, we usually don't ask GuC to use CT "receive" buffer to send
> back response messages, since almost all returned data can fit into
> reserved bits in status dword inside CT
Commit 4f2a572eda67 ("drm/i915/userptr: Never allow userptr into the
mappable GGTT") made I915_GEM_MMAP_GTT IOCTLs to fail when attempted
on a userptr object in order to protect from a lockdep splat. Later
on, new mapping types were introduced by commit cc662126b413
("drm/i915: Introduce
On Tue, Jan 28, 2020 at 03:33:11PM -0800, Matt Roper wrote:
> On Fri, Jan 24, 2020 at 10:44:55AM +0200, Stanislav Lisovskiy wrote:
> > Now using power_domain mutex to protect from race condition, which
> > can occur because intel_dbuf_slices_update might be running in
> > parallel to
== Series Details ==
Series: drm/i915/dsb: Enable lmem for dsb
URL : https://patchwork.freedesktop.org/series/72818/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7850 -> Patchwork_16355
Summary
---
**SUCCESS**
On Tue, Jan 28, 2020 at 03:37:06PM -0800, Matt Roper wrote:
> On Fri, Jan 24, 2020 at 10:44:56AM +0200, Stanislav Lisovskiy wrote:
> > During full modeset, global state(i.e dev_priv) is protected
> > by locking the crtcs in state, otherwise global state is not
> > serialized. Also if it is not a
On Friday, January 31, 2020 3:32:21 PM CET Chris Wilson wrote:
> Quoting Janusz Krzysztofik (2020-01-31 13:20:37)
> > Commit 4f2a572eda67 ("drm/i915/userptr: Never allow userptr into the
> > mappable GGTT") made I915_GEM_MMAP_GTT IOCTLs to fail when atepmted
> > on a userptr object in order to
On Mon, Jan 20, 2020 at 07:47:12PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The linetime watermarks really have very little in common with the
> plane watermarks. It looks to be cleaner to simply track them in
> the crtc_state and program them from the normal modeset/fastset
>
Chris Wilson writes:
> Since PIN_GLOBAL is no longer guaranteed to be synchronous, we must no
> forget to include a wait-for-vma prior to execution.
Dunno if we got em all, we soon know.
Cried for helper but lets move first,
Reviewed-by: Mika Kuoppala
>
> Signed-off-by: Chris Wilson
> ---
While we are always using CT "send" buffer to send request messages
to GuC, we usually don't ask GuC to use CT "receive" buffer to send
back response messages, since almost all returned data can fit into
reserved bits in status dword inside CT descriptor. However, relying
on data modifications
== Series Details ==
Series: drm/i915/dsb: Enable lmem for dsb
URL : https://patchwork.freedesktop.org/series/72818/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1dd958225f8b drm/i915/dsb: Enable lmem for dsb
-:6: WARNING:TYPO_SPELLING: 'memeory' may be misspelled - perhaps
On Friday, January 31, 2020 3:37:05 PM CET Chris Wilson wrote:
> Quoting Janusz Krzysztofik (2020-01-31 13:12:34)
> > Creating a mapping to a userptr backed GEM object may cause a currently
> > unavoidable lockdep splat inside the i915 driver. Then, such operation
> > is expected to fail to
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Also use async bind for
PIN_USER into bsw/bxt ggtt (rev2)
URL : https://patchwork.freedesktop.org/series/72809/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7850 -> Patchwork_16354
On Friday, January 31, 2020 3:32:21 PM CET Chris Wilson wrote:
> Quoting Janusz Krzysztofik (2020-01-31 13:20:37)
> > Commit 4f2a572eda67 ("drm/i915/userptr: Never allow userptr into the
> > mappable GGTT") made I915_GEM_MMAP_GTT IOCTLs to fail when atepmted
> > on a userptr object in order to
Chris Wilson writes:
> In the rare cases where we are using the global GGTT for execution in
> the selftests, we have marked them with PIN_USER knowing that they will
> be bound as PIN_GLOBAL as well. However, we need to catch the extra flag
> in deciding to use the async worker for such binds
Quoting Janusz Krzysztofik (2020-01-31 13:12:34)
> Creating a mapping to a userptr backed GEM object may cause a currently
> unavoidable lockdep splat inside the i915 driver. Then, such operation
> is expected to fail to prevent from that badness to happen.
>
> Add a respective subtest for each
== Series Details ==
Series: series starting with [01/12] drm/i915/gem: Require per-engine reset
support for non-persistent contexts
URL : https://patchwork.freedesktop.org/series/72813/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7850 -> Patchwork_16353
Quoting Janusz Krzysztofik (2020-01-31 13:20:37)
> Commit 4f2a572eda67 ("drm/i915/userptr: Never allow userptr into the
> mappable GGTT") made I915_GEM_MMAP_GTT IOCTLs to fail when atepmted
> on a userptr object in order to protect from a lockdep splat. Later
> on, new mapping types were
Since PIN_GLOBAL is no longer guaranteed to be synchronous, we must no
forget to include a wait-for-vma prior to execution.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++
drivers/gpu/drm/i915/gt/selftest_lrc.c| 33 +++
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Also use async bind for
PIN_USER into bsw/bxt ggtt (rev2)
URL : https://patchwork.freedesktop.org/series/72809/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bb9f5c3f2305 drm/i915/gt: Also use async bind for
== Series Details ==
Series: series starting with [01/12] drm/i915/gem: Require per-engine reset
support for non-persistent contexts
URL : https://patchwork.freedesktop.org/series/72813/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d94430028946 drm/i915/gem: Require
Quoting Michal Wajdeczko (2020-01-31 13:26:10)
> We already have guc_is_running function, but it only reflects
> firmware status, while to fully use GuC we need to know if we've
> already established communication with it.
"Ready, set, go!"
ready has connotations of being before running, whereas
Quoting Mika Kuoppala (2020-01-31 13:22:38)
> Chris Wilson writes:
>
> > If the heartbeat fires in the middle of the preempt-hang test, it
> > consumes our forced hang disrupting the test.
> >
> > Reported-by: Daniel Vetter
> > Signed-off-by: Chris Wilson
> > ---
> >
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