On Tue, Jun 30, 2020 at 07:29:09PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 30, 2020 at 02:26:09PM +0300, Stanislav Lisovskiy wrote:
> > We still need "Bump up CDCLK" workaround otherwise getting
> > underruns - however currently it blocks 8K as CDCLK = Pixel rate,
> > in 8K case would require
We have a mix of dport, intel_dport, intel_dig_port and dig_port to
reference a intel_digital_port struct. Numbers are around
5 intel_dport
36 dport
479 intel_dig_port
352 dig_port
Since we already removed the intel_ prefix from most of our other
structs, do the same here and
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/tgl: Implement WA 18011464164
URL : https://patchwork.freedesktop.org/series/78965/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8680 -> Patchwork_18051
== Series Details ==
Series: drm/i915/dp: Correctly advertise HBR3 for GEN11+ (rev2)
URL : https://patchwork.freedesktop.org/series/61546/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8679 -> Patchwork_18050
Summary
== Series Details ==
Series: drm/i915: Futher hotplug cleanups
URL : https://patchwork.freedesktop.org/series/78962/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8679 -> Patchwork_18049
Summary
---
**SUCCESS**
== Series Details ==
Series: Add support for Keem Bay DRM driver
URL : https://patchwork.freedesktop.org/series/78961/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8679 -> Patchwork_18048
Summary
---
**SUCCESS**
On Tue, 2020-06-30 at 17:28 +0300, Ville Syrjälä wrote:
> On Mon, Jun 29, 2020 at 02:20:58PM -0700, José Roberto de Souza wrote:
> > This fix some possible corruptions.
> >
> > BSpec: 52755
> > BSpec: 52890
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 3
Fix another set of corruption issues.
BSpec: 52758
BSpec: 52890
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 5 insertions(+)
diff --git
This fix some possible corruptions.
v2:
Renamed SLICE_UNIT_LEVEL_CLOCK_GATING_CTL to
SLICE_UNIT_LEVEL_CLKGATE_CTL_94D8
BSpec: 52755
BSpec: 52890
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
2
On Wed, 2020-07-01 at 00:00 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/5] drm/i915: Add plane damage clips
> property (rev2)
> URL : https://patchwork.freedesktop.org/series/78830/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from
On Wed, 2020-05-27 at 16:03 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Drop some pointless curly braces, and add some across the
> else when the if has them too.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 9 -
== Series Details ==
Series: series starting with [v2,1/5] drm/i915: Add plane damage clips property
(rev2)
URL : https://patchwork.freedesktop.org/series/78830/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8678_full -> Patchwork_18047_full
On Wed, 2020-05-27 at 16:03 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Apparently there are EDIDs in the wild with multiple DispID extension
> blocks. Iterate through them all.
>
> In one particular case the tile information is specicied in the
> second DispID ext block, and since
On Wed, 2020-05-27 at 16:03 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Apparently EDIDs with multiple DispID ext blocks is a thing, so prepare
> for iterating through multiple ext blocks of the same type by
> passing the starting ext block index to drm_find_edid_extension(). Well
>
intel_dp_set_source_rates() calls intel_dp_is_edp(), which is unsafe to
use before encoder_type is set. This caused GEN11+ to incorrectly strip
HBR3 from source rates for edp. Move intel_dp_set_source_rates() to
after encoder_type is set. Add comment to intel_dp_is_edp() describing
unsafe usages.
On Sat, 27 Jun 2020 at 03:17, Daniele Ceraolo Spurio
wrote:
>
>
>
> On 6/26/20 12:14 AM, Lucas De Marchi wrote:
> > Cc Matt and Daniele
> >
> > On Thu, Jun 25, 2020 at 9:38 PM Dave Airlie wrote:
> >>
> >> I can't figure this out easily so I'd thought I'd just ask, but does
> >> DG1 have VRAM >
== Series Details ==
Series: drm/i915: Skip stale object handle for debugfs per-file-stats
URL : https://patchwork.freedesktop.org/series/78948/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8678_full -> Patchwork_18046_full
On Wed, Jul 01, 2020 at 12:20:26AM +0300, Ville Syrjälä wrote:
> On Fri, Jun 26, 2020 at 04:26:41PM -0700, Manasi Navare wrote:
> > Based on the platform, Bspec expects us to wait or poll with
> > timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active
> > after enabling DDI_BUF_CTL.
== Series Details ==
Series: drm/i915/gem: Always do pin_user_pages under the mmu-notifier (rev2)
URL : https://patchwork.freedesktop.org/series/78941/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8678_full -> Patchwork_18045_full
== Series Details ==
Series: drm/i915: Futher hotplug cleanups
URL : https://patchwork.freedesktop.org/series/78962/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: Add support for Keem Bay DRM driver
URL : https://patchwork.freedesktop.org/series/78961/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c489c4330583 drm/kmb: Add support for KeemBay Display
-:39: WARNING:FILE_PATH_CHANGES: added, moved or deleted
From: Ville Syrjälä
Make a clean split between hpd pins for DDI vs. TC. This matches
how the actual hardware is split.
And with this we move the DDI/PHY->HPD pin mapping into the encoder
init instead of having to remap yet again in the interrupt code.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
No point in assigning the function return value to a local
variable if we're just going to use it the one time.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Introduce intel_hpd_hotplug_irqs() as a partner to
intel_hpd_enabled_irqs(). There's no need to care about the
encoders which we're not exposing, so we can avoid hardocoding
the masks in various places.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 50
From: Ville Syrjälä
No reason to stuff both DDI and TC port handling into the same
function. Split it into two.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 48 ++---
1 file changed, 27 insertions(+), 21 deletions(-)
diff --git
From: Ville Syrjälä
Currently DP/HDMI/DDI encoders init their hpd_pin from the
connector init. Let's move it to the encoder init so that
we don't need to add platform specific junk to the connector
init (which is shared by all g4x+ platforms).
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
We have nice parametrized GEN11_{TC,TBT}_HOTPLUG() so nuke
the overlapping defines.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 20 +-
drivers/gpu/drm/i915/i915_reg.h | 36 +++--
2 files changed, 22
From: Ville Syrjälä
gen11_hpd_detection_setup() is missing ports TC5/6. Add them.
TODO: Might be nice to only enable the hpd detection logic
for ports we actually have. Should be rolled out for all
platforms if/when done...
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 8
From: Ville Syrjälä
AUX CH H/I need their power domains too.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
We need to go up to AUX_CH_I (aka. AUX CH USBC6) these days.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
From: Ville Syrjälä
As with everything else VBT can now specify AUX CH H or I.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 6 ++
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 ++
2 files changed, 8 insertions(+)
diff --git
From: Ville Syrjälä
We need to go up to PORT_I (aka. TC6) these days.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
VBT has ports H and I since version 217.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 ++
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8 ++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Our hotplug interrupt handling is still a mess.
Continue the cleanup.
Ville Syrjälä (12):
drm/i915: Add more AUX CHs to the enum
drm/i915: Add PORT_{H,I} to intel_port_to_power_domain()
drm/i915: Add AUX_CH_{H,I} power domain handling
drm/i915: Add VBT DVO ports H
From: Edmund Dea
Video artifacts appear during playback as horizontal lines that
sporadically appear every few frames. Issue was caused by writing to
LCD_LAYERn_CFG register twice during plane updates. Issue is fixed by
writing to LCD_LAYERn_CFG only once.
Removed plane_init_status so that
From: Edmund Dea
Note that we enable clk_msscam but do not set clk_msscam. However, we do
enable and set clk_mipi_ecfg and clk_mipi_cfg.
Verify that LCD and MIPI clocks are set successfully.
Signed-off-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_drv.c | 112
Enable clocks for LCD, mipi common and mipi tx0
Renamed MSS_CAM_CLK_CTRL and also fixed bug in the
call to set this register.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 8
drivers/gpu/drm/kmb/kmb_drv.h | 14 ++
drivers/gpu/drm/kmb/kmb_dsi.c |
Print messages for LCD DMA FIFO errors.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 68 +++--
drivers/gpu/drm/kmb/kmb_plane.h | 2 ++
2 files changed, 60 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c
cleanup code
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 5 +++--
drivers/gpu/drm/kmb/kmb_drv.h | 1 -
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index b0ab40b..1f0dcbe 100644
---
Set the DMA Vstride and Line width for U and V planes to the same as the
Y plane and not the actual pitch.
Bit18 of layer config does not have any effect when U and V planes are
swapped, so swap it in the driver.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Edmund Dea
---
Register DSI host first and then defer probe until ADV bridge is
initialized.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 144 ++
drivers/gpu/drm/kmb/kmb_dsi.c | 46 --
drivers/gpu/drm/kmb/kmb_dsi.h | 3 +-
3 files
KMB display pipeline is LCD->Mipi->HDMI. Mipi->HDMI converter chip only
accepts 4-lane input from mipi.
With 4-lane mipi, KMB hardware can only support 1080p resolution.
Therefore, limit supported mode to 1080p.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
general cleaning
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 977fcb8..8a12d6d 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++
Find ADV 7535 from the device tree and get the bridge driver and attach
it to the DRM and the MIPI encoder.
v2: check for valid encoder node
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 27 ++-
From: Edmund Dea
to remove compiler warnings and general clean up
Signed-off-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_crtc.c | 48 +-
drivers/gpu/drm/kmb/kmb_crtc.h |6 +-
drivers/gpu/drm/kmb/kmb_drv.c | 115 +++--
drivers/gpu/drm/kmb/kmb_drv.h | 107 ++--
The issue was that spurious interrupts were happening before the LCD
controller was enabled and system hangs. Fix is to
clear LCD interrupts and disable them before modeset
and re enable them after enabling LCD controller.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
Mipi input expects the memory layout to be unpacked with 8 bits per
pixel in RGB (BRG) order. If the LCD is not configured properly,
corrupted output results, changed dma_unpacked to 0 in mipi FG.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c |
Disable ping pong mode otherwise video corruption results,
use continuous mode and also fetch the dma
addresses before disabling dma. For now, only initialize the dma and
planes once and for next plane updates only update the addresses for
dma.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob
setbits instead of write dword for LCD_CONTROL register
this was inadvertantly disabling the LCD controller.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
of probe and return probe_defer early on, so that all the other
initializations can be done after adv driver is loaded successfully.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 81 ++--
drivers/gpu/drm/kmb/kmb_dsi.c | 144
System clock is different for A0 and B0 silicons, so get it directly
from clk_PLL0 through SCMI calls.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 11 +++
drivers/gpu/drm/kmb/kmb_drv.h | 1 +
drivers/gpu/drm/kmb/kmb_dsi.c | 12
Get clock info from DT and enable it during initialization.
Also changed name of the driver to "kmb,display" to match other
entries in the DT.
v2: fixed error in clk_disable
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 42
Also free dsi resources on driver unload. System clock frequency change
for llp ratio calculation.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_crtc.c | 21 ---
drivers/gpu/drm/kmb/kmb_drv.c | 6 +-
drivers/gpu/drm/kmb/kmb_drv.h | 1 +
Set swap bit for the colors to display correctly
when the format is RGB and not set when its BGR.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff
Initial issue was that display remains shifted after undeflow, this fix is
to recover the dma after underflow so display is clean. Major changes are
reduce LCD_CLK to 200Mhz and some changes in the lcd timing params
run recovery sequence at the EOF after underflow happens
do nothing in
Removed hardcoded timings, set timings based on the current mode's
input timings. Also calculate and set the lane rate based on the
timings.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_crtc.c | 9 +++-
drivers/gpu/drm/kmb/kmb_dsi.c | 93
name change
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/Makefile | 4 ++--
drivers/gpu/drm/kmb/kmb_drv.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/kmb/Makefile b/drivers/gpu/drm/kmb/Makefile
index
name change
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 1f0dcbe..b1cc8ad 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++
When disabling/enabling LCD layers, the change takes effect
immediately and does not wait for EOF (end of frame). If we
disable an LCD layer in kmb_plane_atomic_disable, then the frame
reappears with incorrect display offsets.
The solution is to mark the plane as disabled when
From: Edmund Dea
Made it conditionally compiled.
Signed-off-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_drv.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 4eb472b..1aedcf8 100644
---
The issue was video starts fine, but towards the end, the color disappers.
Do the layer initializations only once, but update the DMA registers
for every frame. Also changed DRM_INFO to DRM_DEBUG.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c |
Also added debug messages
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 19 +--
drivers/gpu/drm/kmb/kmb_regs.h | 6 +++---
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
Enabled vblank interrupts for LCD.
Signed-off-by: Anitha Chrisanithus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 35 +++
drivers/gpu/drm/kmb/kmb_drv.c | 41 +
drivers/gpu/drm/kmb/kmb_plane.c | 6
Also moved num_planes init before load, time out for dsi
fixed kmb regs read/write to only pass dev_p and few other minor
changes.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 32 ++--
drivers/gpu/drm/kmb/kmb_drv.h | 34
From: Edmund Dea
- Removed deprecated code blocks within probe functions
- In kmb_remove, unregister MIPI DSI host
- In kmb_probe, if kmb_load fails, then unregister MIPI DSI host
- Change kmb_dsi_host_bridge_init to return error codes using ERR_PTR
- Do clock intitialization earlier
- Rename
From: Edmund Dea
Added test pattern generator function. Enable this at compile time to
test if mipi is working. mipi->hdmi section
Signed-off-by: Edmund Dea
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 31 +++
drivers/gpu/drm/kmb/kmb_dsi.h | 7
unmap MSSCAM registers
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 15 +++
drivers/gpu/drm/kmb/kmb_drv.h | 1 -
drivers/gpu/drm/kmb/kmb_regs.h | 2 +-
3 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c
Fix test_mode_send and dphy_wait_fsm for 2-lane MIPI
- Fix test_mode_send when sending normal mode test codes
- Change dphy_wait_fsm to check for IDLE status rather than LOCK
status for 2-lane MIPI
Signed-off-by: Anitha Chrisanthus
Signed-off-by: Edmund Dea
---
To run modetest without ADV driver, enable LCD_TEST and FCC_TEST.
Also made front porches 0, and some changes in the plane init.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_crtc.c | 13 +++
drivers/gpu/drm/kmb/kmb_drv.c | 6 +--
drivers/gpu/drm/kmb/kmb_drv.h | 3 +-
This initializes the interrupts for DSI. This is the final part of mipi
DSI initialization.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 1 +
drivers/gpu/drm/kmb/kmb_drv.h | 30 +++-
drivers/gpu/drm/kmb/kmb_dsi.c | 46
Mipi TX frame section configuration
This is the first part in the MIPI controller initialization.
Compute and set the right values in MIPI TX frame section configuration
registers like packet header(PH), unpacked bytes and line config.
v2: added more comments to clarify assumptions
v3: improved
This initializes the multichannel fifo in the mipi transmitter and
sets the LCD to mipi interconnect which connects LCD to MIPI ctrl #6
v2: code review changes to make code simpler
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.h | 25
Register physical addresses are remapped and the register mmio
addresses for lcd,mipi and msscam are saved in drm_private.
All register reads/writes are updated to get the mmio offset
from this structure. We are using hardcoded values for register
physical addresses and this will be modified to
Mipi HS registers start at an additional offset of 0x400 which needs to be
added at the register macro definition and not at the read/write function
level.
v2: replaced calculations with macro to make code simpler
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
Mipi TX Frame generator timing configuration
Compute and set frame generator timings like hactive, front porch,
back porch etc.
v2: minor code review changes
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 132
v2: code review changes
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 14 +-
drivers/gpu/drm/kmb/kmb_regs.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c
Basic frame work for mipi encoder and connector.
More hardware specific details will be added in the future commits.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/Makefile | 2 +-
drivers/gpu/drm/kmb/kmb_drv.c | 2 +
drivers/gpu/drm/kmb/kmb_dsi.c | 114
These changes are ported from Myriadx which has additional registers
updated for planes. This change does the following
reinitialize plane interrupts
program Cb/Cr for planar formats
set LCD_CTRL_VHSYNC_IDLE_LVL
set output format and configure csc
v2: code review changes
Signed-off-by: Anitha
Added mipi DSI host initialization functions
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 59 +++
drivers/gpu/drm/kmb/kmb_dsi.h | 4 +++
2 files changed, 63 insertions(+)
diff --git
Myriadx code has it set to these values.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index
This initializes the mipi high speed transmitter CTRL and SYNC
configuration registers.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 55 --
drivers/gpu/drm/kmb/kmb_regs.h | 29 +-
2
This code is commented out until firmware is updated to
redirect LCD IRQ from MSSCPU to A53.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git
This completes the DPHY initialization and Tx initialization.
v2: minor code review changes
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 65 ++
drivers/gpu/drm/kmb/kmb_dsi.h | 18
Also added separate macros for lcd and mipi register accesses that
use the corrected mmio offset. mmio oofset will be read from the device
tree in the future.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 49
From: Edmund Dea
revert dsi_host to static and instead add dsi_host_unregister.
Signed-off-by: Edmund Dea
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 6 +++---
drivers/gpu/drm/kmb/kmb_drv.h | 1 -
drivers/gpu/drm/kmb/kmb_dsi.c | 9 +++--
drivers/gpu/drm/kmb/kmb_dsi.h | 1
Added handlers for lcd and mipi, it only finds and clears the interrupt
as of now, more functionality can be added as needed.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 51 --
This is a new DRM driver for Intel's KeemBay SOC.
The SoC couples an ARM Cortex A53 CPU with an Intel
Movidius VPU.
This driver is tested with the KMB EVM board which is the refernce baord
for Keem Bay SOC. The SOC's display pipeline is as follows
+--++-+
Initial check-in for basic display driver for KeemBay family of SOCs.
This is not tested and does not work and also there are many TBDs in the
code which will be implemented in future commits.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/Kconfig | 2 +
This is part1 of DPHY initialization.
v2: remove kmb_write() as the function provides no benefit over
calling writel() directly.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.h | 5 -
drivers/gpu/drm/kmb/kmb_dsi.c | 346
Check if format is supported and size is within limits.
v2: simplified the code as per code review
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 111 +++-
1 file changed, 65 insertions(+), 46 deletions(-)
This is part2 of DPHY initialization- sets up DPHY PLLs.
v2: simplified mipi_tx_get_vco_params() based on review
v3: added WARN_ON for invalid freq
v4: fixed bug in mipi_tx_get_vco_params
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 194
This is to keep track of the id of the plane as there are 4 planes in
Kmb and when update() is called, we need to know which plane need to be
updated so that the corresponding plane's registers can be programmed.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
Did some general clean up and organization.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 3 +-
drivers/gpu/drm/kmb/kmb_regs.h | 852 +++--
2 files changed, 307 insertions(+), 548 deletions(-)
diff --git
During update plane, set the layer format, bpp, fifo level,
RGB order, Cb/Cr order etc. in the LAYER_CFG register.
v2: Return val in set_pixel and set_bpp instead of passing in pointer,
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 145
Keep the old handles in a small ring so that we build up a small amount
of pressure for i915_gem_close_object() and throw in a few concurrent
contexts so we have to process an obj->lut_list containing more than one
element. And to make sure the list is truly long enough to schedule,
start leaking
On Tue, Jun 30, 2020 at 02:10:45PM -0700, Manasi Navare wrote:
> On Wed, Jul 01, 2020 at 12:03:30AM +0300, Ville Syrjälä wrote:
> > On Fri, Jun 26, 2020 at 04:26:40PM -0700, Manasi Navare wrote:
> > > Modify the helper to add a fixed delay or poll with timeout
> > > based on platform specification
On Fri, Jun 26, 2020 at 04:26:41PM -0700, Manasi Navare wrote:
> Based on the platform, Bspec expects us to wait or poll with
> timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active
> after enabling DDI_BUF_CTL.
>
> v4:
> * Use the timeout for GLK (Ville)
> v3:
> * Add a new
== Series Details ==
Series: drm/i915: Clamp min_cdclk to max_cdclk_freq to unblock 8K
URL : https://patchwork.freedesktop.org/series/78940/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8678_full -> Patchwork_18044_full
On Wed, Jul 01, 2020 at 12:03:30AM +0300, Ville Syrjälä wrote:
> On Fri, Jun 26, 2020 at 04:26:40PM -0700, Manasi Navare wrote:
> > Modify the helper to add a fixed delay or poll with timeout
> > based on platform specification to check for either Idle bit
> > set (DDI_BUF_CTL is idle for disable
On Fri, Jun 26, 2020 at 04:26:40PM -0700, Manasi Navare wrote:
> Modify the helper to add a fixed delay or poll with timeout
> based on platform specification to check for either Idle bit
> set (DDI_BUF_CTL is idle for disable case)
>
> v3:
> * Change the timeout to 16usecs (Ville)
> v2:
> * Use
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