[Intel-gfx] ✓ Fi.CI.BAT: success for enhanced i915 vgpu with PV feature support

2020-09-06 Thread Patchwork
== Series Details == Series: enhanced i915 vgpu with PV feature support URL : https://patchwork.freedesktop.org/series/81400/ State : success == Summary == CI Bug Log - changes from CI_DRM_8968 -> Patchwork_18446 Summary ---

[Intel-gfx] ✗ Fi.CI.DOCS: warning for enhanced i915 vgpu with PV feature support

2020-09-06 Thread Patchwork
== Series Details == Series: enhanced i915 vgpu with PV feature support URL : https://patchwork.freedesktop.org/series/81400/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_vgpu.c:846: warning: Excess function parameter 'dev_priv'

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for enhanced i915 vgpu with PV feature support

2020-09-06 Thread Patchwork
== Series Details == Series: enhanced i915 vgpu with PV feature support URL : https://patchwork.freedesktop.org/series/81400/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for enhanced i915 vgpu with PV feature support

2020-09-06 Thread Patchwork
== Series Details == Series: enhanced i915 vgpu with PV feature support URL : https://patchwork.freedesktop.org/series/81400/ State : warning == Summary == $ dim checkpatch origin/drm-tip b72c9e3578ae drm/i915: introduced vgpu pv capability -:98: CHECK:PARENTHESIS_ALIGNMENT: Alignment should

[Intel-gfx] [PATCH v1 12/12] drm/i915/gvt: GVTg support pv workload submssion

2020-09-06 Thread Xiaolin Zhang
implemented pv workload submission support within GVTg. GVTg to read engine submission data (engine lrc) from the shared_page with pv interface to reduce mmio trap cost and then eliminate execlist HW behavior emulation by removing injecting context switch interrupt to guest under workload

[Intel-gfx] [PATCH v1 03/12] drm/i915: vgpu pv command buffer transport protocol

2020-09-06 Thread Xiaolin Zhang
based on the common shared memory, vgpu pv command transport buffer (CTB) protocol is implemented which is a simple pv command buffer ring with pv command descriptor used to perform guest-2-gvt single direction commucation between guest and host GVTg. with this CTB, guest can send PV command with

[Intel-gfx] [PATCH v1 05/12] drm/i915: vgpu ggtt page table pv support

2020-09-06 Thread Xiaolin Zhang
to improve efficiency and reduce the complexsity of vgpu ggtt support, vgpu ggtt page table operations are implemented in pv fashion and implemented pv version of bind/unbind for ggtt vma ops. The pv version of ggtt vma ops use the CTB protocol to communicate pv ggtt command along with data

[Intel-gfx] [PATCH v1 04/12] drm/i915: vgpu ppgtt page table pv support

2020-09-06 Thread Xiaolin Zhang
to improve efficiency and reduce the complexsity of vgpu ppgtt support, vgpu ppgtt page table operations are implemented in pv fashion and implemented pv version of bind/unbind for ppgtt vma ops. The pv version of ppgtt vma ops use the CTB protocol to communicate pv ppgtt command along with data

[Intel-gfx] [PATCH v1 11/12] drm/i915/gvt: GVTg support ggtt pv operations

2020-09-06 Thread Xiaolin Zhang
This patch is to handle ppgtt PV_CMD_BIND_GGTT and PV_CMD_UNBIND_GGTT for pv ggtt, it is operated (bind/unbind) per vma instead of per ggtt entry mmio update to improve efficiency Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/gtt.c | 83 +

[Intel-gfx] [PATCH v1 02/12] drm/i915: vgpu shared memory setup for pv support

2020-09-06 Thread Xiaolin Zhang
To support vgpu pv features, a common shared memory is setup used for communication and data exchange between guest and host GVTg to reduce data access overhead and trap cost. guest i915 will allocate this common memory (1 page size) and then pass it's physical address to host GVTg through PVINFO

[Intel-gfx] [PATCH v1 01/12] drm/i915: introduced vgpu pv capability

2020-09-06 Thread Xiaolin Zhang
to enable vgpu pv feature, pv capability is introduced for guest by new pv_caps member in struct i915_virtual_gpu and for host GVT by new pv_caps register in struct vgt_if. both of them are used to control different pv feature support in each domain and the final pv caps runtime negotiated

[Intel-gfx] [PATCH v1 09/12] drm/i915/gvt: GVTg support vgpu pv CTB protocol

2020-09-06 Thread Xiaolin Zhang
host side to implement vgpu PV CTB protocol. based on the protocol, CTB read functionality is implemented to handle pv command from guest. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/handlers.c | 119 +++- 1 file changed, 118 insertions(+), 1

[Intel-gfx] [PATCH v1 08/12] drm/i915/gvt: GVTg handle guest shared_page setup

2020-09-06 Thread Xiaolin Zhang
GVTg implemented guest shared_page register operation and read and write shared_page functionality based on hypervisor read and write functionality. the shared_page_gpa was passed from guest driver through PVINFO shared_page_gpa register. Signed-off-by: Xiaolin Zhang ---

[Intel-gfx] [PATCH v1 10/12] drm/i915/gvt: GVTg support ppgtt pv operations

2020-09-06 Thread Xiaolin Zhang
This patch is to handle ppgtt PV_CMD_BIND_PPGTT and PV_CMD_UNBIND_PPGTT for ppgtt, it creates local ppgtt tables and set up the PTE's directly from the PV command data from guest, which does not track the usage of guest page table and remove the cost of write protection from the original PPGTT

[Intel-gfx] [PATCH v1 06/12] drm/i915: vgpu workload submisison pv support

2020-09-06 Thread Xiaolin Zhang
to improve efficiency and reduce the complexity of vgpu workload submission support, a pv version of workload submission backend implemented with engine submission data in the shared memory and eliminating execlists csb process and context switch interrupt in submisision routine. new

[Intel-gfx] [PATCH v1 07/12] drm/i915/gvt: GVTg expose pv_caps PVINFO register

2020-09-06 Thread Xiaolin Zhang
expose pv_caps PVINFO register from GVTg to guest in order that guest can query and control different pv capability support. report VGT_CAPS_PV capability in pvinfo page for guest. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/gvt.h | 8

[Intel-gfx] [PATCH v1 00/12] enhanced i915 vgpu with PV feature support

2020-09-06 Thread Xiaolin Zhang
This is new i915 VGPU PV design based on the last year proposal [1]. This is a new series of patch set and discontiued the old series of patch set due to this new design. To improve vgpu performance, it could implement some PV optimizations in different gpu resource domain to reduce the data

[Intel-gfx] Pushed atomic-pwm changes, had to manually resolve a conflict in drm-tip

2020-09-06 Thread Hans de Goede
Hi All, Note this is just FYI, in case I did anything wrong... Now that it is finally fully acked up and has passed CI I have pushed my atomic-pwm support for i915 series to dinq. This let to a conflict in drm-tip. The problem was that in dinq prior to my push intel_panel.c had the following