Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/drm_gem.c
between commit:
f49a51bfdc8e ("drm/shme-helpers: Fix dma_buf_mmap forwarding bug")
from the drm-misc-fixes tree and commit:
d693def4fd1c ("drm: Remove obsolete GEM and PRIME callbacks from
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL : https://patchwork.freedesktop.org/series/82411/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9214_full -> Patchwork_18801_full
==
On Wed, 2020-10-28 at 05:54 +, Patchwork wrote:
Patch Details
Series: series starting with [v2,1/6] drm/i915/display/psr: Calculate selective
fetch plane registers
URL:https://patchwork.freedesktop.org/series/83119/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/
== Series Details ==
Series: drm/i915: Force initial atomic check in all eDP panels
URL : https://patchwork.freedesktop.org/series/83170/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9214_full -> Patchwork_18800_full
Summa
I don’t see how these failures are related to the patch series
Manasi
From: Patchwork
Sent: Wednesday, October 28, 2020 4:31 PM
To: Navare, Manasi D
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for series starting with [v3,1/6] drm/i915/dp:
Some reshuffling in mode_valid a
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/dp: Some reshuffling in
mode_valid as prep for bigjoiner modes
URL : https://patchwork.freedesktop.org/series/83173/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9214 -> Patchwork_18802
=
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/dp: Some reshuffling in
mode_valid as prep for bigjoiner modes
URL : https://patchwork.freedesktop.org/series/83173/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
29b307e050f4 drm/i915/dp: Some reshuffling in
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL : https://patchwork.freedesktop.org/series/82411/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9214 -> Patchwork_18801
Su
On Wed, Oct 28, 2020 at 11:33:23PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
ibx_irq_pre_postinstall() looks totally pointless. We can just
init both SDEIMR and SDEIER at the same time before enabling the
master intererupt. It's equally racy as the other order due
master interrupt
to
On Wed, Oct 28, 2020 at 11:33:21PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
Let's enable the hardware hpd logic only for the ports we
can actually use.
In theory this may save some miniscule amounts of power,
and more importantly it eliminates a lot if platform specific
codepaths since
On Wed, Oct 28, 2020 at 03:04:37PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 28, 2020 at 01:26:27PM +0100, Maarten Lankhorst wrote:
> > Op 27-10-2020 om 20:11 schreef Ville Syrjälä:
> > > On Tue, Oct 27, 2020 at 11:19:16AM -0700, Navare, Manasi wrote:
> > >> On Tue, Oct 27, 2020 at 03:42:30PM +0200
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL : https://patchwork.freedesktop.org/series/82411/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL : https://patchwork.freedesktop.org/series/82411/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ee08af3a4155 drm/i915: s/PORT_TC/TC_PORT_/
-:313: CHECK:MACRO_ARG_REUSE: Macro ar
== Series Details ==
Series: drm/i915: Force initial atomic check in all eDP panels
URL : https://patchwork.freedesktop.org/series/83170/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9214 -> Patchwork_18800
Summary
---
On Wed, Oct 28, 2020 at 11:33:18PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
No reason that I can see why we should enable the hpd detection logic
already during irq postinstall phase. We don't even do this on all
the platforms. We just need it before we actually enable the hotplug
interr
Quoting Stephen Rothwell (2020-10-28 21:28:23)
> Hi all,
>
> Commit
>
> d13208a88f41 ("lockdep: Fix nr_unused_locks")
>
> is missing a Signed-off-by from its author.
>
> Also, the author's email name is missing the leading 'P'.
And it shouldn't be in the drm-intel-fixes tree.
-Chris
No functional changes here. Just pass intel_atomic_state
along with crtc_state to certain atomic_check functions.
This will lay the foundation for adding bigjoiner master/slave
states in atomic check.
v2:
* More prep with intel_atomic_state (Ville)
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
No functional changes. This patch just moves some mode checks
around to prepare for adding bigjoiner related mode validation
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
1 file changed, 6 insertions(+),
From: Maarten Lankhorst
With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v7:
* Remove redundant comment (Ville)
* Just keep mode instead of pipe_mode (Vill
No functional changes, to align with previous cleanups pass
intel_atomic_state instead of drm_atomic_state.
Also pass this intel_atomic_state with crtc_state to
some of the atomic_check functions.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make intel_dp_can
This adds new pipe_mode readout in verify_crtc_state()
Here it is just adjusted_mode without bigjoiner.
Bigjoiner pipe_mode readout will be added later.
While at it, create a separate intel_encoder_get_config()
function that calls encoder->get_config hook.
This is needed so that later we can add b
From: Ville Syrjälä
Move intel_hpd_{enabled,hotplug}_irqs() closes to the beginning of
the file so we can use them in more places. No functional changes.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 50 -
1 fil
From: Ville Syrjälä
Parametrize the icp+ TC HPD bits using hpd_pin rather than
tc_port so it's clear what kind of an animal we're dealing
with.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 30 -
drivers/gpu/drm/i915/i9
From: Ville Syrjälä
Since tgl the DDIs have been named A,B,C,TC1,TC2,TC3...
Add the appropriate enum values for the TC DDIs to enum port.
v2: Deal with rkl and dg1
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c| 10 +++
drivers
From: Ville Syrjälä
Replace this silly tmp_mask with hotplug_trigger/te_trigger
where appropriate.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers
From: Ville Syrjälä
As with the VBT DVO port, RKL uses PHY based mapping for the
VBT AUX CH. Adjust the code to use the new AUX_USBCn names
and add a comment to explain the situation.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +
From: Ville Syrjälä
No reason not to use GEN3_IRQ_INIT() on icp+.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i9
From: Ville Syrjälä
No reason to stuff both type-c and tbt into the same function.
Let's split this so we may more easily handle platforms that
lack the tbt spefific bits.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 13 ++---
1 file
From: Ville Syrjälä
Let's make the AUX CH names match the spec (AUX A-F for pre-tgl,
AUX A-C or AUX USBC1-6 for tgl+). And while at it let's include
the full encoder name in the AUX CH name as well (as opposed to
just using port_name() which wouldn't give us the right thing on
tgl+).
Reviewed-by
From: Ville Syrjälä
We no longer unmask all HPD irqs, so we can drop the ugly per-platform
HPD IIR masking. IMR will prevent unsupported bits from appearing in
IIR.
v2: Deal with DG1
Include "HOTPLUG" in the mask names (Lucas)
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear
these have nothing to do with DDI ports or PHYs as such. The only
thing that matters is the HPD pin assignment.
v2: Remember the gvt
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/
From: Ville Syrjälä
ibx_irq_pre_postinstall() looks totally pointless. We can just
init both SDEIMR and SDEIER at the same time before enabling the
master intererupt. It's equally racy as the other order due
to doing all of this from the postinstall stage with the interrupt
handler already in pla
From: Ville Syrjälä
Use hpd_pin instead of port in the parametrized ICP+ DDI HPD
macros. Makes it clear what these refer to.
v2: Handle DG1
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 22 +++
drivers/gpu/drm/i915/i915_reg.h | 50
From: Ville Syrjälä
Use hpd_pin instead of tc_port in the GEN11_{TC,TBT}_HOTPLUG()
to make it clear what they refer to.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 48 -
drivers/gpu/drm/i915/i915_reg.h | 37 ++
From: Ville Syrjälä
Let's enable the hardware hpd logic only for the ports we
can actually use.
In theory this may save some miniscule amounts of power,
and more importantly it eliminates a lot if platform specific
codepaths since the generic thing can now deal with any
combination of ports bein
From: Ville Syrjälä
No reason that I can see why we should enable the hpd detection logic
already during irq postinstall phase. We don't even do this on all
the platforms. We just need it before we actually enable the hotplug
interrupts in .hpd_irq_setup(), and in fact we already do it there as
w
From: Ville Syrjälä
Make the namespacing for enum tc_port better by adding
the TC_ to the actual enum values.
v2: Drop the extra TC (Lucas)
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_d
From: Ville Syrjälä
Just like with the DDIs tgl+ renamed the AUX CHs to reflect
the type of the DDI. Let's add the aliasing enum values for
the type-C AUX CHs.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.h | 8 +++
drivers/gpu/drm/
From: Ville Syrjälä
Rebase of the remaining hpd cleanup series. Almost started
merging from the start but then realized some dg1 stuff landed
which needed some tweaking. So figured best repost the whole thing
one more time.
Only a few patches missing and r-b I think.
Main changes since last tim
From: Ville Syrjälä
Let's pimp the DDI encoder->name to reflect what the spec calls them.
Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6.
Also since each encoder is really a combination of the DDI and the PHY
we include the PHY name as well.
ICL is a bit special since it already has the t
From: Ville Syrjälä
Unify the BDW/BXT hotplug bits. BDW only has port A, but that
matches BXT port A so we can shar the same macro for both.
v2: Remember the gvt
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gvt/display.c | 14 +++---
drivers/gpu/
Hi all,
Commit
d13208a88f41 ("lockdep: Fix nr_unused_locks")
is missing a Signed-off-by from its author.
Also, the author's email name is missing the leading 'P'.
--
Cheers,
Stephen Rothwell
pgp0c7gXTexDy.pgp
Description: OpenPGP digital signature
_
After commit 00e5deb5c4f5 ("drm/i915: Fix encoder lookup during PSR
atomic check") dig_port was not being used but while fixing it I
realized that would be better to mark all CRTCs that has a eDP
connector as needing to have their state computed.
The principal reason is that in future we will suppo
On Tue, Oct 27, 2020 at 10:02:45AM -0400, Jason Andryuk wrote:
> On Tue, Oct 27, 2020 at 9:36 AM Imre Deak wrote:
> >
> > Make sure to propagate the error result from the DPRX link training
> > phase. The lack of this broke the link training fall-back logic if the
> > link training failed during t
On Wed, Oct 28, 2020 at 04:15:26PM -0300, Jason Gunthorpe wrote:
> Since commit 9a40401cfa13 ("lib/scatterlist: Do not limit max_segment to
> PAGE_ALIGNED values") the max_segment input to sg_alloc_table_from_pages()
> does not have to be any special value. The new algorithm will always
> create so
On Wed, Oct 28, 2020 at 02:46:41PM +0530, Tejas Upadhyay wrote:
> As per W/A implemented for TGL to program half of the nominal
> DCO divider fraction value which is also applicable on EHL.
>
> Cc: Deak Imre
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c |
On Wed, Oct 28, 2020 at 05:50:13AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Fix encoder lookup during PSR atomic check
> URL : https://patchwork.freedesktop.org/series/83102/
> State : success
Thanks for the review, pushed to -dinq.
>
> == Summary ==
>
> CI Bug Lo
== Series Details ==
Series: drm/i915/jsl: Disable cursor clock gating in HDR mode
URL : https://patchwork.freedesktop.org/series/83142/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9209_full -> Patchwork_18797_full
Summar
== Series Details ==
Series: drm/i915/guc: Update to GuC v49
URL : https://patchwork.freedesktop.org/series/83157/
State : failure
== Summary ==
Applying: drm/i915/guc: Update to use firmware v49.0.1
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/gt/intel_engine_cs
== Series Details ==
Series: drm/i915/rkl: new rkl ddc map for different PCH
URL : https://patchwork.freedesktop.org/series/83154/
State : failure
== Summary ==
Applying: drm/i915/rkl: new rkl ddc map for different PCH
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915
From: John Harrison
The latest GuC firmware includes a number of interface changes that
require driver updates to match.
* Starting from Gen11, the ID to be provided to GuC needs to contain
the engine class in bits [0..2] and the instance in bits [3..6].
NOTE: this patch breaks pointer dere
From: John Harrison
Rather than just saying 'GuC failed to load: -110', actually print out
the GuC status register and break it down into the individual fields.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 31
From: John Harrison
Clear out some pointers when objects have been de-allocated. This
makes it much easier to track down use-after-free type issues.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
drivers/gpu/drm/i915/gt/u
From: John Harrison
Update to the latest GuC firmware
v2: Rebase to newer tree, updated a commit message (review feedback
from Daniele) and dropped the patch to enable GuC/HuC loading by
default as apparently this is not allowed.
v3: Rebase to drm-intel-gt-next which is apparently missing the
p
After boot into kernel. Driver configured ddc pin mapping based on
predefined table in parse_ddi_port(). Now driver configure rkl
ddc pin mapping depends on icp_ddc_pin_map[]. Then this table will
give incorrect gmbus port number to cause HDMI can't work.
Refer to commit d0a89527d06 ("drm/i915/rkl
On Fri, Oct 23, 2020 at 02:21:21PM +0200, Daniel Vetter wrote:
> Again needs to be put right after the call to
> drm_atomic_helper_commit_hw_done(), since that's the last thing which
> can hold up a subsequent atomic commit.
>
> No surprises here.
>
> Signed-off-by: Daniel Vetter
> Cc: "James (Q
On Wed, Oct 28, 2020 at 01:26:27PM +0100, Maarten Lankhorst wrote:
> Op 27-10-2020 om 20:11 schreef Ville Syrjälä:
> > On Tue, Oct 27, 2020 at 11:19:16AM -0700, Navare, Manasi wrote:
> >> On Tue, Oct 27, 2020 at 03:42:30PM +0200, Ville Syrjälä wrote:
> >>> On Mon, Oct 26, 2020 at 03:41:48PM -0700,
== Series Details ==
Series: drm/i915/ehl: Implement W/A 22010492432
URL : https://patchwork.freedesktop.org/series/83135/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9207_full -> Patchwork_18796_full
Summary
---
*
== Series Details ==
Series: drm/i915/jsl: Disable cursor clock gating in HDR mode
URL : https://patchwork.freedesktop.org/series/83142/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9209 -> Patchwork_18797
Summary
---
Op 27-10-2020 om 20:11 schreef Ville Syrjälä:
> On Tue, Oct 27, 2020 at 11:19:16AM -0700, Navare, Manasi wrote:
>> On Tue, Oct 27, 2020 at 03:42:30PM +0200, Ville Syrjälä wrote:
>>> On Mon, Oct 26, 2020 at 03:41:48PM -0700, Navare, Manasi wrote:
On Mon, Oct 26, 2020 at 10:18:54PM +0200, Ville
Quoting Tejas Upadhyay (2020-10-28 11:17:31)
> Display underrun in HDR mode when cursor is enabled.
> RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> As per W/A 1604331009, Disable cursor clock gating in HDR mode.
>
> Bspec : 33451
>
> Cc: Souza Jose
> Signed-off-by: Tejas Upadhya
Ok, I have initiated the steps to upgrade the CI machine's silicon & BIOS.
Thanks
Hariom Pandey
> -Original Message-
> From: Vivi, Rodrigo
> Sent: Wednesday, October 28, 2020 5:24 PM
> To: Pandey, Hariom ; Szwichtenberg, Radoslaw
>
> Cc: Chris Wilson ; Ausmus, James
> ; Nikula, Jani ; i
> On Oct 27, 2020, at 11:49 PM, Pandey, Hariom wrote:
>
> Hi Chris,
>
> Awaiting your kind response here…
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9208/fi-ehl-1/igt@i915_selftest@live@gt_pm.html
"Did not enter RC6!"
Chris already told that we need to get RC6 working on CI.
If we need
Display underrun in HDR mode when cursor is enabled.
RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
As per W/A 1604331009, Disable cursor clock gating in HDR mode.
Bspec : 33451
Cc: Souza Jose
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +++
On Oct 27, 2020, at 1:46 PM, Rodrigo Vivi
mailto:rodrigo.v...@intel.com>> wrote:
On Tue, Oct 27, 2020 at 11:17:40AM +0800, Zhenyu Wang wrote:
Hi,
Here's first gvt fixes for 5.10 which includes more vGPU
suspend/resume fix in HWSP reset handling, and also fix for host i915
suspend regression w
Is there a list that has the cover letter and the whole series?
I've only found fragments (and mostly the same fragments) while
wading through my backlog in various list folders..
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.fr
== Series Details ==
Series: drm/i915/ehl: Implement W/A 22010492432
URL : https://patchwork.freedesktop.org/series/83135/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9207 -> Patchwork_18796
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/dg1: Fix unbalanced braces
URL : https://patchwork.freedesktop.org/series/83120/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18794_full
Summary
---
**SUC
As per W/A implemented for TGL to program half of the nominal
DCO divider fraction value which is also applicable on EHL.
Cc: Deak Imre
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git
++Tejas
-Original Message-
From: Anshuman Gupta
Sent: 28 October 2020 14:35
To: K, SrinivasX
Cc: intel-gfx@lists.freedesktop.org; seanp...@chromium.org; Pandey, Hariom
Subject: Re: [Intel-gfx] drm/i915: Acquire connector reference before prop_work
On 2020-10-27 at 16:03:35 +0530, Kam
On 2020-10-27 at 16:03:35 +0530, Kamati Srinivas wrote:
> From: Srinivas Kamati
>
> "Content protection type change" igt test results in kernel
> taint. Everytime after prop_work is done we are also
> giving up connector reference, which is resulting in ref
> count underrun.
>
> Before schedulin
On 2020-10-27 at 21:39:28 +0530, Imre Deak wrote:
> The atomic check hooks must look up the encoder to be used with a
> connector from the connector's atomic state, and not assume that it's
> the connector's current attached encoder. The latter one can change
> under the atomic check func, or can b
== Series Details ==
Series: drm/i915: Remainder of dbuf state stuff
URL : https://patchwork.freedesktop.org/series/83114/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18791_full
Summary
---
*
On Wed, Oct 28, 2020 at 03:17:45AM +, Patchwork wrote:
== Series Details ==
Series: series starting with [1/3] drm/i915: Guard debugfs against invalid
access without display
URL : https://patchwork.freedesktop.org/series/83070/
State : failure
== Summary ==
CI Bug Log - changes from CI_
== Series Details ==
Series: drm/i915/gem: Avoid synchronous binds deep within locks
URL : https://patchwork.freedesktop.org/series/83108/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18789_full
Summ
76 matches
Mail list logo
