== Series Details ==
Series: series starting with [1/2] drm/i915/dmabuf: don't trust the
dma_buf->size
URL : https://patchwork.freedesktop.org/series/86191/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670_full -> Patchwork_19465_full
== Series Details ==
Series: drm/i915/dmabuf: don't trust the dma_buf->size
URL : https://patchwork.freedesktop.org/series/86190/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670_full -> Patchwork_19464_full
Summary
== Series Details ==
Series: drm/i915/buddy: document the unused header bits
URL : https://patchwork.freedesktop.org/series/86189/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670_full -> Patchwork_19463_full
Summary
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: SPDX cleanup
URL : https://patchwork.freedesktop.org/series/86185/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670_full -> Patchwork_19461_full
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/gt: Show the per-engine runtime
in sysfs
URL : https://patchwork.freedesktop.org/series/86180/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670_full -> Patchwork_19458_full
== Series Details ==
Series: series starting with [CI,v5,01/18] drm/i915/display/vrr: Create VRR
file and add VRR capability check
URL : https://patchwork.freedesktop.org/series/86200/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9671 -> Patchwork_19471
== Series Details ==
Series: drm/i915/selftests: Check for engine-reset errors in the middle of
workarounds
URL : https://patchwork.freedesktop.org/series/86179/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9670_full -> Patchwork_19457_full
== Series Details ==
Series: series starting with [v1,1/2] drm/gma500: Convert to use new SCU IPC API
URL : https://patchwork.freedesktop.org/series/86178/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670_full -> Patchwork_19456_full
== Series Details ==
Series: series starting with [CI,v5,01/18] drm/i915/display/vrr: Create VRR
file and add VRR capability check
URL : https://patchwork.freedesktop.org/series/86200/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used,
== Series Details ==
Series: series starting with [CI,v5,01/18] drm/i915/display/vrr: Create VRR
file and add VRR capability check
URL : https://patchwork.freedesktop.org/series/86200/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aa71ea851089 drm/i915/display/vrr: Create VRR
== Series Details ==
Series: drm/i915: Start disabling pread/pwrite ioctl's for future platforms
URL : https://patchwork.freedesktop.org/series/86199/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9671 -> Patchwork_19470
== Series Details ==
Series: drm/i915/gt: Move the defer_request waiter active assertion (rev2)
URL : https://patchwork.freedesktop.org/series/86176/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670_full -> Patchwork_19455_full
== Series Details ==
Series: drm/i915: Remainder of dbuf state stuff (rev3)
URL : https://patchwork.freedesktop.org/series/83114/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9671 -> Patchwork_19469
Summary
---
== Series Details ==
Series: drm/i915: Remainder of dbuf state stuff (rev3)
URL : https://patchwork.freedesktop.org/series/83114/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: drm/i915: Remainder of dbuf state stuff (rev3)
URL : https://patchwork.freedesktop.org/series/83114/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f49e0164bdf9 drm/i915: Extract intel_crtc_ddb_weight()
f8f4731253f8 drm/i915: Pass the crtc to
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: stop registering if
drm_dev_register() fails
URL : https://patchwork.freedesktop.org/series/86196/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19468
== Series Details ==
Series: series starting with [CI,01/10] drm/i915/gt: SPDX cleanup
URL : https://patchwork.freedesktop.org/series/86193/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19467
Summary
From: Ville Syrjälä
The vrr calculations will need to know the framestart delay value
we use. Currently we program it always to zero, but should that change
we probably want to stash it somewhere.
Could stick it into the crtc_state I suppose, but since we never
change it let's just stuff it
From: Ville Syrjälä
Dump vrr state alongside everything else.
Signed-off-by: Ville Syrjälä
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
With VRR the earliest the registers can get latched are at
flipline decision boundary, calculate that as vrr_vmin_vblank_start()
and the latest the regsiters can get latched are vmax decision boundary
calculate that as vrr_vmax_vblank_start()
v2:
* Remove TODO and adjust
This patch disables the VRR enable and VRR PUSH
bits in the HW during commit modeset disable sequence.
Thsi disable will happen when the port is disabled
or when the userspace sets VRR prop to false and
requests to disable VRR.
v2:
* Use intel_de_rmw (Jani N)
v3:
* Remove rmw (Ville)
Cc: Ville
This patch computes the VRR parameters from VRR crtc states
and configures them in VRR registers during CRTC enable in
the modeset enable sequence.
v2:
* Remove initialization to 0 (Jani N)
* Use correct pipe %c (Jani N)
v3:
* Remove debug prints (Ville)
* Use cpu_trans instead of pipe for
From: Ville Syrjälä
To get sensible vblank timestamping behaviour we need to feed
the vmax based timings to the vblank code, otherwise it'll chop
off the scanline counter when it exceeds the minumum vtotal.
Additionally with VRR we have three cases to consider when we
generate the vblank
From: Ville Syrjälä
Give the pipeline full line count bits more descriptive names
Signed-off-by: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git
From: Ville Syrjälä
We want to calculate the vblank_start for vblank evasion
differently for vrr. To make that nicer lets first extract
the current non-vrr case to a helper.
Signed-off-by: Ville Syrjälä
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_sprite.c | 14
VRR achieves vblank stretching using the HW PUSH functionality.
So once the VRR is enabled during modeset then for each flip
request from userspace, in the atomic tail pipe_update_end()
we need to set the VRR push bit in HW for it to terminate
the vblank at configured flipline or anytime after
This functions gets the VRR config from the VRR registers
to match the crtc state variables for VRR.
v2:
* Rebase (Manasi)
* Use HAS_VRR (Jani N)
v3:
* Get pipeline_full, flipline (Ville)
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
Even though our HW supports PSR + VRR, the available panels
do not work reliably with PSR and VRR together. So if user
requested VRR and is supported by HW enable that and do not
enable PSR in that case.
Cc: Ville Syrjälä
Cc: Gwan-gyeong Mun
Cc: Imre Deak
Signed-off-by: Manasi Navare
From: Ville Syrjälä
With vrr enabled the hardware no longer latches the registers
automagically at vblank start. The point at which it will do the
latching even when no push has been sent is the vmax decision
boundary. That is the thing we need to evade to avoid our
register latching to get
If VRR is enabled, the sink should ignore MSA parameters
and regenerate incoming video stream without depending
on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
bit if VRR is enabled.
Reset this bit on VRR disable.
v2:
* ACtually set the dpcd msa ignore bit (Ville)
Cc: Ville Syrjälä
We create a new file for all VRR related helpers.
Also add a function to check vrr capability based on
platform support, DPCD bits and EDID monitor range.
v2:
* Remove author (Jani N)
* Define HAS_VRR (Jani N)
* Ensure intel_dp can be obtained from conn (Jani N)
Cc: Ville Syrjälä
Cc: Jani
From: Ville Syrjälä
If VRR is enabled, DRRS cannot be enabled, so make this check
in atomic check.
Signed-off-by: Ville Syrjälä
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Aditya Swarup
This function sets the VRR property for connector based
on the platform support, EDID monitor range and DP sink
DPCD capability of outputing video without msa
timing information.
v8:
* Use HAS_VRR, remove drm_conn declaration (Jani N)
* Fix typos in Comment (Jani N)
v7:
*
From: Ville Syrjälä
Extract intel_crtc_scanlines_since_frame_timestamp() from
__intel_get_crtc_scanline_from_timestamp(). We'll reuse this
for VRR vblank timestamps.
Signed-off-by: Ville Syrjälä
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_irq.c | 38
This forces a complete modeset if vrr drm crtc state goes
from enabled to disabled and vice versa.
This patch also computes vrr state variables from the mode timings
and based on the vrr property set by userspace as well as hardware's
vrr capability.
v2:
*Rebase
v3:
* Vmin = max (vtotal, vmin)
== Series Details ==
Series: series starting with [CI,01/10] drm/i915/gt: SPDX cleanup
URL : https://patchwork.freedesktop.org/series/86193/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: series starting with [1/2] drm/i915/dmabuf: don't trust the
dma_buf->size
URL : https://patchwork.freedesktop.org/series/86192/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19466
The guidance for i915 at this time is to start phasing out pread/pwrite
ioctl's, the rationale being (a) the functionality can be done entirely in
userspace with a combination of mmap + memcpy, and (b) no existing user
mode clients actually use the pread/pwrite interface.
In this patch we disable
The guidance for i915 at this time is to start phasing out pread/pwrite
ioctl's, the rationale being (a) the functionality can be done entirely in
userspace with a combination of mmap + memcpy, and (b) no existing user
mode clients actually use the pread/pwrite interface.
In this patch we disable
We store every client name, pid and runtime under sysfs. Better check
that matches with the actual client.
Signed-off-by: Chris Wilson
---
lib/igt_sysfs.c| 36 +++
lib/igt_sysfs.h| 3 +
tests/Makefile.sources | 3 +
tests/i915/sysfs_clients.c | 450
On 1/20/2021 12:31 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The meaning of 'default' for the enable_guc module parameter has been
updated to accurately reflect what is supported on current platforms.
So start using the defaults instead of forcing everything off.
Worth
We store every client name, pid and runtime under sysfs. Better check
that matches with the actual client.
Signed-off-by: Chris Wilson
---
lib/igt_sysfs.c| 36
lib/igt_sysfs.h| 3 +
tests/Makefile.sources | 3 +
tests/i915/sysfs_clients.c | 361
== Series Details ==
Series: series starting with [1/2] drm/i915/dmabuf: don't trust the
dma_buf->size
URL : https://patchwork.freedesktop.org/series/86191/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19465
From: Ville Syrjälä
In order to make the dbuf state computation less fragile
let's make it stand on its own feet by not requiring someone
to peek into a crystall ball ahead of time to figure out
which pipes need to be added to the state under which potential
future conditions. Instead we compute
From: Ville Syrjälä
Readout the dbuf related stuff during driver init/resume and
stick it into our dbuf state.
v2: Keep crtc_state->wm.skl.ddb
Reviewed-by: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 4 --
From: Ville Syrjälä
Extract the code to calculate the weights used to chunk up the dbuf
between pipes. There's still extra stuff in there that shouldn't be
there and must be moved out, but that requires a bit more state to
be tracked in the dbuf state.
v2: Keep crtc_state->wm.skl.ddb
From: Ville Syrjälä
The dbuf state will be where we collect all the inter-pipe dbuf
allocation stuff. Start by adding the actual per-pipe ddb entries
there.
Originally the plan was to move them there outright, but that no longer
works as we're no longer guaranteed to have a dbuf state when it
From: Ville Syrjälä
Generalize icl_get_first_dbuf_slice_offset() into something that
just gives us the start+end of the dbuf chunk covered by the
specified slices as a standard ddb entry. Initial idea was to use
it during readout as well, but we shall see.
Reviewed-by: Stanislav Lisovskiy
From: Ville Syrjälä
Put the code into a function with a descriptive name. Also relocate
the code a bit help future work.
Reviewed-by: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 36 +++--
drivers/gpu/drm/i915/intel_pm.h |
From: Ville Syrjälä
skl_compute_dbuf_slices() has no use for the crtc state, so
just pass the crtc itself.
Reviewed-by: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff
From: Ville Syrjälä
skl_ddb_get_pipe_allocation_limits() doesn't care how the weights
for distributing the ddb are caclculated for each pipe. Put that
calculation into a separate function so that such mundane details
are hidden from view.
v2: s/adjusted_mode/pipe_mode/
Reviewed-by: Stanislav
From: Ville Syrjälä
GLK blew up in ci in the glk_force_audio_cdclk() path. The
reason being some reordering in intel_atomic_check() so we're
no longer guaranteed to have a dbuf_state when we commit crtcs.
So I changed the approach slightly to keep duplicate pipe ddb
allocations in the crtc state
Now that all display-related functions are grouped in
i915_driver_register(), move them to display/ so we reduce the amount of
display calls from the rest of the driver.
Signed-off-by: Lucas De Marchi
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_display.c | 54
intel_gt_driver_register() may be called earlier than
intel_opregion_register() and acpi_video_register(), so move it up.
intel_display_debugfs_register() may be called later, together with the
other display-related initializations. There is a slight change in
behavior that sysfs files will show
If drm_dev_register() fails there is no reason to continue registering
the driver and initializing.
Signed-off-by: Lucas De Marchi
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git
== Series Details ==
Series: drm/i915/dmabuf: don't trust the dma_buf->size
URL : https://patchwork.freedesktop.org/series/86190/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19464
Summary
---
On Thu, Jan 21, 2021 at 04:19:36PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Commit 6ce1c33d6c36 ("drm/i915: Kill INTEL_SUBPLATFORM_AML") removed the
only platform which used bit 2 so could also decrease the
INTEL_SUBPLATFORM_BITS definition.
This is not a fixes material but still
>-Original Message-
>From: Intel-gfx On Behalf Of
>Matthew Auld
>Sent: Wednesday, January 20, 2021 12:46 PM
>To: Chris Wilson
>Cc: Intel Graphics Development ; Auld,
>Matthew
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/gem: Allow importing of shmemfs
>objects into any device
>
>On Wed,
== Series Details ==
Series: drm/i915/buddy: document the unused header bits
URL : https://patchwork.freedesktop.org/series/86189/
State : warning
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
CC [M]
== Series Details ==
Series: drm/i915/buddy: document the unused header bits
URL : https://patchwork.freedesktop.org/series/86189/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19463
Summary
---
Trailing newlines before closing the function are best forgotten, or
else checkpatch moans.
Signed-off-by: Chris Wilson
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 1 -
drivers/gpu/drm/i915/gt/intel_rc6.c| 1 -
2 files changed, 2 deletions(-)
Checkpatch spotted a few repeated words in the comment, genuine
mistakes.
Signed-off-by: Chris Wilson
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
Remember to align parameters to the '(', thanks checkpatch
Signed-off-by: Chris Wilson
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +--
2 files changed, 3 insertions(+), 4 deletions(-)
Checkpatch wants spaces, let's give it some spaces.
Signed-off-by: Chris Wilson
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
Checkpatch spotted a couple of commas where we can use the more common
';', and so not worry about the subtle implications of sequence points.
Signed-off-by: Chris Wilson
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.h| 4 ++--
Checkpatch worries that the 'return' before an else clause might be
redundant. In this case, it is avoiding hitting the MISSING_CASE()
warning. Let us appease checkpatch by falling through to the end of the
function, which typically means that we then clean up the unused
wa_list.
Signed-off-by:
Trivial checkpatch cleanup.
Signed-off-by: Chris Wilson
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/debugfs_gt.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +++
drivers/gpu/drm/i915/gt/intel_renderstate.c |
Checkpatch noticed a while(0) and complains about the lack of space.
Signed-off-by: Chris Wilson
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c
Checkpatch noticed that ppgtt->pd should have been (ppgtt)->pd to avoid
issues with macros.
Signed-off-by: Chris Wilson
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Clean up the SPDX licence declarations to comply with checkpatch.
Signed-off-by: Chris Wilson
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/debugfs_gt.c | 1 -
drivers/gpu/drm/i915/gt/gen6_renderstate.c| 20 +
drivers/gpu/drm/i915/gt/gen7_renderstate.c
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: SPDX cleanup
URL : https://patchwork.freedesktop.org/series/86185/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19461
Summary
== Series Details ==
Series: drm/i915/hdcp: Fix return of value in uninitialized variable ret
URL : https://patchwork.freedesktop.org/series/86186/
State : failure
== Summary ==
Applying: drm/i915/hdcp: Fix return of value in uninitialized variable ret
Using index info to reconstruct a base
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: SPDX cleanup
URL : https://patchwork.freedesktop.org/series/86185/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: SPDX cleanup
URL : https://patchwork.freedesktop.org/series/86185/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
80d2e2637324 drm/i915/gt: SPDX cleanup
25941d069d19 drm/i915/gt: Add some missing blank lines
== Series Details ==
Series: series starting with [1/4] drm/i915: Nuke not needed members of
dram_info (rev3)
URL : https://patchwork.freedesktop.org/series/86092/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19460
Quoting Matthew Auld (2021-01-22 18:15:14)
> Throw it into a simple helper, and throw a warning if we encounter an
> object which has been initialised with an object size that exceeds our
> limit of INT_MAX pages.
>
> Suggested-by: Chris Wilson
> Signed-off-by: Matthew Auld
Reviewed-by: Chris
Quoting Matthew Auld (2021-01-22 18:15:13)
> At least for the time being, we need to limit our object sizes such that
> the number of pages can fit within a 32b signed int. It looks like we
> should also apply the same restriction to any imported dma-buf.
>
> Signed-off-by: Matthew Auld
>From
At least for the time being, we need to limit our object sizes such that
the number of pages can fit within a 32b signed int. It looks like we
should also apply the same restriction to any imported dma-buf.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 10
Throw it into a simple helper, and throw a warning if we encounter an
object which has been initialised with an object size that exceeds our
limit of INT_MAX pages.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 9 +--
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/gt: Show the per-engine runtime
in sysfs
URL : https://patchwork.freedesktop.org/series/86180/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19458
== Series Details ==
Series: drm/i915/selftest: Fix potential memory leak
URL : https://patchwork.freedesktop.org/series/86181/
State : failure
== Summary ==
Applying: drm/i915/selftest: Fix potential memory leak
Using index info to reconstruct a base tree...
M
On 1/21/21 11:06 PM, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20210121:
>
> The drm-intel tree lost its build failure.
>
> The notifications tree gained conflicts against the keys tree.
>
> Non-merge commits (relative to Linus' tree): 4819
> 5269 files changed, 192976
Quoting Matthew Auld (2021-01-22 17:54:16)
> On Fri, 22 Jan 2021 at 17:43, Chris Wilson wrote:
> >
> > Quoting Matthew Auld (2021-01-22 17:35:46)
> > > Throw it into a simple helper, and throw a warning if we encounter an
> > > object which has been initialised with an object size that exceeds
On Fri, 22 Jan 2021 at 17:43, Chris Wilson wrote:
>
> Quoting Matthew Auld (2021-01-22 17:35:46)
> > Throw it into a simple helper, and throw a warning if we encounter an
> > object which has been initialised with an object size that exceeds our
> > limit of INT_MAX pages.
> >
> > Suggested-by:
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/gt: Show the per-engine runtime
in sysfs
URL : https://patchwork.freedesktop.org/series/86180/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
Quoting Matthew Auld (2021-01-22 17:35:46)
> Throw it into a simple helper, and throw a warning if we encounter an
> object which has been initialised with an object size that exceeds our
> limit of INT_MAX pages.
>
> Suggested-by: Chris Wilson
> Signed-off-by: Matthew Auld
> ---
>
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/gt: Show the per-engine runtime
in sysfs
URL : https://patchwork.freedesktop.org/series/86180/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e718194c32ae drm/i915/gt: Show the per-engine runtime in sysfs
== Series Details ==
Series: drm/i915/selftests: Check for engine-reset errors in the middle of
workarounds
URL : https://patchwork.freedesktop.org/series/86179/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19457
Throw it into a simple helper, and throw a warning if we encounter an
object which has been initialised with an object size that exceeds our
limit of INT_MAX pages.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 9 +--
At least for the time being, we need to limit our object sizes such that
the number of pages can fit within a 32b signed int. It looks like we
should also apply the same restriction to any imported dma-buf.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 10
a) How are you scheduling flips for ChromeOS HWDRM overlays(not primary planes)?
b) For this you need to understand race. The race is between - Display HW
detecting that there is HDCP display config change and deciding to destroy
crypto context vs. Display HW flipping HWDRM protected surface.
== Series Details ==
Series: series starting with [v1,1/2] drm/gma500: Convert to use new SCU IPC API
URL : https://patchwork.freedesktop.org/series/86178/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19456
Re-reported.
-Original Message-
From: Imre Deak
Sent: Friday, January 22, 2021 6:34 AM
To: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
; Pandiyan, Dhinakaran
; Kahola, Mika ; Roper,
Matthew D ; Chery, Nanley G
; Chris Wilson ; Daniel
Vetter ; Nikula, Jani ; Vudum,
== Series Details ==
Series: drm/i915/gen12: Add display render clear color decompression support
(rev5)
URL : https://patchwork.freedesktop.org/series/85877/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19433_full
== Series Details ==
Series: drm/i915/gt: Move the defer_request waiter active assertion (rev2)
URL : https://patchwork.freedesktop.org/series/86176/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9670 -> Patchwork_19455
Quoting Michal Wajdeczko (2021-01-22 16:03:38)
>
>
> On 22.01.2021 16:49, Chris Wilson wrote:
> > Quoting Michal Wajdeczko (2021-01-22 15:43:26)
> >>
> >>
> >> On 22.01.2021 16:06, Chris Wilson wrote:
> >>> Clean up the SPDX licence declarations to comply with checkpatch.
> >>
> >> typo here and
Quoting Matthew Auld (2021-01-22 15:45:46)
> The largest possible order is (63-12), given that our min chunk size is
> 4K. With that we should only need at most 6 bits to represent all
> possible orders, giving us back 4 bits for other potential uses. Include
> a simple selftest to verify this.
>
On 22.01.2021 16:49, Chris Wilson wrote:
> Quoting Michal Wajdeczko (2021-01-22 15:43:26)
>>
>>
>> On 22.01.2021 16:06, Chris Wilson wrote:
>>> Clean up the SPDX licence declarations to comply with checkpatch.
>>
>> typo here and in the commit message 04/10
>
> s/paramters/parameters/
and
Quoting Matthew Auld (2021-01-22 15:56:28)
> At least for the time being, we need to limit our object sizes such that
> the number of pages can fit within a 32b signed int. It looks like we
> should also apply the same restriction to any imported dma-buf.
>
> Signed-off-by: Matthew Auld
> ---
>
At least for the time being, we need to limit our object sizes such that
the number of pages can fit within a 32b signed int. It looks like we
should also apply the same restriction to any imported dma-buf.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 10
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