On 3/13/21 8:43 PM, Bhaskar Chowdhury wrote:
>
> s/bariers/barriers/
>
> Signed-off-by: Bhaskar Chowdhury
Acked-by: Randy Dunlap
> ---
> drivers/gpu/drm/i915/gt/intel_timeline.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
On Fri, 2021-03-12 at 05:37 -0800, Souza, Jose wrote:
> On Fri, 2021-03-12 at 15:34 +0200, Gwan-gyeong Mun wrote:
> > If the sink state is not reliable, it does not need to wait for
> > PSR "IDLE state" for re-enabling PSR. And it should not try to re-
> > enable
> > PSR.
> >
> > Signed-off-by: Gw
On Thu, 2021-03-11 at 14:36 -0800, Matt Roper wrote:
> From: José Roberto de Souza
>
> Implements changes around PSR for alderlake-P:
>
> - EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
> - Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
> removed settin
On Fri, Mar 12, 2021 at 08:02:36PM +0200, Ville Syrjälä wrote:
> [...]
> On Thu, Mar 11, 2021 at 12:17:34AM +0200, Imre Deak wrote:
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index fc02eca45e4d..08b348c9e3e1 1006