On 02/06/2022 00:18, Matthew Brost wrote:
On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
+VM_BIND/UNBIND ioctl will immediately start binding/unbinding the mapping in an
+async worker. The binding and unbinding will work
On Wed, Jun 01, 2022 at 11:27:17AM +0200, Daniel Vetter wrote:
On Wed, 1 Jun 2022 at 11:03, Dave Airlie wrote:
On Tue, 24 May 2022 at 05:20, Niranjana Vishwanathapura
wrote:
>
> On Thu, May 19, 2022 at 04:07:30PM -0700, Zanoni, Paulo R wrote:
> >On Tue, 2022-05-17 at 11:32 -0700, Niranjana
Regards,
Oak
> -Original Message-
> From: dri-devel On Behalf Of
> Niranjana Vishwanathapura
> Sent: May 17, 2022 2:32 PM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Vetter,
> Daniel
> Cc: Brost, Matthew ; Hellstrom, Thomas
> ; ja...@jlekstrand.net;
== Series Details ==
Series: drm/i915: Add extra registers to GPU error dump
URL : https://patchwork.freedesktop.org/series/104630/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11717_full -> Patchwork_104630v1_full
== Series Details ==
Series: drm/i915: Parse more eDP link rate stuff from VBT
URL : https://patchwork.freedesktop.org/series/104615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11717_full -> Patchwork_104615v1_full
== Series Details ==
Series: drm/i915: Add extra registers to GPU error dump
URL : https://patchwork.freedesktop.org/series/104630/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11717 -> Patchwork_104630v1
Summary
---
== Series Details ==
Series: drm/i915: Add extra registers to GPU error dump
URL : https://patchwork.freedesktop.org/series/104630/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
> On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
> > +VM_BIND/UNBIND ioctl will immediately start binding/unbinding the mapping
> > in an
> > +async worker. The binding and unbinding will work like a special GPU
> >
From: Stuart Summers
Our internal teams have identified a few additional engine registers
that are worth inspecting in error state dumps during development &
debug. Let's capture and print them as part of our error dump.
For simplicity we'll just dump these registers on gen11 and beyond.
Most
== Series Details ==
Series: i915: SSEU handling updates
URL : https://patchwork.freedesktop.org/series/104611/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11717_full -> Patchwork_104611v1_full
Summary
---
On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
> On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
> > +VM_BIND/UNBIND ioctl will immediately start binding/unbinding the mapping
> > in an
> > +async worker. The binding and unbinding will work like a special GPU
> >
>-Original Message-
>From: Adrian Larumbe
>Sent: Friday, May 27, 2022 12:08 PM
>To: Ruhl, Michael J
>Cc: dan...@ffwll.ch; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [RFC PATCH v2 1/1] drm/i915: Replace shmem memory
>region and object backend with TTM
>
>On 17.05.2022
== Series Details ==
Series: drm/i915: Parse more eDP link rate stuff from VBT
URL : https://patchwork.freedesktop.org/series/104615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11717 -> Patchwork_104615v1
Summary
== Series Details ==
Series: i915: SSEU handling updates
URL : https://patchwork.freedesktop.org/series/104611/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11717 -> Patchwork_104611v1
Summary
---
**SUCCESS**
No
== Series Details ==
Series: i915: SSEU handling updates
URL : https://patchwork.freedesktop.org/series/104611/
State : warning
== Summary ==
Error: dim checkpatch failed
92101c27eef9 drm/i915/xehp: Use separate sseu init function
7489d9903596 drm/i915/xehp: Drop GETPARAM lookups of
From: Ville Syrjälä
We're not parsing the 5.4 Gbps value for the old eDP fast link
training link rate, nor are we parsing the new fast link training
link rate field. Remedy both.
Note that we're not even using this information for anything
currently, so should perhaps just nuke it all unless
From: Ville Syrjälä
The eDP BDB block has gained yet another max link rate field.
Let's parse it and consult it during the source rate filtering.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 4
.../drm/i915/display/intel_display_types.h| 1 +
From: Ville Syrjälä
We'll need to know the VBT panel_type before we can determine the
maximum link rate for eDP. To that end move
intel_dp_set_source_rates() & co. to be called after the per-panel
VBT parsing has been done.
I'm not immediately spotting anything that would consult the link
rate
From: Ville Syrjälä
VBT has gained a couple of new ways to specify fast link training
and maximum link rates. Parse all of it.
Ville Syrjälä (3):
drm/i915: Initialize eDP source rates after per-panel VBT parsing
drm/i915: Update eDP fast link training link rate parsing
drm/i915: Parse max
Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform). We can simplify the code slightly by
dropping the
Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.
The slice mask lookup is meaningless since Xe_HP doesn't support
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose
Xe_HP has enough fundamental differences from previous platforms that it
makes sense to use a separate SSEU init function to keep things
straightforward and easy to understand. We'll also add a has_xehp_dss
flag to the SSEU structure that will be used by other upcoming changes.
v2:
- Add
Storing the EU mask internally in the same format the I915_QUERY
topology queries use makes the final copy_to_user() a bit simpler, but
makes the rest of the driver's SSEU more complicated and harder to
follow. Let's switch to an internal representation that's more natural:
Xe_HP platforms will
This series reworks i915's internal handling of slice/subslice/EU (SSEU)
data to represent platforms like Xe_HP in a more natural manner and to
PVC splits the mask of enabled DSS over two registers. It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.
Signed-off-by: Matt Roper
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
On Wed, Jun 01, 2022 at 01:48:56PM +0530, Balasubramani Vivekanandan wrote:
> On 23.05.2022 13:45, Matt Roper wrote:
> > As with EU masks, it's easier to store subslice/DSS masks internally in
> > a format that's more natural for the driver to work with, and then only
> > covert into the u8[] uapi
On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
+VM_BIND/UNBIND ioctl will immediately start binding/unbinding the mapping in an
+async worker. The binding and unbinding will work like a special GPU engine.
+The binding and unbinding operations are serialized and will wait on specified
Acked-by: Nirmoy Das
On 5/25/2022 8:43 PM, Matthew Auld wrote:
Userspace wants to know the size of CPU visible portion of device
local-memory, and on small BAR devices the probed_size is no longer
enough. In Vulkan, for example, it would like to know the size in bytes
for CPU visible
Reviewed-by: Nirmoy Das
On 5/25/2022 8:43 PM, Matthew Auld wrote:
Skip capturing any lmem pages that can't be copied using the CPU. This
in now only best effort on platforms that have small BAR.
Testcase: igt@gem-exec-capture@capture-invisible
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
LGTM Reviewed-by: Nirmoy Das
On 5/25/2022 8:43 PM, Matthew Auld wrote:
If set, force the allocation to be placed in the mappable portion of
I915_MEMORY_CLASS_DEVICE. One big restriction here is that system memory
(i.e I915_MEMORY_CLASS_SYSTEM) must be given as a potential placement for the
On Tue-31-05-2022 07:26 pm, Daniel Vetter wrote:
On Tue, May 17, 2022 at 12:56:34PM +0530, Bhanuprakash Modem wrote:
This series will add a support to set the vrr_enabled property for
crtc based on the platform support and the request from userspace.
And userspace can also query to get the
On Tue-31-05-2022 10:42 pm, Navare, Manasi wrote:
On Tue, May 17, 2022 at 12:56:35PM +0530, Bhanuprakash Modem wrote:
Modern display hardware is capable of supporting variable refresh rates.
This patch introduces helpers to attach and set "vrr_enabled" property
on the crtc to allow userspace to
On Tue-31-05-2022 10:44 pm, Navare, Manasi wrote:
On Tue, May 17, 2022 at 12:56:36PM +0530, Bhanuprakash Modem wrote:
This function sets the vrr_enabled property for crtc based
on the platform support and the request from userspace.
V2: Check for platform support before updating the prop.
V3:
On Tue, 31 May 2022, Andrzej Hajda wrote:
> On 31.05.2022 18:25, Jani Nikula wrote:
>> Avoid bringing the entire machine down even if there's a bug that
>> shouldn't happen, but won't corrupt the system either. Log them loudly
>> and limp on.
>>
>> Signed-off-by: Jani Nikula
>
> All BUG() cases
Thanks, Andrzej.
Sounds good. It is better to make drm_display_mode_from_vic_index() return a
mode with valid VIC.
So it ends up with that all probed modes have valid VICs for HDMI 1.4 and 2.0
respectively.
Regards
William
-Original Message-
From: Hajda, Andrzej
Sent: Tuesday, May
== Series Details ==
Series: drm/i915/display: stop using BUG() (rev4)
URL : https://patchwork.freedesktop.org/series/104559/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11715_full -> Patchwork_104559v4_full
Summary
On Wed, 1 Jun 2022 at 11:03, Dave Airlie wrote:
>
> On Tue, 24 May 2022 at 05:20, Niranjana Vishwanathapura
> wrote:
> >
> > On Thu, May 19, 2022 at 04:07:30PM -0700, Zanoni, Paulo R wrote:
> > >On Tue, 2022-05-17 at 11:32 -0700, Niranjana Vishwanathapura wrote:
> > >> VM_BIND and related uapi
On Tue, 24 May 2022 at 05:20, Niranjana Vishwanathapura
wrote:
>
> On Thu, May 19, 2022 at 04:07:30PM -0700, Zanoni, Paulo R wrote:
> >On Tue, 2022-05-17 at 11:32 -0700, Niranjana Vishwanathapura wrote:
> >> VM_BIND and related uapi definitions
> >>
> >> v2: Ensure proper kernel-doc formatting
== Series Details ==
Series: i915 writeback enablement
URL : https://patchwork.freedesktop.org/series/104591/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
On Tue, May 31, 2022 at 6:56 PM Hans de Goede wrote:
>
> Hi,
>
> On 5/30/22 13:34, Hsin-Yi Wang wrote:
> > On Mon, May 30, 2022 at 4:53 PM Hans de Goede wrote:
> >>
> >> Hi,
> >>
> >> On 5/30/22 10:19, Hsin-Yi Wang wrote:
> >>> Some drivers, eg. mtk_drm and msm_drm, rely on the panel to set the
Adding support for writeback transcoder to start capturing frames using
interrupt mechanism.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 369
Adding WD Types, WD transcoder to enum list and WD Transcoder offsets
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 6 ++
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/i915_reg.h| 2 ++
3 files
With this we try to enable writeback feature keeping with the drm_core
drm_writeback framework but to do this we have to create a drm_encoder and
drm_connector which is not present in intel_connector and intel_encoder
which causes all our iterators to bug out as they assume any drm_encoder
and
On 23.05.2022 13:45, Matt Roper wrote:
> As with EU masks, it's easier to store subslice/DSS masks internally in
> a format that's more natural for the driver to work with, and then only
> covert into the u8[] uapi form when the query ioctl is invoked. Since
> the hardware design changed
== Series Details ==
Series: drm/i915/display: stop using BUG() (rev4)
URL : https://patchwork.freedesktop.org/series/104559/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11715 -> Patchwork_104559v4
Summary
---
== Series Details ==
Series: drm/i915: Support Async Flip on Linear buffers (rev2)
URL : https://patchwork.freedesktop.org/series/103137/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11715_full -> Patchwork_103137v2_full
On 17/05/2022 06:20, Matt Roper wrote:
Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.
The slice mask lookup is
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