== Series Details ==
Series: drm/doc/rfc: i915 VM_BIND feature design + uapi
URL : https://patchwork.freedesktop.org/series/105267/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
VM_BIND and related uapi definitions
v2: Reduce the scope to simple Mesa use case.
Signed-off-by: Niranjana Vishwanathapura
---
Documentation/gpu/rfc/i915_vm_bind.h | 226 +++
1 file changed, 226 insertions(+)
create mode 100644 Documentation/gpu/rfc/i915_vm_bind.h
Add some missing i915 upai documentation which the new
i915 VM_BIND feature documentation will be refer to.
Signed-off-by: Niranjana Vishwanathapura
Reviewed-by: Matthew Auld
---
include/uapi/drm/i915_drm.h | 205
1 file changed, 160 insertions(+), 45
VM_BIND design document with description of intended use cases.
v2: Reduce the scope to simple Mesa use case.
Signed-off-by: Niranjana Vishwanathapura
---
Documentation/gpu/rfc/i915_vm_bind.rst | 238 +
Documentation/gpu/rfc/index.rst| 4 +
2 files changed,
This is the i915 driver VM_BIND feature design RFC patch series along
with the required uapi definition and description of intended use cases.
v2: Reduce the scope to simple Mesa use case.
Remove all compute related uapi, vm_bind/unbind queue support and
only support a timeline out fence
On Fri, Jun 10, 2022 at 12:07:08AM -0700, Niranjana Vishwanathapura wrote:
This is the i915 driver VM_BIND feature design RFC patch series along
with the required uapi definition and description of intended use cases.
Some of us had an offline dicussion on this.
Based on that,
1) The scope
On Thu, 16 Jun 2022 15:01:59 -0700, Zhanjun Dong wrote:
>
> We are seeing error message of "No response for request". Some cases
> happened while waiting for response and reset/suspend action was triggered.
> In this case, no response is not an error, active requests will be
> cancelled.
>
> This
On Thu, 16 Jun 2022 15:01:59 -0700, Zhanjun Dong wrote:
>
> We are seeing error message of "No response for request". Some cases
> happened while waiting for response and reset/suspend action was triggered.
> In this case, no response is not an error, active requests will be
> cancelled.
>
> This
== Series Details ==
Series: Add support for LMEM PCIe resizable bar
URL : https://patchwork.freedesktop.org/series/105231/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11769_full -> Patchwork_105231v1_full
Summary
== Series Details ==
Series: series starting with [1/2] agp/intel: Rename intel-gtt symbols
URL : https://patchwork.freedesktop.org/series/105261/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11773 -> Patchwork_105261v1
== Series Details ==
Series: series starting with [1/2] agp/intel: Rename intel-gtt symbols
URL : https://patchwork.freedesktop.org/series/105261/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [1/2] agp/intel: Rename intel-gtt symbols
URL : https://patchwork.freedesktop.org/series/105261/
State : warning
== Summary ==
Error: dim checkpatch failed
e1bbe8530903 agp/intel: Rename intel-gtt symbols
deae3fe392d9 drm/i915/gt: Re-do the
== Series Details ==
Series: i915/pmu: Wire GuC backend to per-client busyness (rev3)
URL : https://patchwork.freedesktop.org/series/105085/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11773 -> Patchwork_105085v3
Summary
== Series Details ==
Series: drm/i915/fdinfo: Don't show engine classes not present
URL : https://patchwork.freedesktop.org/series/105228/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11768_full -> Patchwork_105228v1_full
== Series Details ==
Series: i915/pmu: Wire GuC backend to per-client busyness (rev3)
URL : https://patchwork.freedesktop.org/series/105085/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/guc: Check for ct enabled while waiting for response
URL : https://patchwork.freedesktop.org/series/105258/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11773 -> Patchwork_105258v1
== Series Details ==
Series: drm/i915/glk: ECS Liva Q2 needs GLK HDMI port timing quirk
URL : https://patchwork.freedesktop.org/series/105226/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11768_full -> Patchwork_105226v1_full
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add smem fallback
allocation for dpt (rev5)
URL : https://patchwork.freedesktop.org/series/104983/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11772 -> Patchwork_104983v5
== Series Details ==
Series: drm/i915/dgfx: Disable d3cold Correctly (rev2)
URL : https://patchwork.freedesktop.org/series/104770/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11768_full -> Patchwork_104770v2_full
Summary
On Thu, Jun 16, 2022 at 05:31:00PM +0530, Anshuman Gupta wrote:
> DG2 NB SKU need to distinguish between MBD and AIC to probe
> the VRAM Self Refresh feature support. Adding those sub platform
> accordingly.
>
> Cc: Matt Roper
> Signed-off-by: Anshuman Gupta
> ---
>
== Series Details ==
Series: DG2 VRAM_SR Support (rev3)
URL : https://patchwork.freedesktop.org/series/104128/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11768_full -> Patchwork_104128v3_full
Summary
---
Exporting the symbols like intel_gtt_* creates some confusion inside
i915 that has symbols named similarly. In an attempt to isolate
platforms needing intel-gtt.ko, commit 7a5c922377b4 ("drm/i915/gt: Split
intel-gtt functions by arch") moved way too much
inside gt/intel_gt_gmch.c, even the
Re-do what was attempted in commit 7a5c922377b4 ("drm/i915/gt: Split
intel-gtt functions by arch"). The goal of that commit was to split the
handlers for older hardware that depend on intel-gtt.ko so i915 can
be built for non-x86 archs, after some more patches. Other archs do not
need
Thanks for adding these tests. I ran these with the kernel patch I had
posted for GuC support and updated the patch to work with virtual
engines - https://patchwork.freedesktop.org/series/105085/#rev3
I have listed some changes I had to do in the below patch. With those
(or similar changes),
From: John Harrison
GuC provides engine_id and last_switch_in ticks for an active context in
the pphwsp. The context image provides a 32 bit total ticks which is the
accumulated by the context (a.k.a. context[CTX_TIMESTAMP]). This
information is used to calculate the context busyness as follows:
We are seeing error message of "No response for request". Some cases
happened while waiting for response and reset/suspend action was triggered.
In this case, no response is not an error, active requests will be
cancelled.
This patch will handle this condition and change the error message into
== Series Details ==
Series: i915/pmu: Wire GuC backend to per-client busyness (rev2)
URL : https://patchwork.freedesktop.org/series/105085/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11770 -> Patchwork_105085v2
Summary
== Series Details ==
Series: i915/pmu: Wire GuC backend to per-client busyness (rev2)
URL : https://patchwork.freedesktop.org/series/105085/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/dp/mst: Read the extended DPCD capabilities during system resume
URL : https://patchwork.freedesktop.org/series/105102/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11756_full -> Patchwork_105102v1_full
Failure is related to https://gitlab.freedesktop.org/drm/intel/-/issues/3063
Lakshmi.
-Original Message-
From: Deak, Imre
Sent: Thursday, June 16, 2022 11:58 AM
To: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
Lyude Paul ; Vudum, Lakshminarayana
Cc:
== Series Details ==
Series: Add support for LMEM PCIe resizable bar
URL : https://patchwork.freedesktop.org/series/105231/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11769 -> Patchwork_105231v1
Summary
---
== Series Details ==
Series: Add support for LMEM PCIe resizable bar
URL : https://patchwork.freedesktop.org/series/105231/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: John Harrison
GuC provides engine_id and last_switch_in ticks for an active context in
the pphwsp. The context image provides a 32 bit total ticks which is the
accumulated by the context (a.k.a. context[CTX_TIMESTAMP]). This
information is used to calculate the context busyness as follows:
On Thu, Jun 16, 2022 at 09:57:43PM +0300, Imre Deak wrote:
> On Wed, Jun 15, 2022 at 04:25:34AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/dp/mst: Read the extended DPCD capabilities during system resume
> > URL : https://patchwork.freedesktop.org/series/105102/
> >
On Wed, Jun 15, 2022 at 04:25:34AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/dp/mst: Read the extended DPCD capabilities during system resume
> URL : https://patchwork.freedesktop.org/series/105102/
> State : failure
Thanks for the reviews, pushed the patch to
== Series Details ==
Series: drm/i915: drm/i915/display: split out verification, hw readout and dump
from intel_display.c
URL : https://patchwork.freedesktop.org/series/105220/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11767_full -> Patchwork_105220v1_full
== Series Details ==
Series: drm/i915/fdinfo: Don't show engine classes not present
URL : https://patchwork.freedesktop.org/series/105228/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11768 -> Patchwork_105228v1
Summary
== Series Details ==
Series: drm/i915/glk: ECS Liva Q2 needs GLK HDMI port timing quirk
URL : https://patchwork.freedesktop.org/series/105226/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11768 -> Patchwork_105226v1
== Series Details ==
Series: Do not enable PSR2 if no active planes (rev3)
URL : https://patchwork.freedesktop.org/series/105109/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11767_full -> Patchwork_105109v3_full
Summary
Hi Lakshmi,
Here would be another false positive, I don't see how my changes would
affect debugfs_test@read_all_entries test on kbl.
/Juha-Pekka
to 16. kesäk. 2022 klo 19.31 Patchwork
kirjoitti:
> *Patch Details*
> *Series:* series starting with [1/3] drm/i915/display: Add smem fallback
>
== Series Details ==
Series: drm/i915/dgfx: Disable d3cold Correctly (rev2)
URL : https://patchwork.freedesktop.org/series/104770/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11768 -> Patchwork_104770v2
Summary
---
== Series Details ==
Series: DG2 VRAM_SR Support (rev3)
URL : https://patchwork.freedesktop.org/series/104128/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11768 -> Patchwork_104128v3
Summary
---
**SUCCESS**
No
On 15/06/2022 19:59, Lucas De Marchi wrote:
On Tue, Jun 14, 2022 at 08:07:04AM +0100, Tvrtko Ursulin wrote:
On 14/06/2022 02:10, Umesh Nerlige Ramappa wrote:
On Sat, Jun 11, 2022 at 10:27:11AM -0700, Alan Previn wrote:
Using igt's gem-create and with additional patches to track object
== Series Details ==
Series: DG2 VRAM_SR Support (rev3)
URL : https://patchwork.freedesktop.org/series/104128/
State : warning
== Summary ==
Error: dim checkpatch failed
ee513fcc2693 drm/i915/dgfx: OpRegion VRAM Self Refresh Support
341133e9b9ad drm/i915/dg1: OpRegion PCON DG1 MBD config
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add smem fallback
allocation for dpt (rev4)
URL : https://patchwork.freedesktop.org/series/104983/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11768 -> Patchwork_104983v4
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add smem fallback
allocation for dpt (rev4)
URL : https://patchwork.freedesktop.org/series/104983/
State : warning
== Summary ==
Error: dim checkpatch failed
4c23115bcf5b drm/i915/display: Add smem fallback allocation
Hi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/priyanka-dandamudi-intel-com/Add-support-for-LMEM-PCIe-resizable-bar/20220616-201631
base: git://anongit.freedesktop.org/drm/drm-tip
/drm-tip drm-tip
config: i386-randconfig-a004
(https://download.01.org/0day-ci/archive/20220616/202206162323.1npq58gh-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project
f0e608de27b3d56846eebf3712ab542979d6)
reproduce (this is a W=1 build):
wget
We have a bug for a similar test timeout on KBL
https://gitlab.freedesktop.org/drm/intel/-/issues/6048
igt@kms_cursor_legacy@pipe-b-torture-move - incomplete - Received signal
SIGQUIT. Per-test timeout exceeded. Killing the current test with SIGQUIT.
Thanks,
Lakshmi.
-Original Message-
From: Priyanka Dandamudi
For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
From: Priyanka Dandamudi
Added support to resize the bar to maximum supported.
Also, added new modparam lmem_bar_size which can resize the bar to one of the
supported sizes.
Akeem G Abodunrin (1):
drm/i915: Add support for LMEM PCIe resizable bar
Priyanka Dandamudi (1):
drm/i915: Add
From: Akeem G Abodunrin
Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
On Thu, 16 Jun 2022, priyanka.dandam...@intel.com wrote:
> From: Akeem G Abodunrin
>
> This patch adds support for the local memory PICe resizable bar, so that
Please use imperative. "Add support ..."
Please don't refer to "this patch".
Please fix your git settings to not prefix with "i-g-t"
On Thu, 16 Jun 2022, priyanka.dandam...@intel.com wrote:
> From: Akeem G Abodunrin
>
> This patch adds support for the local memory PICe resizable bar, so that
> local memory can be resized to the maximum size supported by the device,
> and mapped correctly to the PCIe memory bar. It is usual
/drm-tip drm-tip
config: x86_64-defconfig
(https://download.01.org/0day-ci/archive/20220616/202206162239.am4qoo2c-...@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-3) 11.3.0
reproduce (this is a W=1 build):
#
https://github.com/intel-lab-lkp/linux/commit
On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
> On 16/06/2022 15:15, Jani Nikula wrote:
>> On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
>>> On 16/06/2022 13:01, Anshuman Gupta wrote:
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding
On 16/06/2022 15:15, Jani Nikula wrote:
On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
On 16/06/2022 13:01, Anshuman Gupta wrote:
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
Cc: Matt Roper
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Intel Client DGFX card supports D3Cold with two option.
> D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
>
> i915 requires to evict the lmem objects to smem in order to
> support D3Cold-Off, which increases i915 the suspend/resume
> latency. Enabling
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> From: Tvrtko Ursulin
>
> Store a pointer to respective local memory region in intel_gt so it can be
> used when memory local to a GT needs to be allocated.
>
> Cc: Andi Shyti
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Anshuman Gupta
> ---
>
On Thu, Jun 16, 2022 at 01:52:38PM +0300, Jani Nikula wrote:
> On Wed, 15 Jun 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Pull the underrun status sanitation into its own helper.
> >
> > Signed-off-by: Ville Syrjälä
>
> On the series,
>
> Reviewed-by: Jani Nikula
Thanks.
>
On Thu, Jun 16, 2022 at 01:48:16PM +0300, Jani Nikula wrote:
> On Wed, 15 Jun 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Abstract the bit extraction from the VBT per-panel bitfields
> > slightly.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> >
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Add d3cold_sr_lmem_threshold modparam to choose between
> d3cold-off zero watt and d3cold-VRAM Self Refresh.
> i915 requires to evict the lmem objects to smem in order to
> support d3cold-Off.
>
> If gfx root port is not capable of sending PME from
On Thu, Jun 16, 2022 at 03:00:56PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Stop displaying engine classes with no engines - it is not a huge problem
if they are shown, since the values will correctly be all zeroes, but it
does count as misleading.
Signed-off-by: Tvrtko Ursulin
On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
> On 16/06/2022 13:01, Anshuman Gupta wrote:
>> DG2 NB SKU need to distinguish between MBD and AIC to probe
>> the VRAM Self Refresh feature support. Adding those sub platform
>> accordingly.
>>
>> Cc: Matt Roper
>> Signed-off-by: Anshuman Gupta
>>
From: Tvrtko Ursulin
Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
to display a sorted by card and usage list of processes using GPUs.
Borrows a bit of code from intel_gpu_top but for now omits the fancy
features like interactive functionality, card selection,
From: Tvrtko Ursulin
Some libdrmclient operations require that inactive clients are last in the
list. Rather than relying on callers of the library sort routine to
implement their comparison callbacks correctly, enforce this order
directly in the library and let callers comparison callbacks
From: Tvrtko Ursulin
Prep code for incoming work.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 2 ++
lib/igt_drm_fdinfo.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/lib/igt_drm_fdinfo.c b/lib/igt_drm_fdinfo.c
index 68c89ad2c17e..b850d2210ae7 100644
---
From: Tvrtko Ursulin
Intel_gpu_top gets it's main engine configuration data via PMU probe and
uses that for per client view as well. Furthemore code so far assumed only
clients belonging from a single DRM card would be tracked in a single
clients list.
Break this inter-dependency by moving the
From: Tvrtko Ursulin
Require DRM minor match during client lookup.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
index c23a3fae9793..e11c8b18188f 100644
From: Tvrtko Ursulin
Just a re-send having rebased on top of latest tree.
Tvrtko Ursulin (8):
lib: Extract igt_drm_clients from intel_gpu_top
libdrmfdinfo: Allow specifying custom engine map
libdrmclients: Record client drm minor
libdrmclient: Support multiple DRM cards
libdrmfdinfo:
From: Tvrtko Ursulin
Instead of hard coding the engine names, allow a map of names to indices
to either be passed in or it gets auto-detected (less efficient) while
parsing.
---
lib/igt_drm_clients.c | 18 +---
lib/igt_drm_clients.h | 3 ++-
lib/igt_drm_fdinfo.c| 48
From: Tvrtko Ursulin
Prepare for supporting clients belonging to multiple DRM cards by storing
the DRM minor in the client record.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 22 ++
lib/igt_drm_clients.h | 1 +
2 files changed, 15 insertions(+), 8
From: Tvrtko Ursulin
Extract some code into a new library to prepare for further work towards
making a vendor agnostic gputop tool.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 432 ++
lib/igt_drm_clients.h | 85 +++
lib/meson.build |
From: Tvrtko Ursulin
Stop displaying engine classes with no engines - it is not a huge problem
if they are shown, since the values will correctly be all zeroes, but it
does count as misleading.
Signed-off-by: Tvrtko Ursulin
Fixes: 055634e4b62f ("drm/i915: Expose client engine utilisation via
== Series Details ==
Series: drm/i915: Remove bogus LPT iCLKIP WARN
URL : https://patchwork.freedesktop.org/series/105221/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11767 -> Patchwork_105221v1
Summary
---
From: Tvrtko Ursulin
We need some coverage of the virtual engines.
Signed-off-by: Tvrtko Ursulin
Cc: Umesh Nerlige Ramappa
---
tests/i915/drm_fdinfo.c | 284 +++-
1 file changed, 282 insertions(+), 2 deletions(-)
diff --git a/tests/i915/drm_fdinfo.c
== Series Details ==
Series: drm/i915: drm/i915/display: split out verification, hw readout and dump
from intel_display.c
URL : https://patchwork.freedesktop.org/series/105220/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11767 -> Patchwork_105220v1
== Series Details ==
Series: drm/i915: drm/i915/display: split out verification, hw readout and dump
from intel_display.c
URL : https://patchwork.freedesktop.org/series/105220/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: drm/i915: drm/i915/display: split out verification, hw readout and dump
from intel_display.c
URL : https://patchwork.freedesktop.org/series/105220/
State : warning
== Summary ==
Error: dim checkpatch failed
ab29d65b77e1 drm/i915/wm: move wm state verification to
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
> configs. MBD config requires HOST BIOS GPIO toggling support
> in order to enable/disable VRAM SR using ACPI OpRegion.
>
> i915 requires to check OpRegion PCON MBD Config bits to
>
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
> DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
> opportunistic S0ix system wide suspend flow as well.
>
> Without VRSR enablement i915 has to evict the lmem objects
== Series Details ==
Series: Do not enable PSR2 if no active planes (rev3)
URL : https://patchwork.freedesktop.org/series/105109/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11767 -> Patchwork_105109v3
Summary
---
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Setup VRAM Self Refresh with D3COLD state.
> VRAM Self Refresh will retain the context of VRAM, driver
> need to save any corresponding hardware state that needs
> to be restore on D3COLD exit, example PCI state.
>
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
From: Diego Santa Cruz
The quirk added in upstream commit 90c3e2198777 ("drm/i915/glk: Add
Quirk for GLK NUC HDMI port issues.") is also required on the ECS Liva
Q2.
Note: Would be nicer to figure out the extra delay required for the
retimer without quirks, however don't know how to check for
Currently i915 disables d3cold for i915 pci dev.
This blocks D3 for i915 gfx pci upstream bridge (VSP).
Let's disable d3cold at gfx root port to make sure that
i915 gfx VSP can transition to D3 to save some power.
We don't need to disable/enable d3cold in rpm, s2idle
suspend/resume handlers.
From: Priyanka Dandamudi
For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
From: Akeem G Abodunrin
This patch adds support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible
From: Priyanka Dandamudi
Added support to resize the bar to maximum supported.
Also, added new modparam lmem_bar_size which can resize the bar
to one of the supported sizes.
Akeem G Abodunrin (1):
drm/i915: Add support for LMEM PCIe resizable bar
Priyanka Dandamudi (1):
drm/i915: Add
On 16/06/2022 13:01, Anshuman Gupta wrote:
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
Cc: Matt Roper
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
Add d3cold_sr_lmem_threshold modparam to choose between
d3cold-off zero watt and d3cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support d3cold-Off.
If gfx root port is not capable of sending PME from d3cold
then i915 don't need to program
From: Tvrtko Ursulin
Store a pointer to respective local memory region in intel_gt so it can be
used when memory local to a GT needs to be allocated.
Cc: Andi Shyti
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
Intel Client DGFX card supports D3Cold with two option.
D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support D3Cold-Off, which increases i915 the suspend/resume
latency. Enabling VRAM Self Refresh feature optimize the
latency with
Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit, example PCI state.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
Add has_lmem_sr platform specific flag to know,
whether platform has VRAM self refresh support.
As of now both DG1 and DG2 client platforms supports VRAM self refresh
with D3Cold but let it enable first on DG2 as primary lead platform
for D3Cold support. Let it get enable on DG1 once this feature
Add DG2 Motherboard Down Config check support.
v2:
- Don't use pciid to check DG2 MBD. [Jani]
BSpec: 44477
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 9 +
2 files changed, 11
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
Cc: Matt Roper
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_device_info.c | 21
DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
configs. MBD config requires HOST BIOS GPIO toggling support
in order to enable/disable VRAM SR using ACPI OpRegion.
i915 requires to check OpRegion PCON MBD Config bits to
discover whether Gfx Card is MBD config before enabling
Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
opportunistic S0ix system wide suspend flow as well.
Without VRSR enablement i915 has to evict the lmem objects to
system memory. Depending on some heuristics driver
This series add DG2 D3Cold VRAM_SR support.
TODO: GuC Interface state save/restore on VRAM_SR entry/exit.
Anshuman Gupta (8):
drm/i915/dgfx: OpRegion VRAM Self Refresh Support
drm/i915/dg1: OpRegion PCON DG1 MBD config support
drm/i915/dg2: Add DG2_NB_MBD subplatform
drm/i915/dg2: DG2
On 5/25/22 20:43, Matthew Auld wrote:
Userspace wants to know the size of CPU visible portion of device
local-memory, and on small BAR devices the probed_size is no longer
enough. In Vulkan, for example, it would like to know the size in bytes
for CPU visible VkMemoryHeap. We already track the
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