[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

== Series Details == Series: drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode URL : https://patchwork.freedesktop.org/series/110130/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12294_full -> Patchwork_110130v1_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/xelp: Add Wa_1806527549 (rev2)

== Series Details == Series: drm/i915/xelp: Add Wa_1806527549 (rev2) URL : https://patchwork.freedesktop.org/series/109885/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12261_full -> Patchwork_109885v2_full Summary

Re: [Intel-gfx] mm/huge_memory: do not clobber swp_entry_t during THP split

On Tue, 25 Oct 2022, Andrew Morton wrote: > On Tue, 25 Oct 2022 11:03:38 +0100 Mel Gorman > wrote: > > > > If so I > > > can temporarily put it in until it arrives via the next rc - assuming that > > > would be the flow from upstream pov? > > > > > > > I expect it to. It's currently in the

Re: [Intel-gfx] mm/huge_memory: do not clobber swp_entry_t during THP split

On Tue, 25 Oct 2022 11:03:38 +0100 Mel Gorman wrote: > > If so I > > can temporarily put it in until it arrives via the next rc - assuming that > > would be the flow from upstream pov? > > > > I expect it to. It's currently in the akpm/mm.git branch > mm/mm-hotfixes-unstable where I expect it

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/slpc: Use platform limits for min/max frequency (rev5)

== Series Details == Series: drm/i915/slpc: Use platform limits for min/max frequency (rev5) URL : https://patchwork.freedesktop.org/series/109632/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109632v5_full

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Handle wopcm per-GT and limit calculations.

On 10/24/2022 15:26, Daniele Ceraolo Spurio wrote: From: Aravind Iddamsetty With MTL standalone media architecture the wopcm layout has changed, with separate partitioning in WOPCM for the root GT GuC and the media GT GuC. The size of WOPCM is 4MB with the lower 2MB reserved for the media GT

[Intel-gfx] ✓ Fi.CI.BAT: success for Delay disabling GuC scheduling of an idle context (rev2)

== Series Details == Series: Delay disabling GuC scheduling of an idle context (rev2) URL : https://patchwork.freedesktop.org/series/109466/ State : success == Summary == CI Bug Log - changes from CI_DRM_12295 -> Patchwork_109466v2 Summary

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/ttm: rework on ttm_resource to use size_t type

== Series Details == Series: drm/ttm: rework on ttm_resource to use size_t type URL : https://patchwork.freedesktop.org/series/110129/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_110129v1_full

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Delay disabling GuC scheduling of an idle context (rev2)

== Series Details == Series: Delay disabling GuC scheduling of an idle context (rev2) URL : https://patchwork.freedesktop.org/series/109466/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/display: Change terminology for cdclk actions

== Series Details == Series: series starting with [CI,1/4] drm/i915/display: Change terminology for cdclk actions URL : https://patchwork.freedesktop.org/series/110145/ State : success == Summary == CI Bug Log - changes from CI_DRM_12295 -> Patchwork_110145v1

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix Guc-Err-Capture sizing warning (rev2)

== Series Details == Series: Fix Guc-Err-Capture sizing warning (rev2) URL : https://patchwork.freedesktop.org/series/109439/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/109439/revisions/2/mbox/ not applied Applying: drm/i915/guc: Fix GuC

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/kms: Stop registering multiple /sys/class/backlight devs for a single display (rev4)

== Series Details == Series: drm/kms: Stop registering multiple /sys/class/backlight devs for a single display (rev4) URL : https://patchwork.freedesktop.org/series/107755/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/107755/revisions/4/mbox/

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

Hi Ashutosh, > On Tue, 25 Oct 2022 02:25:06 -0700, Andi Shyti wrote: > > > > Hi Ashutosh, > > Hi Andi :) > > > > > If a non-constant variable is used as the first argument of the > > > > FIELD_PREP > > > > macro, a build error occurs when using the clang compiler. > > A "non-constant

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm/i915/display: Change terminology for cdclk actions

== Series Details == Series: series starting with [CI,1/4] drm/i915/display: Change terminology for cdclk actions URL : https://patchwork.freedesktop.org/series/110145/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

On Wed, Oct 26, 2022 at 01:27:25AM +0200, Hans de Goede wrote: > this code should actually set the ACPI_VIDEO_BACKLIGHT flag: > drivers/acpi/scan.c: > > static acpi_status > acpi_backlight_cap_match(acpi_handle handle, u32 level, void *context, > void **return_value) >

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: stop abusing swiotlb_max_segment (rev6)

== Series Details == Series: drm/i915: stop abusing swiotlb_max_segment (rev6) URL : https://patchwork.freedesktop.org/series/109946/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109946v6_full

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

Hi, On 10/25/22 22:40, Matthew Garrett wrote: > On Tue, Oct 25, 2022 at 10:25:33PM +0200, Hans de Goede wrote: > >> Having the native driver come and then go and be replaced >> with the vendor driver would also be quite inconvenient >> for these planned changes. > > I understand that it would

[Intel-gfx] [CI 4/4] drm/i915/display: Move squash_ctl register programming to its own function

No functional change. Introduce dg2_cdclk_squash_program and move squash_ctl register programming bits to this. v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani) Cc: Jani Nikula Cc: Balasubramani Vivekanandan Cc: Ville Syrjälä Signed-off-by: Anusha Srivatsa Reviewed-by:

[Intel-gfx] [CI 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

No functional change. Moving segments out to simplify bxt_set_cdlck() v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani) Cc: Jani Nikula Cc: Balasubramani Vivekanandan Cc: Ville Syrjälä Signed-off-by: Anusha Srivatsa Reviewed-by: Balasubramani Vivekanandan ---

[Intel-gfx] [CI 1/4] drm/i915/display: Change terminology for cdclk actions

No functional changes. Changing terminology in some print statements. s/has_cdclk_squasher/has_cdclk_squash, s/crawler/crawl and s/squasher/squash. Cc: Balasubramani Vivekanandan Cc: Ville Syrjälä Signed-off-by: Anusha Srivatsa Reviewed-by: Balasubramani Vivekanandan ---

[Intel-gfx] [CI 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

Driver had discrepancy in how cdclk squash and crawl support were checked. Like crawl, add squash as a 1 bit feature flag to the display section of DG2. Cc: Balasubramani Vivekanandan Cc: Ville Syrjälä Signed-off-by: Anusha Srivatsa Reviewed-by: Balasubramani Vivekanandan ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Optmize waitboost for SLPC (rev7)

== Series Details == Series: drm/i915/slpc: Optmize waitboost for SLPC (rev7) URL : https://patchwork.freedesktop.org/series/109840/ State : success == Summary == CI Bug Log - changes from CI_DRM_12294 -> Patchwork_109840v7 Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for Add DG2 OA support (rev10)

== Series Details == Series: Add DG2 OA support (rev10) URL : https://patchwork.freedesktop.org/series/107584/ State : success == Summary == CI Bug Log - changes from CI_DRM_12294 -> Patchwork_107584v10 Summary --- **SUCCESS** No

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/xelp: Add Wa_1806527549 (rev2)

On Thu, Oct 20, 2022 at 01:00:27AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/xelp: Add Wa_1806527549 (rev2) > URL : https://patchwork.freedesktop.org/series/109885/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_12261_full ->

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Prep work for finishing (de)gamma readout (rev3)

== Series Details == Series: drm/i915: Prep work for finishing (de)gamma readout (rev3) URL : https://patchwork.freedesktop.org/series/109229/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109229v3_full

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DG2 OA support (rev10)

== Series Details == Series: Add DG2 OA support (rev10) URL : https://patchwork.freedesktop.org/series/107584/ State : warning == Summary == Error: dim checkpatch failed f49ce1a759c5 drm/i915/perf: Fix OA filtering logic for GuC mode 5e811f8d8045 drm/i915/perf: Add 32-bit OAG and OAR formats

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix CFI violations in gt_sysfs (rev5)

== Series Details == Series: drm/i915: Fix CFI violations in gt_sysfs (rev5) URL : https://patchwork.freedesktop.org/series/108917/ State : success == Summary == CI Bug Log - changes from CI_DRM_12294 -> Patchwork_108917v5 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix CFI violations in gt_sysfs (rev5)

== Series Details == Series: drm/i915: Fix CFI violations in gt_sysfs (rev5) URL : https://patchwork.freedesktop.org/series/108917/ State : warning == Summary == Error: dim checkpatch failed e2d4c2e70109 drm/i915: Fix CFI violations in gt_sysfs -:125: CHECK:LINE_SPACING: Please use a blank

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/kms: Stop registering multiple /sys/class/backlight devs for a single display (rev3)

== Series Details == Series: drm/kms: Stop registering multiple /sys/class/backlight devs for a single display (rev3) URL : https://patchwork.freedesktop.org/series/107755/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/107755/revisions/3/mbox/

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Connect VFIO to IOMMUFD

== Series Details == Series: Connect VFIO to IOMMUFD URL : https://patchwork.freedesktop.org/series/110133/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/110133/revisions/1/mbox/ not applied Applying: vfio: Move vfio_device driver open/close

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

On Tue, Oct 25, 2022 at 10:25:33PM +0200, Hans de Goede wrote: > Having the native driver come and then go and be replaced > with the vendor driver would also be quite inconvenient > for these planned changes. I understand that it would be inconvenient, but you've broken existing working

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

Hi (again), On 10/25/22 22:25, Hans de Goede wrote: > Hi Matthew, > > On 10/25/22 21:32, Matthew Garrett wrote: >> On Tue, Oct 25, 2022 at 08:50:54PM +0200, Hans de Goede wrote: >> >>> That is a valid point, but keep in mind that this is only used on ACPI >>> platforms and then only on devices

Re: [Intel-gfx] [PATCH] drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

On Tue, Oct 25, 2022 at 08:47:32PM +0300, Jani Nikula wrote: > On Tue, 25 Oct 2022, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > If we can't dig out a fixed mode for LVDS from the VBT or EDID > > let's fall back to using the current output timings. This should > > work as long as the

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

Hi Matthew, On 10/25/22 21:32, Matthew Garrett wrote: > On Tue, Oct 25, 2022 at 08:50:54PM +0200, Hans de Goede wrote: > >> That is a valid point, but keep in mind that this is only used on ACPI >> platforms and then only on devices with a builtin LCD panel and then >> only by GPU drivers which

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/display: Change terminology for cdclk actions

== Series Details == Series: series starting with [1/4] drm/i915/display: Change terminology for cdclk actions URL : https://patchwork.freedesktop.org/series/110135/ State : success == Summary == CI Bug Log - changes from CI_DRM_12294 -> Patchwork_110135v1

[Intel-gfx] [PATCH v5 09/16] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers

User passes uabi engine class and instance to the perf OA interface. Use gt corresponding to the engine to pin the buffers to the right ggtt. Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 21 +++-- 1 file changed, 19

[Intel-gfx] [PATCH v5 01/16] drm/i915/perf: Fix OA filtering logic for GuC mode

With GuC mode of submission, GuC is in control of defining the context id field that is part of the OA reports. To filter reports, UMD and KMD must know what sw context id was chosen by GuC. There is not interface between KMD and GuC to determine this, so read the upper-dword of EXECLIST_STATUS to

[Intel-gfx] [PATCH v5 11/16] drm/i915/perf: Add Wa_1508761755:dg2

Disable Clock gating in EU when gathering the events so that EU events are not lost. v2: Fix checkpatch issues v3: User MCR helpers to write to MC reg Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +

[Intel-gfx] [PATCH v5 08/16] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops

With multi-gt, user can access multiple OA buffers concurrently. Use stream->lock instead of gt->perf.lock to serialize file operations. Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_perf.c | 31 --

[Intel-gfx] [PATCH v5 15/16] drm/i915/perf: complete programming whitelisting for XEHPSDV

From: Lionel Landwerlin We have an additional register to select which slices contribute to OAG/OAG counter increments. Signed-off-by: Lionel Landwerlin Signed-off-by: Matt Roper Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_drv.h | 2 ++

[Intel-gfx] [PATCH v5 14/16] drm/i915/guc: Support OA when Wa_16011777198 is enabled

From: Vinay Belgaumkar On DG2, a w/a resets RCS/CCS before it goes into RC6. This breaks OA since OA does not expect engine resets during its use. Fix it by disabling RC6. v2: (Ashutosh) - Bring back slpc_unset_param helper - Update commit msg - Use with_intel_runtime_pm helper for set/unset

[Intel-gfx] [PATCH v5 16/16] drm/i915/perf: Enable OA for DG2

OA was disabled for DG2 as support was missing. Enable it back now. Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_perf.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c

[Intel-gfx] [PATCH v5 05/16] drm/i915/perf: Enable bytes per clock reporting in OA

XEHPSDV and DG2 provide a way to configure bytes per clock vs commands per clock reporting. Enable bytes per clock setting on enabling OA. Bspec: 51762 Bspec: 52201 v2: - Fix commit msg (Ashutosh) - Fix checkpatch issues v3: - s/commands/bytes/ in code comment and commmit msg Signed-off-by:

[Intel-gfx] [PATCH v5 06/16] drm/i915/perf: Simply use stream->ctx

Earlier code used exclusive_stream to check for user passed context. Simplify this by accessing stream->ctx. Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH v5 04/16] drm/i915/perf: Determine gen12 oa ctx offset at runtime

Some SKUs of same gen12 platform may have different oactxctrl offsets. For gen12, determine oactxctrl offsets at runtime. v2: (Lionel) - Move MI definitions to intel_gpu_commands.h - Ensure __find_reg_in_lri does read past context image size v3: (Ashutosh) - Drop unnecessary use of double

[Intel-gfx] [PATCH v5 07/16] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf

Make perf part of gt as the OAG buffer is specific to a gt. The refactor eventually simplifies programming the right OA buffer and the right HW registers when supporting multiple gts. Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Lionel Landwerlin Reviewed-by: Ashutosh Dixit ---

[Intel-gfx] [PATCH v5 10/16] drm/i915/perf: Store a pointer to oa_format in oa_buffer

DG2 introduces OA reports with 64 bit report header fields. Perf OA would need more information about the OA format in order to process such reports. Store all OA format info in oa_buffer instead of just the size and format-id. v2: Drop format_size variable (Ashutosh) Signed-off-by: Umesh

[Intel-gfx] [PATCH v5 13/16] drm/i915/perf: Save/restore EU flex counters across reset

If a drm client is killed, then hw contexts used by the client are reset immediately. This reset clears the EU flex counter configuration. If an OA use case is running in parallel, it would start seeing zeroed eu counter values following the reset even if the drm client is restarted. Save/restore

[Intel-gfx] [PATCH v5 12/16] drm/i915/perf: Apply Wa_18013179988

OA reports in the OA buffer contain an OA timestamp field that helps user calculate delta between 2 OA reports. The calculation relies on the CS timestamp frequency to convert the timestamp value to nanoseconds. The CS timestamp frequency is a function of the CTC_SHIFT value in RPM_CONFIG0. In

[Intel-gfx] [PATCH v5 03/16] drm/i915/perf: Fix noa wait predication for DG2

Predication for batch buffer commands changed in XEHPSDV. MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT register. The MI_SET_PREDICATE_RESULT register can only be modified with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE command sets MI_SET_PREDICATE_RESULT

[Intel-gfx] [PATCH v5 02/16] drm/i915/perf: Add 32-bit OAG and OAR formats for DG2

Add new OA formats for DG2. MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893 v2: - Update commit title (Ashutosh) - Coding style fixes (Lionel) - 64 bit OA formats need UMD changes in GPUvis, drop for now and send in a separate series with UMD changes v3: - Update commit

[Intel-gfx] [PATCH v5 00/16] Add DG2 OA support

Add OA format support for DG2 and various fixes for DG2. This series has 2 uapi changes listed below: 1) drm/i915/perf: Add OAG and OAR formats for DG2 DG2 has new OA formats defined that can be selected by the user. The UMD changes that are consumed by GPUvis are:

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)

== Series Details == Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) URL : https://patchwork.freedesktop.org/series/109963/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/display: Change terminology for cdclk actions

== Series Details == Series: series starting with [1/4] drm/i915/display: Change terminology for cdclk actions URL : https://patchwork.freedesktop.org/series/110135/ State : warning == Summary == Error: dim checkpatch failed 4061a06bfea9 drm/i915/display: Change terminology for cdclk actions

[Intel-gfx] [PATCH v3] drm/i915: Fix CFI violations in gt_sysfs

From: Nathan Chancellor When booting with CONFIG_CFI_CLANG, there are numerous violations when accessing the files under /sys/devices/pci:00/:00:02.0/drm/card0/gt/gt0: $ cd /sys/devices/pci:00/:00:02.0/drm/card0/gt/gt0 $ grep . * id:0 punit_req_freq_mhz:350

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/slpc: Optmize waitboost for SLPC (rev6)

== Series Details == Series: drm/i915/slpc: Optmize waitboost for SLPC (rev6) URL : https://patchwork.freedesktop.org/series/109840/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12294 -> Patchwork_109840v6 Summary ---

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

On Tue, Oct 25, 2022 at 08:50:54PM +0200, Hans de Goede wrote: > That is a valid point, but keep in mind that this is only used on ACPI > platforms and then only on devices with a builtin LCD panel and then > only by GPU drivers which actually call acpi_video_get_backlight_type(), > so e.g. not

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

Regression failures are related to https://gitlab.freedesktop.org/drm/intel/-/issues/7311 Re-reported. Lakshmi. -Original Message- From: Auld, Matthew Sent: Tuesday, October 25, 2022 2:09 AM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana Subject: Re: ✗ Fi.CI.BAT: failure

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978

== Series Details == Series: series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978 URL : https://patchwork.freedesktop.org/series/110131/ State : success == Summary == CI Bug Log - changes from CI_DRM_12294 -> Patchwork_110131v1

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

Hi, On 10/24/22 22:30, Matthew Garrett wrote: > On Tue, Sep 27, 2022 at 01:04:52PM +0200, Hans de Goede wrote: > >> So to fix this we need to make acpi_video_get_backlight_type() >> return native on the Acer Chromebook Spin 713. > > Isn't the issue broader than that? Unless the platform is

[Intel-gfx] [PATCH 09/10] vfio: Make vfio_container optionally compiled

Add a kconfig CONFIG_VFIO_CONTAINER that controls compiling the container code. If 'n' then only iommufd will provide the container service. All the support for vfio iommu drivers, including type1, will not be built. This allows a compilation check that no inappropriate dependencies between the

[Intel-gfx] [PATCH 06/10] vfio-iommufd: Allow iommufd to be used in place of a container fd

This makes VFIO_GROUP_SET_CONTAINER accept both a vfio container FD and an iommufd. In iommufd mode an IOAS will exist after the SET_CONTAINER, but it will not be attached to any groups. >From a VFIO perspective this means that the VFIO_GROUP_GET_STATUS and VFIO_GROUP_FLAGS_VIABLE works subtly

[Intel-gfx] [PATCH 07/10] vfio-iommufd: Support iommufd for physical VFIO devices

This creates the iommufd_device for the physical VFIO drivers. These are all the drivers that are calling vfio_register_group_dev() and expect the type1 code to setup a real iommu_domain against their parent struct device. The design gives the driver a choice in how it gets connected to iommufd

[Intel-gfx] [PATCH 08/10] vfio-iommufd: Support iommufd for emulated VFIO devices

Emulated VFIO devices are calling vfio_register_emulated_iommu_dev() and consist of all the mdev drivers. Like the physical drivers, support for iommufd is provided by the driver supplying the correct correct standard ops. Provide ops from the core that duplicate what

[Intel-gfx] [PATCH 10/10] iommufd: Allow iommufd to supply /dev/vfio/vfio

If the VFIO container is compiled out, give a kconfig option for iommufd to provide the miscdev node with the same name and permissions as vfio uses. The compatibility node supports the same ioctls as VFIO and automatically enables the VFIO compatible pinned page accounting mode. Signed-off-by:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978

== Series Details == Series: series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978 URL : https://patchwork.freedesktop.org/series/110131/ State : warning == Summary == Error: dim checkpatch failed c5d85fb8644b drm/i915/dg2: Introduce Wa_18018764978 -:37:

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

On Tue, 25 Oct 2022 07:30:49 -0700, Jani Nikula wrote: > > On Tue, 25 Oct 2022, Jani Nikula wrote: > > On Tue, 25 Oct 2022, Gwan-gyeong Mun wrote: > >> If a non-constant variable is used as the first argument of the FIELD_PREP > >> macro, a build error occurs when using the clang compiler. > >>

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

On Tue, 25 Oct 2022 02:25:06 -0700, Andi Shyti wrote: > > Hi Ashutosh, Hi Andi :) > > > If a non-constant variable is used as the first argument of the FIELD_PREP > > > macro, a build error occurs when using the clang compiler. A "non-constant variable" does not seem to be the cause of the

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/uapi: expose GTT alignment"

== Series Details == Series: Revert "drm/i915/uapi: expose GTT alignment" URL : https://patchwork.freedesktop.org/series/110041/ State : success == Summary == CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1 Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

== Series Details == Series: drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode URL : https://patchwork.freedesktop.org/series/110130/ State : success == Summary == CI Bug Log - changes from CI_DRM_12294 -> Patchwork_110130v1

[Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

No functional change. Introduce dg2_cdclk_squash_program and move squash_ctl register programming bits to this. v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani) Cc: Jani Nikula Cc: Balasubramani Vivekanandan Cc: Ville Syrjälä Signed-off-by: Anusha Srivatsa Reviewed-by:

[Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

Driver had discrepancy in how cdclk squash and crawl support were checked. Like crawl, add squash as a 1 bit feature flag to the display section of DG2. Cc: Balasubramani Vivekanandan Cc: Ville Syrjälä Signed-off-by: Anusha Srivatsa Reviewed-by: Balasubramani Vivekanandan ---

[Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions

No functional changes. Changing terminology in some print statements. s/has_cdclk_squasher/has_cdclk_squash, s/crawler/crawl and s/squasher/squash. Cc: Balasubramani Vivekanandan Cc: Ville Syrjälä Signed-off-by: Anusha Srivatsa Reviewed-by: Balasubramani Vivekanandan ---

[Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

No functional change. Moving segments out to simplify bxt_set_cdlck() v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani) Cc: Jani Nikula Cc: Balasubramani Vivekanandan Cc: Ville Syrjälä Signed-off-by: Anusha Srivatsa Reviewed-by: Balasubramani Vivekanandan ---

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: EDID override refactoring and fixes (rev3)

== Series Details == Series: drm/edid: EDID override refactoring and fixes (rev3) URL : https://patchwork.freedesktop.org/series/109579/ State : success == Summary == CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109579v3_full

[Intel-gfx] [PATCH 01/10] vfio: Move vfio_device driver open/close code to a function

This error unwind is getting complicated. Move all the code into two pair'd function. The functions should be called when the open_count == 1 after incrementing/before decrementing. Signed-off-by: Jason Gunthorpe --- drivers/vfio/vfio_main.c | 95 ++-- 1 file

[Intel-gfx] [PATCH 00/10] Connect VFIO to IOMMUFD

This series provides an alternative container layer for VFIO implemented using iommufd. This is optional, if CONFIG_IOMMUFD is not set then it will not be compiled in. At this point iommufd can be injected by passing in a iommfd FD to VFIO_GROUP_SET_CONTAINER which will use the VFIO compat layer

[Intel-gfx] [PATCH 04/10] vfio: Move storage of allow_unsafe_interrupts to vfio_main.c

This legacy module knob has become uAPI, when set on the vfio_iommu_type1 it disables some security protections in the iommu drivers. Move the storage for this knob to vfio_main.c so that iommufd can access it too. Signed-off-by: Jason Gunthorpe --- drivers/vfio/vfio.h | 2 ++

[Intel-gfx] [PATCH 02/10] vfio: Move vfio_device_assign_container() into vfio_device_first_open()

The only thing this function does is assert the group has an assigned container and incrs refcounts. The overall model we have is that once a conatiner_users refcount is incremented it cannot be de-assigned from the group - vfio_group_ioctl_unset_container() will fail and the group FD cannot be

[Intel-gfx] [PATCH 03/10] vfio: Rename vfio_device_assign/unassign_container()

These functions don't really assign anything anymore, they just increment some refcounts and do a sanity check. Call them vfio_group_[un]use_container() Signed-off-by: Jason Gunthorpe --- drivers/vfio/container.c | 14 ++ drivers/vfio/vfio.h | 4 ++-- drivers/vfio/vfio_main.c

[Intel-gfx] [PATCH 05/10] vfio: Use IOMMU_CAP_ENFORCE_CACHE_COHERENCY for vfio_file_enforced_coherent()

iommufd doesn't establish the iommu_domains until after the device FD is opened, even if the container has been set. This design is part of moving away from the group centric iommu APIs. This is fine, except that the normal sequence of establishing the kvm wbindv won't work: group =

[Intel-gfx] [PATCH 1/2] drm/i915/dg2: Introduce Wa_18018764978

Wa_18018764978 applies to specific steppings of DG2 (G11 C0+, G11 and G12 A0+). Bspec: 66622 Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + 2 files changed, 8 insertions(+) diff --git

[Intel-gfx] [PATCH 2/2] drm/i915/dg2: Introduce Wa_18019271663

Wa_18019271663 applies to all DG2 steppings and skus. Bspec:45809 Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git

Re: [Intel-gfx] [PATCH] drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

On Tue, 25 Oct 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > If we can't dig out a fixed mode for LVDS from the VBT or EDID > let's fall back to using the current output timings. This should > work as long as the BIOS has (somehow) enabled the output. > > In this case we are dealing with

Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

On 21.10.2022 14:39, Anusha Srivatsa wrote: > No functional change. Introduce dg2_cdclk_squash_program and > move squash_ctl register programming bits to this. > > v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani) > > Cc: Jani Nikula > Cc: Balasubramani Vivekanandan > Cc:

Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

On 21.10.2022 14:39, Anusha Srivatsa wrote: > No functional change. Moving segments out to simplify > bxt_set_cdlck() > > v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani) > > Cc: Jani Nikula > Cc: Balasubramani Vivekanandan > Cc: Ville Syrjälä > Signed-off-by: Anusha Srivatsa > --- >

Re: [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

On 21.10.2022 14:39, Anusha Srivatsa wrote: > Driver had discrepancy in how cdclk squash and crawl support > were checked. Like crawl, add squash as a 1 bit feature flag > to the display section of DG2. > > Cc: Balasubramani Vivekanandan > Cc: Ville Syrjälä > Signed-off-by: Anusha Srivatsa >

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions

On 21.10.2022 14:39, Anusha Srivatsa wrote: > No functional changes. Changing terminolgy in some > print statements. s/has_cdclk_squasher/has_cdclk_squash, > s/crawler/crawl and s/squasher/squash. > > Cc: Balasubramani Vivekanandan > Cc: Ville Syrjälä > Signed-off-by: Anusha Srivatsa > --- >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Use platform limits for min/max frequency (rev5)

== Series Details == Series: drm/i915/slpc: Use platform limits for min/max frequency (rev5) URL : https://patchwork.freedesktop.org/series/109632/ State : success == Summary == CI Bug Log - changes from CI_DRM_12293 -> Patchwork_109632v5

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes for MTL (rev11)

On Mon, 24 Oct 2022 18:25:06 -0700, Patchwork wrote: > Hi Lakshmi, The below failures are unrelated to this series. Thanks. -- Ashutosh > Patch Details > > Series: i915: CAGF and RC6 changes for MTL (rev11) > URL: https://patchwork.freedesktop.org/series/108156/ > State: failure >

[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

== Series Details == Series: Revert "drm/i915/uapi: expose GTT alignment" URL : https://patchwork.freedesktop.org/series/110041/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1 Summary ---

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

On 25/10/2022 17:37, Patchwork wrote: *Patch Details* *Series:* Revert "drm/i915/uapi: expose GTT alignment" *URL:* https://patchwork.freedesktop.org/series/110041/ *State:*failure *Details:*

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/slpc: Use platform limits for min/max frequency (rev5)

== Series Details == Series: drm/i915/slpc: Use platform limits for min/max frequency (rev5) URL : https://patchwork.freedesktop.org/series/109632/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH] drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

From: Ville Syrjälä If we can't dig out a fixed mode for LVDS from the VBT or EDID let's fall back to using the current output timings. This should work as long as the BIOS has (somehow) enabled the output. In this case we are dealing with the some kind of BLB based POS machine (Toshiba SurePOS

Re: [Intel-gfx] [PATCH v2] drm/ttm: rework on ttm_resource to use size_t type

On Tue, 25 Oct 2022 at 16:51, Somalapuram Amaranath wrote: > > Change ttm_resource structure from num_pages to size_t size in bytes. > v1 -> v2: change PFN_UP(dst_mem->size) to ttm->num_pages > v1 -> v2: change bo->resource->size to bo->base.size at some places > v1 -> v2: remove the local

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

Start of lore thread for context: https://lore.kernel.org/intel-gfx/20221024210953.1572998-1-gwan-gyeong@intel.com/ On Tue, Oct 25, 2022 at 2:25 AM Andi Shyti wrote: > > Hi Ashutosh, > > > > drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of > > > constant

[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

== Series Details == Series: Revert "drm/i915/uapi: expose GTT alignment" URL : https://patchwork.freedesktop.org/series/110041/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1 Summary ---

Re: [Intel-gfx] [PATCH v2] drm/ttm: rework on ttm_resource to use size_t type

Am 25.10.22 um 17:50 schrieb Somalapuram Amaranath: Change ttm_resource structure from num_pages to size_t size in bytes. v1 -> v2: change PFN_UP(dst_mem->size) to ttm->num_pages v1 -> v2: change bo->resource->size to bo->base.size at some places v1 -> v2: remove the local variable v1 -> v2:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/ttm: rework on ttm_resource to use size_t type

== Series Details == Series: drm/ttm: rework on ttm_resource to use size_t type URL : https://patchwork.freedesktop.org/series/110129/ State : success == Summary == CI Bug Log - changes from CI_DRM_12293 -> Patchwork_110129v1 Summary

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/ttm: rework on ttm_resource to use size_t type

== Series Details == Series: drm/ttm: rework on ttm_resource to use size_t type URL : https://patchwork.freedesktop.org/series/110129/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

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