From: Tvrtko Ursulin
Some libdrmclient operations require that inactive clients are last in the
list. Rather than relying on callers of the library sort routine to
implement their comparison callbacks correctly, enforce this order
directly in the library and let callers comparison callbacks
From: Tvrtko Ursulin
Require DRM minor match during client lookup.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
index b837450301dc..06b66fe95b62 100644
From: Tvrtko Ursulin
Instead of hard coding the engine names, allow a map of names to indices
to either be passed in or it gets auto-detected (less efficient) while
parsing.
---
lib/igt_drm_clients.c | 18 ---
lib/igt_drm_clients.h | 3 ++-
lib/igt_drm_fdinfo.c| 51
From: Tvrtko Ursulin
Extract some code into a new library to prepare for further work towards
making a vendor agnostic gputop tool.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 471 +++
lib/igt_drm_clients.h | 89 +++
lib/meson.build |
From: Tvrtko Ursulin
Prepare for supporting clients belonging to multiple DRM cards by storing
the DRM minor in the client record.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 22 ++
lib/igt_drm_clients.h | 1 +
2 files changed, 15 insertions(+), 8
From: Tvrtko Ursulin
This is a pile of patches which implements a rudimentary vendor agnostic gputop
tool based of the new DRM spec as documented in
Documentation/gpu/drm-usage-stats.rst.
First part of the series is code refactoring which should be reasonably stable.
I've tested it all while
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_dp_link_training.c | 62 +--
1 file changed, 44
On Mon, 17 Apr 2023, "Kandpal, Suraj" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Monday, April 17, 2023 4:04 PM
>> To: Kandpal, Suraj ; intel-
>> g...@lists.freedesktop.org
>> Subject: RE: [Intel-gfx] [PATCH v2] drm/i915/display: Increase AUX timeout
>> for Type-C
>>
>>
> -Original Message-
> From: Jani Nikula
> Sent: Monday, April 17, 2023 4:04 PM
> To: Kandpal, Suraj ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH v2] drm/i915/display: Increase AUX timeout
> for Type-C
>
> On Mon, 17 Apr 2023, "Kandpal, Suraj" wrote:
> >>
kmap() s been deprecated in favor of kmap_local_page().
There are two main problems with kmap(): (1) It comes with an overhead as
mapping space is restricted and protected by a global lock for
synchronization and (2) it also requires global TLB invalidation when the
kmap’s pool wraps and it might
kmap() s been deprecated in favor of kmap_local_page().
There are two main problems with kmap(): (1) It comes with an overhead as
mapping space is restricted and protected by a global lock for
synchronization and (2) it also requires global TLB invalidation when the
kmap’s pool wraps and it might
kmap() has been deprecated in favor of kmap_local_page().
There are two main problems with kmap(): (1) It comes with an overhead as
mapping space is restricted and protected by a global lock for
synchronization and (2) it also requires global TLB invalidation when the
kmap’s pool wraps and it
kmap() has been deprecated in favor of kmap_local_page().
There are two main problems with kmap(): (1) It comes with an overhead as
mapping space is restricted and protected by a global lock for
synchronization and (2) it also requires global TLB invalidation when the
kmap’s pool wraps and it
On Mon, 17 Apr 2023, "Kandpal, Suraj" wrote:
>> On Wed, 05 Apr 2023, Suraj Kandpal wrote:
>> > Type-C PHYs are taking longer than expected for Aux IO Power Enabling.
>> > Workaround: Increase the timeout.
>> >
>> > WA_14017248603: adlp
>> > Bspec: 55480
>> >
>> > ---v2
>> > -change style on how
On Mon, 17 Apr 2023, Jani Nikula wrote:
> On Mon, 17 Apr 2023, Arun R Murthy wrote:
>> For 128b/132b LT prior to LT DPTX should set power state, DP channel
>> coding and then link rate.
>>
>> Signed-off-by: Arun R Murthy
>> ---
>> .../drm/i915/display/intel_dp_link_training.c | 52
On Mon, 17 Apr 2023, Arun R Murthy wrote:
> For 128b/132b LT prior to LT DPTX should set power state, DP channel
> coding and then link rate.
>
> Signed-off-by: Arun R Murthy
> ---
> .../drm/i915/display/intel_dp_link_training.c | 52 +--
> 1 file changed, 35 insertions(+), 17
> On Wed, 05 Apr 2023, Suraj Kandpal wrote:
> > Type-C PHYs are taking longer than expected for Aux IO Power Enabling.
> > Workaround: Increase the timeout.
> >
> > WA_14017248603: adlp
> > Bspec: 55480
> >
> > ---v2
> > -change style on how we mention WA [Ankit] -fix bat error
> >
> >
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_dp_link_training.c | 52 +--
1 file changed, 35 insertions(+), 17 deletions(-)
diff --git
On Fri, 14 Apr 2023, Jani Nikula wrote:
> v2 of https://patchwork.freedesktop.org/series/116431/ with the minor
> review comments addressed.
Thanks for the reviews, pushed to drm-intel-next.
BR,
Jani.
>
> BR,
> Jani.
>
> Jani Nikula (10):
> drm/i915/display: remove
Hi Jani,
On Mon, Apr 17, 2023 at 11:57:42AM +0300, Jani Nikula wrote:
> Use rmw where needed.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Andi Shyti
Andi
Use rmw where needed.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_pps.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 7f9926672a6a..4f0b0cca03cc 100644
On Wed, 05 Apr 2023, Suraj Kandpal wrote:
> Type-C PHYs are taking longer than expected for Aux IO Power Enabling.
> Workaround: Increase the timeout.
>
> WA_14017248603: adlp
> Bspec: 55480
>
> ---v2
> -change style on how we mention WA [Ankit]
> -fix bat error
>
> Signed-off-by: Suraj Kandpal
Hi
On 4/14/23 12:11, Christian König wrote:
Am 13.04.23 um 15:13 schrieb Daniel Vetter:
On Thu, 13 Apr 2023 at 11:46, Christian König
wrote:
Am 13.04.23 um 10:48 schrieb Daniel Vetter:
On Wed, 12 Apr 2023 at 16:18, Christian König
wrote:
Am 12.04.23 um 11:08 schrieb Daniel Vetter:
On
> -Original Message-
> From: Kandpal, Suraj
> Sent: Monday, April 17, 2023 12:21 PM
> To: Murthy, Arun R ; intel-
> g...@lists.freedesktop.org
> Cc: Sharma, Swati2
> Subject: RE: [PATCH v2] drm/i915/display: Increase AUX timeout for Type-C
>
> : RE: [PATCH v2] drm/i915/display: Increase
: RE: [PATCH v2] drm/i915/display: Increase AUX timeout for Type-C
>
> > -Original Message-
> > From: Kandpal, Suraj
> > Sent: Wednesday, April 5, 2023 12:50 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Murthy, Arun R ; Sharma, Swati2
> > ; Kandpal, Suraj
> > Subject: [PATCH v2]
> fei.y...@intel.com kirjoitti 17.4.2023 klo 9.24:
>> From: Fei Yang
>>
>> The series includes patches needed to enable MTL.
>> Also add new extension for GEM_CREATE uAPI to let user space set cache
>> policy for buffer objects.
>
> if I'm counting right, this would be version 5 of the series,
fei.y...@intel.com kirjoitti 17.4.2023 klo 9.24:
From: Fei Yang
The series includes patches needed to enable MTL.
Also add new extension for GEM_CREATE uAPI to let
user space set cache policy for buffer objects.
if I'm counting right, this would be version 5 of the series, yet that
is not
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent,
From: Fei Yang
The series includes patches needed to enable MTL.
Also add new extension for GEM_CREATE uAPI to let
user space set cache policy for buffer objects.
Fei Yang (7):
drm/i915/mtl: Set has_llc=0
drm/i915/mtl: Add PTE encode function
drm/i915/mtl: workaround coherency issue for
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by
From: Madhumitha Tolakanahalli Pradeep
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for L4 cache calls a
MOCS/PAT table update.
Alos the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8. This
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out its life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
PTE encode functions are platform dependent. This patch implements
PTE functions for MTL, and ensures the correct PTE encode function
is used by calling pte_encode function pointer instead of the
hardcoded gen8 version of PTE encode.
Signed-off-by: Fei Yang
---
From: Fei Yang
On MTL, GT is no longer allocated on LLC, set has_llc=0.
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cddb6e197972..025d32c0b161 100644
---
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line.
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