> From: Alex Williamson
> Sent: Wednesday, April 19, 2023 2:39 AM
>
> On Tue, 18 Apr 2023 09:57:32 -0300
> Jason Gunthorpe wrote:
>
> > On Mon, Apr 17, 2023 at 02:06:42PM -0600, Alex Williamson wrote:
> > > On Mon, 17 Apr 2023 16:31:56 -0300
> > > Jason Gunthorpe wrote:
> > >
> > > > On Mon,
On Wed, Apr 19, 2023 at 06:34:00PM +0300, Jani Nikula wrote:
> On Tue, 18 Apr 2023, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Define and use the bitmasks for the x/y components
> > of the ilk+ panel filter window pos/size registers.
>
> This reduces the field sizes by 3-4 bits. Maybe
== Series Details ==
Series: drm/i915/mtl: Add workaround 14018778641
URL : https://patchwork.freedesktop.org/series/116750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13033 -> Patchwork_116750v1
Summary
---
On 4/20/2023 1:21 PM, Tejas Upadhyay wrote:
WA 18018781329 is applicable now across all MTL
steppings.
Cc: Matt Roper
Signed-off-by: Tejas Upadhyay
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +---
1 file changed, 13 insertions(+), 7
On Tue, 18 Apr 2023, Rodrigo Vivi wrote:
> On Mon, Apr 17, 2023 at 06:37:41PM +0300, Jani Nikula wrote:
>> An error-valued pointer can handle all in one without the wrapper
>> struct.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_crt.c | 18
://download.01.org/0day-ci/archive/20230420/202304201909.d57x63j5-...@intel.com/config)
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line.
Hi Fei,
> To comply with the design that buffer objects shall have immutable
> cache setting through out their life cycle, {set, get}_caching ioctl's
> are no longer supported from MTL onward. With that change caching
> policy can only be set at object creation time. The current code
> applies a
This is a important fix and can be pushed without depending on this series.
I will send this out to mailing list separately for CI.
Regards,
Nirmoy
On 4/20/2023 1:00 AM, fei.y...@intel.com wrote:
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by
== Series Details ==
Series: drm/i915/mtl: Set has_llc=0
URL : https://patchwork.freedesktop.org/series/116747/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13033 -> Patchwork_116747v1
Summary
---
**SUCCESS**
No
Hi Fei,
On Wed, Apr 19, 2023 at 04:00:50PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> The series includes patches needed to enable MTL.
> Also add new extension for GEM_CREATE uAPI to let
> user space set cache policy for buffer objects.
>
> v2: addressing review comments and
WA 18018781329 is applicable now across all MTL
steppings.
Cc: Matt Roper
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
On Tue, 18 Apr 2023, "Teres Alexis, Alan Previn"
wrote:
> On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
>> From: Alexander Usyskin
>>
>> GSC Proxy component is used for communication between the
>> Intel graphics driver and MEI driver.
>
>
>
>> diff --git
On Wed, 19 Apr 2023, Ville Syrjälä wrote:
> On Wed, Apr 19, 2023 at 02:54:49PM +0300, Jani Nikula wrote:
>> The declaration was removed earlier, but got accidentally resurrected in
>> i915xx_wm.[ch] refactoring. Remove harder.
>
> i9xx_wm
I was going to fix that while pushing, but got distracted
From: Fei Yang
On MTL, LLC is not shared between GT and CPU, set has_llc=0.
Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git
We have multiple bugs that requires this and it can be picked up
irrespective of this series. I have sent a trybot patch for this and
once that passes, I will push this one.
https://patchwork.freedesktop.org/series/116746/
Nirmoy
On 4/20/2023 1:00 AM, fei.y...@intel.com wrote:
From: Fei
On 20.04.2023 01:00, fei.y...@intel.com wrote:
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In
On 20.04.2023 01:00, fei.y...@intel.com wrote:
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes
ay-dc-link-link_validation.c:warning:variable-link-set-but-not-used
|-- alpha-randconfig-r001-20230420
| |--
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used
| |--
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warni
Hi Dave and Daniel,
this is this week's PR for drm-misc-fixes.
Best regards
Thomas
drm-misc-fixes-2023-04-20-2:
Short summary of fixes pull:
* nouveau: fix dma-resv timeout
* rockchip: fix suspend/resume
* sched: fix timeout handling
The following changes since commit
On 20.04.2023 01:00, fei.y...@intel.com wrote:
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to
Hi Dave & Daniel,
Here's another drm-intel-next-fixes pull request.
One Cc stable CSC plane index fix, then MST PLL fix and smaller
null/oob/leak fixes.
Regards, Joonas
***
drm-intel-next-fixes-2023-04-20-1:
Active port PLL MST fix for second stream, CSC plane index fix,
null and oob array
On Tue, 2023-04-11 at 22:14 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Some cleanups around mostly PSR/related registers.
>
> v2: Improve the mask bit docs and rebase due to
> intel_psr_regs.h
For the whole set:
Reviewed-by: Jouni Högander
>
> Ville Syrjälä (8):
>
On 19/04/2023 23:10, Dixit, Ashutosh wrote:
On Wed, 19 Apr 2023 06:21:27 -0700, Tvrtko Ursulin wrote:
Hi Tvrtko,
On 10/04/2023 23:35, Ashutosh Dixit wrote:
Instead of erroring out when GuC reset is in progress, block waiting for
GuC reset to complete which is a more reasonable uapi
://download.01.org/0day-ci/archive/20230420/202304201512.cllnzi0u-...@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
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