== Series Details ==
Series: drm/i915/mtl: add PTE encode function (rev3)
URL : https://patchwork.freedesktop.org/series/116868/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13062 -> Patchwork_116868v3
Summary
---
*
== Series Details ==
Series: drm/i915/mtl: add PTE encode function (rev3)
URL : https://patchwork.freedesktop.org/series/116868/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent, ha
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a def
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by a
From: Fei Yang
The first three patches in this series are taken from
https://patchwork.freedesktop.org/series/116868/
These patches are included here because the last patch
has dependency on the pat_index refactor.
This series is focusing on uAPI changes,
1. end support for set caching ioctl [PA
From: Fei Yang
PTE encode is platform dependent. After replacing cache_level with
pat_index, the newly introduced mtl_pte_encode is actually generic
for all gen12 platforms, thus rename it to gen12_pte_encode and
apply it to all gen12 platforms.
Cc: Chris Wilson
Cc: Matt Roper
Signed-off-by: F
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent, ha
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by a
From: Fei Yang
PTE encode is platform dependent. After replacing cache_level with
pat_index, the newly introduced mtl_pte_encode is actually generic
for all gen12 platforms, thus rename it to gen12_pte_encode and
apply it to all gen12 platforms.
Cc: Chris Wilson
Cc: Matt Roper
Signed-off-by: F
From: Fei Yang
These patches are extracted from series
https://patchwork.freedesktop.org/series/115980/
This series refactor the cache policy programming so that the PTE
encode functions can be unified across all GEN12 platforms. This
refactor is also important in implementing the design which a
On 4/24/2023 6:34 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:13PM +0530, Ankit Nautiyal wrote:
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_for
Hey Dave, Daniel,
Complementary pull request for drm-misc-next-fixes!
~Maarten
drm-misc-next-fixes-2023-04-26:
drm-misc-next-fixes for v6.4-rc1:
- Revert uAPI from accel/qaic.
- Fix TTM build on archs where PMD_SHIFT is not constant.
- Improve error handling in nt35950.
- Fix double unregister
Hi Dave, Daniel,
drm-misc-fixes pull request for rc1. drm-misc-next-fixes coming up.. next
~Maarten
drm-misc-fixes-2023-04-26:
drm-misc-fixes for v6.4-rc1:
- Fix DSC macros.
- Fix VESA format for simplefb.
- Prohibit potential out-of-bounds access in generic fbdev emulation.
- Improve AST2500+
On 4/24/2023 6:21 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:08PM +0530, Ankit Nautiyal wrote:
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MS
On 4/24/2023 6:07 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:05PM +0530, Ankit Nautiyal wrote:
Start passing the sink_format, to all functions that take a bool
ycbcr420_output as parameter. This will make the functions generic,
and will serve as a slight step towards 4:2:2 support
Hi Ville,
Thanks for pointing out the issues and suggestions.
I agree with the suggested changes and corrections and will make the
changes in the next version.
Regards,
Ankit
On 4/24/2023 6:01 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:03PM +0530, Ankit Nautiyal wrote:
The dec
On 4/24/2023 6:16 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:02PM +0530, Ankit Nautiyal wrote:
New member to store the YCBCR20 Pass through capability of the DP sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
1 file changed, 1
== Series Details ==
Series: drm/i915/mtl: Implement Wa_14019141245 (rev2)
URL : https://patchwork.freedesktop.org/series/116939/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13062_full -> Patchwork_116939v2_full
Summary
-
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: f600e0bbde8562a06bee31b3eb1b69d49acac4c5 Add linux-next specific
files for 20230425
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202304102354.q4voxgte-...@intel.com
https
On 4/25/2023 6:40 PM, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* series starting with [v6,1/2] drm/i915/guc/slpc: Provide
sysfs for efficient freq
*URL:* https://patchwork.freedesktop.org/series/116957/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/guc/slpc: Provide sysfs for
efficient freq
URL : https://patchwork.freedesktop.org/series/116957/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13062 -> Patchwork_116957v1
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/guc/slpc: Provide sysfs for
efficient freq
URL : https://patchwork.freedesktop.org/series/116957/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked sepa
Use the new efficient frequency toggling interface. Also
create a helper function to restore the frequencies after
the test is done.
v2: Restore max freq first and then min.
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/selftest_slpc.c | 42 ++---
1 file change
SLPC enables use of efficient freq at init by default. It is
possible for GuC to request frequencies that are higher than
the 'software' max if user has set it lower than the efficient
level.
Scenarios/tests that require strict fixing of freq below the efficient
level will need to disable it throu
== Series Details ==
Series: mtl: add support for pmdemand (rev2)
URL : https://patchwork.freedesktop.org/series/116949/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13062 -> Patchwork_116949v2
Summary
---
**FAILURE
== Series Details ==
Series: mtl: add support for pmdemand (rev2)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: mtl: add support for pmdemand (rev2)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim checkpatch failed
5016f41822c8 drm/i915: fix the derating percentage for MTL
058a5643fd59 drm/i915: update the QGV point frequency c
== Series Details ==
Series: drm/i915/dsi: Use unconditional msleep() instead of intel_dsi_msleep()
URL : https://patchwork.freedesktop.org/series/116947/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13062 -> Patchwork_116947v1
== Series Details ==
Series: drm/i915/mtl: Implement Wa_14019141245 (rev2)
URL : https://patchwork.freedesktop.org/series/116939/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13062 -> Patchwork_116939v2
Summary
---
Hi Vinod,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Vinod-Govindapillai/drm-i915-fix-the-derating-percentage-for-MTL/20230426-043120
base: git://anongit.freedesktop.org/drm/drm-ti
Hi Vinod,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Vinod-Govindapillai/drm-i915-update-the-QGV-point-frequency-calculations/20230426-042322
base: git://anongit.freedesktop.org/dr
On Thu, Apr 20, 2023 at 03:40:46PM +0300, Mika Kahola wrote:
> From: Gustavo Sousa
>
> Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
> Interrupt registers. The bits for Type-C ports are defined in the PICA
> interrupt registers.
>
> BSpec: 50064
> Signed-off-by: Gustavo Sousa
While configuring pmdemand parameters, there could be
intel_get_crtc_new_encoder call where encoders could be 0. To avoid
invoking drm_warn in such cases, use a parameter to indicate drm_warn
should be suppressed.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_cx0_phy.
From: Mika Kahola
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file changed, 130 insertions(+), 105 deletions
MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.
Signed-off-by: Vinod Govindapillai
>From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i91
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 7 +--
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
pmdemand support patches for MTL
SAGV configuration support for MTL
v2: added one missing patch in the previous version
Mika Kahola (1):
drm/i915/mtl: Add support for PM DEMAND
Vinod Govindapillai (7):
drm/i915: fix the derating percentage for MTL
drm/i915: update the QGV point frequency
While configuring pmdemand parameters, there could be
intel_get_crtc_new_encoder call where encoders could be 0. To avoid
invoking drm_warn in such cases, use a parameter to indicate drm_warn
should be suppressed.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_cx0_phy.
From: Mika Kahola
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.
Signed-off-by: Vinod Govindapillai
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file changed, 130 insertions(+), 105 deletions
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 7 +--
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
>From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i91
pmdemand support patches for MTL
SAGV configuration support for MTL
Mika Kahola (1):
drm/i915/mtl: Add support for PM DEMAND
Vinod Govindapillai (6):
drm/i915: update the QGV point frequency calculations
drm/i915: store the peak bw per QGV point
drm/i915: extract intel_bw_check_qgv_point
From: John Harrison
Some MI_ instructions have changed (or are just new) for Gen12. So
update the decoder code to match.
Signed-off-by: John Harrison
---
lib/i915/intel_decode.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/lib/i915/intel_decode.c b/lib/i
From: John Harrison
The error capture decoder was reporting invalid errors in batch
buffers and getting confused about the prescence of the GuC CTB. So
fix those up.
Signed-off-by: John Harrison
John Harrison (2):
lib/intel_decode: Decode Gen12 ring/batch instructions correctly
tools/inte
From: John Harrison
The buffer decoding code doesn't cope well with unknown buffers. So
add an entry for the GuC CTB so that it gets decoded correctly.
Signed-off-by: John Harrison
---
tools/intel_error_decode.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/intel_error_decode.c b/t
On Thu, Apr 20, 2023 at 03:40:45PM +0300, Mika Kahola wrote:
> Readout hw state for Thunderbolt.
>
Reviewed-by: Radhakrishna Sripada
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2
Hi,
> Andrzej Hajda (7):
> lib/ref_tracker: add unlocked leak print helper
> lib/ref_tracker: improve printing stats
> lib/ref_tracker: add printing to memory buffer
> lib/ref_tracker: remove warnings in case of allocation failure
> drm/i915: Correct type of wakeref v
Hi John,
> Dan Carpenter pointed out that 'err' was not being set in the case
> where the GuC firmware version range check fails. Fix that.
>
> Note that while this is bug fix for a previous patch (see Fixes tag
is _a_ bug fix.
> below). It is an exceedingly low risk bug. The range check is
> a
The intel_dsi_msleep() helper skips sleeping if the MIPI-sequences have
a version of 3 or newer and the panel is in vid-mode.
This is based on the big comment around line 730 which starts with
"Panel enable/disable sequences from the VBT spec.", where
the "v3 video mode seq" column does not have a
On Thu, Apr 20, 2023 at 03:40:44PM +0300, Mika Kahola wrote:
> Enabling and disabling sequence for Thunderbolt PLL.
>
Bspec: 64568
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++-
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
drm/i915: Initialize dkl_phy spin lock from display code path
Start moving the initialization of display locks from
i915_driver_early_probe().
Display locks should be initialized from display-only code paths.
It was also agreed that if a variable is only used in one file, it
should be initialized
Hi Andrzej,
On Tue, Apr 25, 2023 at 12:05:43AM +0200, Andrzej Hajda wrote:
> Beside reusing existing code, the main advantage of ref_tracker is
> tracking per instance of wakeref. It allows also to catch double
> put.
> On the other side we lose information about the first acquire and
> the last r
On Thu, 2023-04-06 at 15:26 -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Don't use GEN9 as a prefix for register lists that contain all GEN8
> registers.
alan:snip
alan: This patch as a stand-along looks good, so I'll provide the RB but take
note of the comment below
that s
On Thu, Apr 20, 2023 at 03:40:41PM +0300, Mika Kahola wrote:
> Calculate port clock with C20 phy.
>
> BSpec: 64568
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
> .../gpu/drm/i9
On Thu, 2023-04-06 at 15:26 -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Fix Xe_LP name.
>
> Signed-off-by: John Harrison
alan:snip
> -/* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */
> +/* GEN8+ Render / Compute Per-Engine-Instance */
alan: two comments on this:
On Thu, 2023-04-06 at 15:26 -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Don't use 'xe_lp*' prefixes for register lists that are common with
> Gen8.
alan:snip
> @@ -177,32 +177,32 @@ static const struct __guc_mmio_reg_descr
> empty_regs_list[] = {
> static const struct _
Enable strict RAR to prevent spurious GPU hangs.
v1.1: Rebase
Cc: Rodrigo Vivi
Cc: Umesh Nerlige Ramappa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4
drivers/gpu/drm/i915/i915_perf_oa_regs.
On Thu, 2023-04-06 at 15:26 -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Remove 99% duplicated steered register list code. Also, include the
> pre-Xe steered registers in the pre-Xe list generation.
>
> Signed-off-by: John Harrison
alan: Nice work - good cleanup. Thanks so
On 2023-04-25 06:41:54, Joonas Lahtinen wrote:
> (+ Faith and Daniel as they have been involved in previous discussions)
>
> Quoting Jordan Justen (2023-04-24 20:13:00)
> > On 2023-04-24 02:08:43, Tvrtko Ursulin wrote:
> > >
> > > Being able to "list" supported extensions sounds like a reasonable
Enable strict RAR to prevent spurious GPU hangs.
Cc: Rodrigo Vivi
Cc: Umesh Nerlige Ramappa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
drivers/gpu/drm/i915/i915_perf_oa_regs.h| 4
On Thu, 2023-04-06 at 15:26 -0700, Harrison, John C wrote:
> From: John Harrison
>
> A pair of pre-Xe registers were being included in the Xe capture list.
> GuC was rejecting those as being invalid and logging errors about
> them. So, stop doing it.
>
alan:snip
> #define COMMON_GEN9BASE_GLOBAL
On Tue, 2023-04-25 at 16:41 +0300, Joonas Lahtinen wrote:
> (+ Faith and Daniel as they have been involved in previous discussions)
An orthogonal (but losely related) question: Is PXP the only subsystem that has
the unique problem of: Uses a delayed worker to complete all dependencies for
init..
b
Hi Tejas,
On Mon, Apr 24, 2023 at 03:47:49PM +0530, Tejas Upadhyay wrote:
> WA 18018781329 is applicable now across all MTL
> steppings.
>
> V2:
> - Remove IS_MTL check, code already running for MTL - Matt
>
> Cc: Matt Roper
> Signed-off-by: Tejas Upadhyay
pushed in drm-intel-gt-next.
Than
== Series Details ==
Series: drm/i915/dsi: ICL+ DSI modeset sequence fixes
URL : https://patchwork.freedesktop.org/series/116926/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13059_full -> Patchwork_116926v1_full
Summary
-
Hi Tejas,
On Mon, Apr 24, 2023 at 07:06:07PM +0530, Tejas Upadhyay wrote:
> igt_live_test has pr_err dumped in case of some
> GT failures. It will be more informative regarding
> GT if we use gt_err instead.
>
> Cc: Andi Shyti
> Signed-off-by: Tejas Upadhyay
pushed to drm-intel-gt-next.
Thank
Validate basic api for GT freq control. Also test
interaction with GT reset. We skip rps tests with
SLPC enabled, this will re-introduce some coverage.
SLPC selftests are already covering some other workload
related scenarios.
v2: Rename test (Rodrigo)
v3: Review comments (Ashutosh)
v4: Skip when
Trying out for CI. Do not review.
Signed-off-by: Vinay Belgaumkar
---
tests/intel-ci/fast-feedback.testlist | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/intel-ci/fast-feedback.testlist
b/tests/intel-ci/fast-feedback.testlist
index d9fcb62d..653668dd 100644
--- a/tests/intel-ci/fa
Borrow some subtests from xe_guc_pc. Also add per GT debugfs helpers.
v3: Review comments and add HAX patch
v4: Modify the condition for skipping the test
v5: Update the SLPC helper to per GT
v6: Review comments (Ashutosh)
Signed-off-by: Vinay Belgaumkar
Vinay Belgaumkar (4):
lib/debugfs: Add
These can be used to open per-gt debugfs files.
Reviewed-by: Ashutosh Dixit
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
---
lib/igt_debugfs.c | 60 +++
lib/igt_debugfs.h | 4
2 files changed, 64 insertions(+)
diff --git a/lib
Use default of 0 where GT id is not being used.
Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/8308
v2: Add a helper for GT 0 (Ashutosh)
v3: Additional review comments (Ashutosh)
v4: Return false if slpc debugfs is not found
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Ashutosh Dixit
On Tue, Apr 25, 2023 at 07:06:20AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/adlp+: Disable DC5/6 states for TC port DDI/AUX and for
> combo port AUX
> URL : https://patchwork.freedesktop.org/series/116909/
> State : success
Thanks for the review, pushed to drm-intel-
(+ Faith and Daniel as they have been involved in previous discussions)
Quoting Jordan Justen (2023-04-24 20:13:00)
> On 2023-04-24 02:08:43, Tvrtko Ursulin wrote:
> >
> > Being able to "list" supported extensions sounds like a reasonable
> > principle, albeit a departure from the design directio
On Tue, Apr 25, 2023 at 12:06 AM Andrzej Hajda wrote:
>
> Similar to stack_(depot|trace)_snprint the patch
> adds helper to printing stats to memory buffer.
> It will be helpful in case of debugfs.
>
> Signed-off-by: Andrzej Hajda
> Reviewed-by: Andi Shyti
Reviewed-by: Eric Dumazet
On Tue, Apr 25, 2023 at 12:06 AM Andrzej Hajda wrote:
>
> In case the library is tracking busy subsystem, simply
> printing stack for every active reference will spam log
> with long, hard to read, redundant stack traces. To improve
> readabilty following changes have been made:
> - reports are pr
== Series Details ==
Series: drm/i915/dsi: ICL+ DSI modeset sequence fixes
URL : https://patchwork.freedesktop.org/series/116926/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13059 -> Patchwork_116926v1
Summary
---
== Series Details ==
Series: drm/i915/dsi: ICL+ DSI modeset sequence fixes
URL : https://patchwork.freedesktop.org/series/116926/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitop
== Series Details ==
Series: drm/i915/display: Communicate display power demands to pcode (rev4)
URL : https://patchwork.freedesktop.org/series/115371/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13059 -> Patchwork_115371v4
===
== Series Details ==
Series: drm/i915/display: Communicate display power demands to pcode (rev4)
URL : https://patchwork.freedesktop.org/series/115371/
State : warning
== Summary ==
Error: dim checkpatch failed
ff5edc1e59b9 drm/i915/display: Communicate display power demands to pcode
-:9: WARN
From: Ville Syrjälä
No idea why the DSI code is feeling the need to assert that
has_pch_encoder must not be set. PCH encoders aren't even a
thing on any platform that has DSI.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 --
drivers/gpu/drm/i915/display/vlv_dsi.c
From: Ville Syrjälä
The encoder hooks already get passed the crtc state so just
grab the crtc from there instead of from the connector state.
This is generally what everyone else does, so no reason for
icl_dsi.c to be different.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl
From: Ville Syrjälä
Follow what Windows does and do the DSI panel reset+power off
after everything else.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_d
From: Ville Syrjälä
icl+ DSI isn't respecting the panel power_off_delay. Remedy that.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
i
From: Ville Syrjälä
Do the scaler disable in the spot where bspec has specfied it
for TLG+ DSC. And also move the DSC disable to match what
intel_ddi.c does.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
di
From: Ville Syrjälä
encoder->disable() is supposed to happen before the pipe/transcoder
gets disabled. The icl+ DSI code screwed that up and put most things
(including the transcoder disable itself) into encoder->disable().
Follow the common rules and hoist most things into the
encoder->post_dis
From: Ville Syrjälä
The clock gating step is in the wrong spot compared to the
TGL+ bspec sequence. Move it the right place. Windows also
seems to use the TGL+ order here always.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 5 ++---
1 file changed, 2 insertions(+),
From: Ville Syrjälä
Plug in the encoder->shutdown() hook for icl+ DSI so that
we are guaranteed to respect the power cycle delay during
reboots and whatnot.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
drivers/gpu/drm/i915/display/intel_dsi.c | 7 +++
dr
From: Ville Syrjälä
Handle the DSI panel power cycle delay on icl+.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 6 ++
drivers/gpu/drm/i915/display/intel_dsi.c | 13 +
drivers/gpu/drm/i915/display/intel_dsi.h | 1 +
drivers/gpu/drm/i915/display/
From: Ville Syrjälä
The programming of the DPHY vs. DSI _TIMING registers are
two separate steps in the TGL+ bspec sequence, with some
other stuff in between. Implement the same split.
Windows also seems follow the bspec TGL+ sequence, even
on ICL/JSL.
Signed-off-by: Ville Syrjälä
---
drivers/
From: Ville Syrjälä
Help out debugging things by printing out how long the VBT
delay sequence is supposed to wait.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/inte
From: Ville Syrjälä
Windows doesn't try any tricks to optimize out the DSI panel power
delays. Let's follow suit since anything else is entirely untested
behaviour. Why would the VBT even specify a power on delay if we're
not supposed to use it?
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm
From: Ville Syrjälä
Doing the init OTP and display on DSI sequences back to back
doesn't really make any sense (a single sequence would suffice
then). Move the display on sequence to be done just before
backlight on, which is also what Windows does.
Signed-off-by: Ville Syrjälä
---
drivers/gpu
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