Reviewed-by: Yan Zhao
On Fri, May 12, 2023 at 05:35:53PM -0700, Sean Christopherson wrote:
> Disable the page-track notifier code at compile time if there are no
> external users, i.e. if CONFIG_KVM_EXTERNAL_WRITE_TRACKING=n. KVM itself
> now hooks emulated writes directly instead of relying on
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Wednesday, May 17, 2023 5:33 AM
> To: Kandpal, Suraj ; David Airlie
> ; Daniel Vetter ; Jani Nikula
> ; Joonas Lahtinen
> ; Vivi, Rodrigo ;
> Tvrtko Ursulin ; Rob Clark
> ; Abhinav Kumar ;
> Sean Paul ; Marijn Suijten
>
> Cc:
>
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in preparation to
> adding more configuration data.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 139
Reviewed-by: Yan Zhao
On Fri, May 12, 2023 at 05:35:44PM -0700, Sean Christopherson wrote:
> Call kvm_mmu_zap_all_fast() directly when flushing a memslot instead of
> bouncing through the page-track mechanism. KVM (unfortunately) needs to
> zap and flush all page tables on memslot DELETE/MOVE
Hi, Thomas
After apply your patch set, the kernel with
arch/loongarch/configs/loongson3_defconfig
can not finish compile anymore. gcc complains:
AR drivers/gpu/built-in.a
AR drivers/built-in.a
AR built-in.a
AR vmlinux.a
LD vmlinux.o
OBJCOPY
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/mtl: Add MTL performance tuning
changes
URL : https://patchwork.freedesktop.org/series/117847/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_117847v1
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/mtl: Add MTL performance tuning
changes
URL : https://patchwork.freedesktop.org/series/117847/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
Reviewed-by: Yan Zhao
Tested-by: Yan Zhao
On Fri, May 12, 2023 at 05:35:39PM -0700, Sean Christopherson wrote:
> Now that gvt_pin_guest_page() explicitly verifies the pinned PFN is a
> transparent hugepage page, don't use KVM's gfn_to_pfn() to pre-check if a
> 2MiB GTT entry is possible and
Like DG2, MTL a-step hardware is subject to Wa_16014892111 which
requires that any changes made to the DRAW_WATERMARK register be
done via an INDIRECT_CTX batch buffer rather than through a regular
context workaround.
The bspec gives the same non-default recommended tuning value
for
MTL reuses the tuning parameters for DG2. Extend the dg2
performance tuning parameters to MTL.
v2: Add DRAW_WATERMARK tuning parameter.
v3: Limit DRAW_WATERMARK tuning to non A0 step.
v4: Reorder platform checks.
Restrict Blend fill caching optimization to Render GT.
Bspec: 68331
Cc:
On Tue, 16 May 2023 16:35:33 -0700, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> +static u64 frequency_enabled_mask(void)
u32
> +{
> + unsigned int i;
> + u64 mask = 0;
u32
> +
> + for (i = 0; i < I915_PMU_MAX_GTS; i++)
> + mask |=
== Series Details ==
Series: Add MTL PMU support for multi-gt
URL : https://patchwork.freedesktop.org/series/117843/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_117843v1
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: move DSC RC tables to drm_dsc_helper.c (rev7)
URL : https://patchwork.freedesktop.org/series/114473/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
AR
On Tue, 16 May 2023 16:35:28 -0700, Umesh Nerlige Ramappa wrote:
>
Hi Umesh/Tvrtko,
Mostly repeating comments/questions made on the previous patch below.
> From: Tvrtko Ursulin
>
> Having it as u64 was a confusing (but harmless) mistake.
>
> Also add some asserts to make sure the internal
== Series Details ==
Series: series starting with [CI,DO_NOT_MERGE,1/2] drm/i915/mtl: do not enable
render power-gating on MTL
URL : https://patchwork.freedesktop.org/series/117839/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_117839v1
Stop using an interim structure rc_parameters for storing calculated
params and then setting drm_dsc_config using that structure. Instead put
calculated params into the struct drm_dsc_config directly.
Reviewed-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in
preparation to adding more configuration data.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++
Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
Reviewed-by: Suraj Kandpal
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 450 +++
include/drm/display/drm_dsc_helper.h | 2 +
2 files changed, 452 insertions(+)
diff
Next commits are going to add support for additional RC parameter lookup
tables. These tables are going to use different bpp/bpc combinations,
thus it makes little sense to keep the 2d array for RC parameters.
Switch to using the flat array.
Reviewed-by: Jani Nikula
Signed-off-by: Dmitry
DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
include them here for completeness. The values were generated from the
'pre_scr_cfg_files_for_reference' files found in DSC models 20210623.
The same fileset is a part of DSC model 20161212.
Reviewed-by: Jessica Zhang
The rc_buf_thresh values are common to all DSC implementations. Move
them to the common helper together with the code to propagate them to
the drm_dsc_config.
Reviewed-by: Jani Nikula
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c |
Move DSC RC tables to DRM DSC helper. No additional code changes
and/or cleanups are a part of this commit, it will be cleaned up in the
followup commits.
Reviewed-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 372 ++
After cross-checking DSC models (20150914, 20161212, 20210623) change
values in rc_parameters tables to follow config files present inside
the DSC model. Handle two places, where i915 tables diverged from the
model, by patching the rc values in the code.
Note: I left one case uncorrected,
Other platforms (msm) will benefit from sharing the DSC config setup
functions. This series moves parts of static DSC config data from the
i915 driver to the common helpers to be used by other drivers.
Note: the RC parameters were cross-checked against config files found in
DSC model 2021062,
On 16/05/2023 21:46, Kandpal, Suraj wrote:
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in preparation to
adding more configuration data.
Hi ,
Needed to add some more comments apart from the previous ones
== Series Details ==
Series: series starting with [CI,DO_NOT_MERGE,1/2] drm/i915/mtl: do not enable
render power-gating on MTL
URL : https://patchwork.freedesktop.org/series/117839/
State : warning
== Summary ==
Error: dim checkpatch failed
00ac40784ada drm/i915/mtl: do not enable render
On Tue, May 16, 2023 at 03:13:01PM -0700, Umesh Nerlige Ramappa wrote:
On Tue, May 16, 2023 at 10:24:45AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
From: Tvrtko Ursulin
We do not want to have timers per tile and waste CPU cycles and energy via
multiple wake-up sources, for a relatively un-important task of PMU
sampling, so keeping a single timer works well. But we also do not want
the first GT which goes idle to turn off the timer.
Add
From: Tvrtko Ursulin
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet.
v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
From: Tvrtko Ursulin
Start exporting frequency and RC6 counters from all tiles.
Existing counters keep their names and config values and new one use the
namespace added in the previous patch, with the "-gtN" added to their
names.
Interrupts counter is an odd one off. Because it is the global
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 3 +++
1 file changed, 3 insertions(+)
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Cc:
With MTL, frequency and rc6 counters are specific to a gt. Export these
counters via gt-specific events to the user space.
v2: Remove aggregation support from kernel
v3: Review comments (Ashutosh, Tvrtko)
v4:
- Include R-b for 6/6
- Add Test-with
- Fix versioning info in cover letter
v5:
-
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev9)
URL : https://patchwork.freedesktop.org/series/116870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_116870v9
Summary
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev9)
URL : https://patchwork.freedesktop.org/series/116870/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/guc/slpc: Disable rps_boost debugfs (rev2)
URL : https://patchwork.freedesktop.org/series/117711/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_117711v2
Summary
On Tue, May 16, 2023 at 10:24:45AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
Signed-off-by: Tvrtko Ursulin
Cc: Ashutosh Dixit
Cc: Umesh
On 5/16/2023 13:52, Rodrigo Vivi wrote:
On Tue, May 16, 2023 at 12:21:05PM -0700, John Harrison wrote:
On 5/16/2023 12:17, Belgaumkar, Vinay wrote:
> On 4/18/2023 11:17 AM, [1]john.c.harri...@intel.com
Multiple CI tests fails if render power gatins is enabled,
with forcewake ack timeouts.
BSpec 52698 clearly states it should be 0.
Media gate seems also problematic.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983
Signed-off-by: Andrzej Hajda
---
Let's try disabling render
Multiple CI tests fails with forcewake timeouts. Disabling power
gating for render and media solves the issue.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +++
1 file changed, 3 insertions(+)
diff
== Series Details ==
Series: series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable
render power-gating on MTL
URL : https://patchwork.freedesktop.org/series/117819/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_117819v1
== Series Details ==
Series: series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable
render power-gating on MTL
URL : https://patchwork.freedesktop.org/series/117819/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit
== Series Details ==
Series: series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable
render power-gating on MTL
URL : https://patchwork.freedesktop.org/series/117819/
State : warning
== Summary ==
Error: dim checkpatch failed
e0f1fa65f100 drm/i915/mtl: do not enable render
== Series Details ==
Series: drm/i915: fix intel_display_irq.c include order
URL : https://patchwork.freedesktop.org/series/117816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151_full -> Patchwork_117816v1_full
On Tue, May 16, 2023 at 12:21:05PM -0700, John Harrison wrote:
>On 5/16/2023 12:17, Belgaumkar, Vinay wrote:
>
>
>
>> On 4/18/2023 11:17 AM, [1]john.c.harri...@intel.com
== Series Details ==
Series: drm/i915/gem: Use large rings for compute contexts
URL : https://patchwork.freedesktop.org/series/117814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151_full -> Patchwork_117814v1_full
Hi, Vinod.
I have provided a comment inline below. Also note that I have replied to
some of your comments on the previous version [1].
[1]
https://patchwork.freedesktop.org/patch/534347/?series=116949=4#comment_973634
Quoting Vinod Govindapillai (2023-05-11 20:17:49)
>From: Mika Kahola
>
On 5/16/2023 12:17, Belgaumkar, Vinay wrote:
On 4/18/2023 11:17 AM, john.c.harri...@intel.com wrote:
From: John Harrison
This is useful for getting debug information out in certain
situations, such as failing kernel selftests and CI runs that don't
log error captures. It is especially useful
== Series Details ==
Series: drm/i915: tweak language in fastset pipe config compare logging
URL : https://patchwork.freedesktop.org/series/117807/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13151_full -> Patchwork_117807v1_full
On 4/18/2023 11:17 AM, john.c.harri...@intel.com wrote:
From: John Harrison
In the past, There have been sporadic CTB failures which proved hard
to reproduce manually. The most effective solution was to dump the GuC
log at the point of failure and let the CI system do the repro. It is
On 4/18/2023 11:17 AM, john.c.harri...@intel.com wrote:
From: John Harrison
This is useful for getting debug information out in certain
situations, such as failing kernel selftests and CI runs that don't
log error captures. It is especially useful for things like retrieving
GuC logs as GuC
On 4/18/2023 11:17 AM, john.c.harri...@intel.com wrote:
From: John Harrison
Sometimes, the only effective way to debug an issue is to dump all the
interesting information at the point of failure. So add support for
doing that.
v2: Extra CONFIG wrapping (review feedback from Rodrigo)
>
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in preparation to
> adding more configuration data.
>
Hi ,
Needed to add some more comments apart from the previous ones already given
> Signed-off-by:
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a
From: Fei Yang
This series introduce a new extension for GEM_CREATE,
1. end support for set caching ioctl [PATCH 4/5]
2. add set_pat extension for gem_create [PATCH 5/5]
v2: drop one patch that was merged separately
commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
v3: rebased
> Subject: [PATCH v5 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR)
> parameters
>
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in preparation to
> adding more configuration data.
>
>
On Tue, 16 May 2023 02:24:45 -0700, Tvrtko Ursulin wrote:
>
> From: Tvrtko Ursulin
>
> Having it as u64 was a confusing (but harmless) mistake.
>
> Also add some asserts to make sure the internal field does not overflow
> in the future.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Ashutosh Dixit
>
== Series Details ==
Series: drm/i915/syncmap: squelch a sparse warning
URL : https://patchwork.freedesktop.org/series/117802/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151_full -> Patchwork_117802v1_full
Summary
On Tue, 16 May 2023 00:12:45 -0700, Tvrtko Ursulin wrote:
>
> On 15/05/2023 22:24, Dixit, Ashutosh wrote:
> > On Mon, 15 May 2023 02:52:35 -0700, Tvrtko Ursulin wrote:
> >>
> >> On 13/05/2023 00:44, Umesh Nerlige Ramappa wrote:
> >>> On Fri, May 12, 2023 at 04:20:19PM -0700, Dixit, Ashutosh wrote:
On Tue, May 16, 2023 at 4:05 AM Jani Nikula wrote:
>
> On Thu, 09 Mar 2023, Jani Nikula wrote:
> > On Thu, 09 Mar 2023, Christian König wrote:
> >> Am 09.03.23 um 13:37 schrieb Jani Nikula:
> >>> Make the struct ttm_device_funcs pointers const so the data can be placed
> >>> in rodata.
> >>>
>
Am 09.03.23 um 13:37 schrieb Jani Nikula:
Make the struct ttm_device_funcs pointers const so the data can be placed in
rodata.
Cc: Christian Koenig
Cc: Huang Rui
Signed-off-by: Jani Nikula
Reviewed-by: Thomas Zimmermann
---
drivers/gpu/drm/ttm/ttm_device.c | 2 +-
Hi Andrzej,
Thanks for review.
On Tuesday, 16 May 2023 16:08:26 CEST Andrzej Hajda wrote:
> On 16.05.2023 12:05, Janusz Krzysztofik wrote:
> > Visible glitches have been observed when running graphics applications on
> > Linux under Xen hypervisor. Those observations have been confirmed with
>
rps_boost debugfs shows host turbo related info. This is not valid
when SLPC is enabled. guc_slpc_info already shows the number of boosts.
Add num_waiters there as well and disable rps_boost when SLPC is
enabled.
v2: Replace Bug with Link to resolve checkpatch warning
Link:
== Series Details ==
Series: drm/i915: constify pointers to hwmon_channel_info (rev2)
URL : https://patchwork.freedesktop.org/series/117750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151_full -> Patchwork_117750v2_full
== Series Details ==
Series: drm/i915: fix intel_display_irq.c include order
URL : https://patchwork.freedesktop.org/series/117816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117816v1
Summary
---
== Series Details ==
Series: drm/i915/gem: Use large rings for compute contexts
URL : https://patchwork.freedesktop.org/series/117814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117814v1
Summary
On 16.05.2023 12:05, Janusz Krzysztofik wrote:
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
frame buffer objects using
On Sat, May 13, 2023 at 01:08:42AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue
> (rev13)
> URL : https://patchwork.freedesktop.org/series/117004/
> State : success
Patchset is pushed to -din, thanks for the
Multiple CI tests fails if render power gatins is enabled,
with forcewake ack timeouts.
BSpec 52698 clearly states it should be 0.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983
Signed-off-by: Andrzej Hajda
---
Let's see if disabling render pg is enough.
---
The test examines if running spinners do not interfere with forcewake.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/selftests/intel_uncore.c | 85 +++
1 file changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
Multiple CI tests fails with forcewake timeouts. Disabling power
gating for render and media solves the issue.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +++
1 file changed, 3 insertions(+)
diff
== Series Details ==
Series: drm/i915: tweak language in fastset pipe config compare logging
URL : https://patchwork.freedesktop.org/series/117807/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117807v1
Hi Sam
Am 15.05.23 um 19:43 schrieb Sam Ravnborg:
Hi Thomas,
On Mon, May 15, 2023 at 11:40:24AM +0200, Thomas Zimmermann wrote:
Use the regular fbdev helpers for framebuffer I/O instead of DRM's
helpers. Exynos does not use damage handling, so DRM's fbdev helpers
are mere wrappers around the
Hi
Am 15.05.23 um 20:04 schrieb Russell King (Oracle):
On Mon, May 15, 2023 at 07:55:44PM +0200, Sam Ravnborg wrote:
Hi Thomas,
On Mon, May 15, 2023 at 11:40:23AM +0200, Thomas Zimmermann wrote:
Use the regular fbdev helpers for framebuffer I/O instead of DRM's
helpers. Armada does not use
Quoting Jani Nikula (2023-05-16 09:29:26)
>I meant to sort the includes before submitting commit 2b874a027810
>("drm/i915/irq: split out display irq handling") but forgot, and it
>wasn't noticed in review either. Sort the includes.
Oops... My bad.
>
>Cc: Gustavo Sousa
>Signed-off-by: Jani
Hi
Am 15.05.23 um 19:55 schrieb Sam Ravnborg:
Hi Thomas,
On Mon, May 15, 2023 at 11:40:23AM +0200, Thomas Zimmermann wrote:
Use the regular fbdev helpers for framebuffer I/O instead of DRM's
helpers. Armada does not use damage handling, so DRM's fbdev helpers
are mere wrappers around the
On 15/05/2023 12:12, Jani Nikula wrote:
On Thu, 04 May 2023, Dmitry Baryshkov wrote:
Other platforms (msm) will benefit from sharing the DSC config setup
functions. This series moves parts of static DSC config data from the
i915 driver to the common helpers to be used by other drivers.
Note:
On Tue, 16 May 2023, Tejas Upadhyay wrote:
> From: Chris Wilson
>
> Allow compute contexts to submit the maximal amount of work without
> blocking userspace.
>
> The original size for user LRC ring's (SZ_16K) was chosen to minimise
> memory consumption, without being so small as to frequently
I meant to sort the includes before submitting commit 2b874a027810
("drm/i915/irq: split out display irq handling") but forgot, and it
wasn't noticed in review either. Sort the includes.
Cc: Gustavo Sousa
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 16
From: Chris Wilson
Allow compute contexts to submit the maximal amount of work without
blocking userspace.
The original size for user LRC ring's (SZ_16K) was chosen to minimise
memory consumption, without being so small as to frequently stall in the
middle of workloads. With the main consumers
== Series Details ==
Series: drm/i915/pmu: Change bitmask of enabled events to u32
URL : https://patchwork.freedesktop.org/series/117805/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117805v1
Summary
On Tue, May 16, 2023 at 01:43:44PM +0300, Lisovskiy, Stanislav wrote:
> On Fri, May 12, 2023 at 11:54:16AM +0530, Ankit Nautiyal wrote:
> > Currently, we take the max lane, rate and pipe bpp, to get the maximum
> > compressed bpp possible. We then set the output bpp to this value.
> > This patch
> -Original Message-
> From: Intel-gfx On Behalf Of Suraj
> Kandpal
> Sent: Monday, May 15, 2023 4:02 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v4 0/4] Fix modeset locking issue in HDCP MST
>
> HDCP MST scenario sees modeset locking issue ever since
== Series Details ==
Series: drm/i915/syncmap: squelch a sparse warning
URL : https://patchwork.freedesktop.org/series/117802/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117802v1
Summary
---
== Series Details ==
Series: drm/i915/syncmap: squelch a sparse warning
URL : https://patchwork.freedesktop.org/series/117802/
State : warning
== Summary ==
Error: dim checkpatch failed
2e08e006d88c drm/i915/syncmap: squelch a sparse warning
-:4: WARNING:EMAIL_SUBJECT: A patch subject line
On Fri, May 12, 2023 at 11:54:16AM +0530, Ankit Nautiyal wrote:
> Currently, we take the max lane, rate and pipe bpp, to get the maximum
> compressed bpp possible. We then set the output bpp to this value.
> This patch provides support to have max bpp, min rate and min lanes,
> that can support
== Series Details ==
Series: drm/i915/mtl: Fix expected reg value for Thunderbolt PLL disabling
(rev3)
URL : https://patchwork.freedesktop.org/series/117690/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13148_full -> Patchwork_117690v3_full
>
> The "fastset mismatch" debug logging has been slightly confusing, leading
> people to believe some error happened. Change it to the more informative
> "fastset requirement not met", and add a final message about this leading to
> full modeset.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Cc:
On Mon, May 15, 2023 at 05:44:51PM +0300, Ville Syrjälä wrote:
> On Fri, May 12, 2023 at 11:54:09AM +0530, Ankit Nautiyal wrote:
> > As per Bsepc:49259, Bigjoiner BW check puts restriction on the
> > compressed bpp for a given CDCLK, pixelclock in cases where
> > Bigjoiner + DSC are used.
> >
> >
== Series Details ==
Series: drm/i915: constify pointers to hwmon_channel_info (rev2)
URL : https://patchwork.freedesktop.org/series/117750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117750v2
Summary
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
frame buffer objects using hardware CRC checksums calculated by display
hi Sean
Do you think it's necessary to double check that struct page pointers
are also contiguous?
And do you like to also include a fix as below, which is to remove the
warning in vfio_device_container_unpin_pages() when npage is 0?
@ -169,7 +173,8 @@ static int gvt_pin_guest_page(struct
== Series Details ==
Series: Fix modeset locking issue in HDCP MST (rev5)
URL : https://patchwork.freedesktop.org/series/117615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13148_full -> Patchwork_117615v5_full
Summary
== Series Details ==
Series: Fix modeset locking issue in HDCP MST (rev5)
URL : https://patchwork.freedesktop.org/series/117615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13148_full -> Patchwork_117615v5_full
Summary
The "fastset mismatch" debug logging has been slightly confusing,
leading people to believe some error happened. Change it to the more
informative "fastset requirement not met", and add a final message about
this leading to full modeset.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
Signed-off-by: Tvrtko Ursulin
Cc: Ashutosh Dixit
Cc: Umesh Nerlige Ramappa
---
I am not entirely sure the
Hi Kamil,
Thanks for review.
On Monday, 15 May 2023 22:02:51 CEST Kamil Konieczny wrote:
> Hi Janusz,
>
> On 2023-05-15 at 10:50:20 +0200, Janusz Krzysztofik wrote:
> > Visible glitches have been observed when running graphics applications on
> > Linux under Xen hypervisor. Those observations
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