On Fri, 25 Aug 2023, Linyu Yuan wrote:
> GCC report GUC_KLV_0_KEY and GUC_KLV_0_LEN is not constant when do
> preprocessing.
Please paste the actual compiler warning.
BR,
Jani.
>
> Change to use GENMASK() to avoid the issue.
>
> Signed-off-by: Linyu Yuan
> ---
>
On Wed, Aug 23, 2023 at 01:49:21PM -0700, Matt Roper wrote:
On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote:
LNL's south display uses the same table as MTP. Check for LNL's fake PCH
to make it consistent with the other checks.
The VBT table doesn't contain the VBT -> spec
== Series Details ==
Series: eDP DSC fixes (rev3)
URL : https://patchwork.freedesktop.org/series/122792/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13561_full -> Patchwork_122792v3_full
Summary
---
**FAILURE**
== Series Details ==
Series: drm/bridge_connector: implement OOB HPD handling (rev3)
URL : https://patchwork.freedesktop.org/series/120395/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13562 -> Patchwork_120395v3
Summary
== Series Details ==
Series: drm/bridge_connector: implement OOB HPD handling (rev3)
URL : https://patchwork.freedesktop.org/series/120395/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/bridge_connector: implement OOB HPD handling (rev3)
URL : https://patchwork.freedesktop.org/series/120395/
State : warning
== Summary ==
Error: dim checkpatch failed
c914ada6d133 drm: Add HPD state to drm_connector_oob_hotplug_event()
b16fe4596376
On Wed, Aug 23, 2023 at 10:07:40AM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan
>
> Enable the display support for LUNARLAKE
>
> Signed-off-by: Balasubramani Vivekanandan
>
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/xe/xe_pci.c | 1 +
> 1 file changed, 1
On Wed, Aug 23, 2023 at 10:07:38AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli
>
> Add support to check c10 phy link rate for LNL in
> intel_c10_phy_check_hdmi_link_rate() function.
If it turns out the LNL tables from the previous patch aren't necessary,
then we should be able to
== Series Details ==
Series: iommu/vt-d: Check domain flags before setting snp bit in page-control
(rev2)
URL : https://patchwork.freedesktop.org/series/121893/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13562 -> Patchwork_121893v2
On Wed, Aug 23, 2023 at 10:07:37AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli
>
> Add PLL Table for Lunar Lake platform.
>
> BSpec: 68862
I think this should actually be 74224?
> Cc: Clint Taylor
> Cc: Anusha Srivatsa
> Signed-off-by: Ravi Kumar Vodapalli
> Signed-off-by:
From: Bjorn Andersson
In some implementations, such as the Qualcomm platforms, the display
driver has no way to query the current HPD state and as such it's
impossible to distinguish between disconnect and attention events.
Add a parameter to drm_connector_oob_hotplug_event() to pass the HPD
Implement the oob_hotplug_event() callback. Translate it to the HPD
notification sent to the HPD bridge in the chain.
Reviewed-by: Janne Grunau
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/drm_bridge_connector.c | 29 +++---
1 file changed, 26 insertions(+), 3
In some cases the bridge drivers would like to receive hotplug events
even in the case new status is equal to the old status. In the DP case
this is used to deliver "attention" messages to the DP host. Stop
filtering the events in the drm_bridge_connector_hpd_cb() and let
drivers decide whether
Note, numbering for this series starts from v5, since there were several
revisions for this patchset under a different series title ([1]).
USB altmodes code would send OOB notifications to the drm_connector
specified in the device tree. However as the MSM DP driver uses
drm_bridge_connector,
On Wed, Aug 23, 2023 at 10:07:34AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli
>
> Add CDCLK initialization sequence changes and CDCLK set frequency
> sequence for LNL platform.
>
> CDCLK frequency change sequence is different for LNL compared to MTL
> when a change in
== Series Details ==
Series: iommu/vt-d: Check domain flags before setting snp bit in page-control
(rev2)
URL : https://patchwork.freedesktop.org/series/121893/
State : warning
== Summary ==
Error: dim checkpatch failed
5275ee2b0d93 iommu/vt-d: Check domain flags before setting snp bit in
On Wed, Aug 23, 2023 at 10:07:33AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy
>
> When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
> between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
> change.
>
> Previsouly DBuf state and CDCLK were not
== Series Details ==
Series: series starting with [1/3] drm/i915: Create a bind context for GGTT
updates
URL : https://patchwork.freedesktop.org/series/122870/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13562 -> Patchwork_122870v1
== Series Details ==
Series: series starting with [1/3] drm/i915: Create a bind context for GGTT
updates
URL : https://patchwork.freedesktop.org/series/122870/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
== Series Details ==
Series: series starting with [1/3] drm/i915: Create a bind context for GGTT
updates
URL : https://patchwork.freedesktop.org/series/122870/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc:
On Wed, Aug 23, 2023 at 12:28:04PM -0700, Matt Roper wrote:
On Wed, Aug 23, 2023 at 10:07:18AM -0700, Lucas De Marchi wrote:
From: Clint Taylor
Do not read DE_RRMR register after display version 20. This register
contains display state information during GFX state dumps.
Bspec: 69456
Cc:
From: Ashok Raj
Signed-off-by: Ashok Raj
Signed-off-by: Radhakrishna Sripada
---
drivers/iommu/intel/iommu.c | 2 +-
drivers/iommu/intel/pasid.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index
== Series Details ==
Series: drm/i915/dp_link_training: Define a final failure state when link
training fails (rev2)
URL : https://patchwork.freedesktop.org/series/122850/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13562 -> Patchwork_122850v2
== Series Details ==
Series: drm/i915/vma: constify unbind_fence_ops (rev2)
URL : https://patchwork.freedesktop.org/series/122627/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13560_full -> Patchwork_122627v2_full
Summary
On Thu, Aug 24, 2023 at 06:06:10PM -0400, Rodrigo Vivi wrote:
> On Wed, Aug 23, 2023 at 03:22:07PM -0700, Matt Roper wrote:
> > On Wed, Aug 23, 2023 at 05:39:01PM -0400, Rodrigo Vivi wrote:
> > > Let's introduce the basic documentation about CCS.
> > > While doing that, also removed the legacy
== Series Details ==
Series: drm/i915/dp_link_training: Define a final failure state when link
training fails (rev2)
URL : https://patchwork.freedesktop.org/series/122850/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: drm/i915/dp_link_training: Define a final failure state when link
training fails (rev2)
URL : https://patchwork.freedesktop.org/series/122850/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50:
On Wed, Aug 23, 2023 at 03:22:07PM -0700, Matt Roper wrote:
> On Wed, Aug 23, 2023 at 05:39:01PM -0400, Rodrigo Vivi wrote:
> > Let's introduce the basic documentation about CCS.
> > While doing that, also removed the legacy execution flag name. That flag
> > simply doesn't exist for CCS and it is
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/122864/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13562 -> Patchwork_122864v1
Summary
---
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/122864/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/122864/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123 (rev3)
URL : https://patchwork.freedesktop.org/series/122804/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13562 -> Patchwork_122804v3
Summary
---
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123 (rev3)
URL : https://patchwork.freedesktop.org/series/122804/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123 (rev3)
URL : https://patchwork.freedesktop.org/series/122804/
State : warning
== Summary ==
Error: dim checkpatch failed
5fe66b3b6af8 drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
-:11: WARNING:BAD_SIGN_OFF:
From: Nirmoy Das
MTL can hang because of a HW bug while parallel reading/writing
from/to LMEM/GTTMMADR BAR so try to reduce GGTT update
related pci transactions with blitter command as recommended
for Wa_13010847436 and Wa_14019519902.
To issue blitter commands, the driver must be primed to
From: Nirmoy Das
Implement GGTT update method with blitter command, MI_UPDATE_GTT
and install those handlers if a platform requires that.
v2: Make sure we hold the GT wakeref and Blitter engine wakeref before
we call mutex_lock/intel_context_enter below. When GT/engine are not
awake, the
From: Nirmoy Das
Create a separate blitter context if a platform requires
GGTT updates using MI_UPDATE_GTT blitter command.
Subsequent patch will introduce methods to update
GGTT using this blitter context and MI_UPDATE_GTT blitter
command.
v2: Fix a typo in comment. (Oak)
v3:
Thanks,
Oak
> -Original Message-
> From: Intel-gfx On Behalf Of Zeng,
> Oak
> Sent: August 24, 2023 4:38 PM
> To: Roper, Matthew D
> Cc: chris.p.wil...@linux.intel.com; intel-gfx@lists.freedesktop.org; Shyti,
> Andi
> ; Das, Nirmoy
> Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915:
When a link-training attempt fails, emit a uevent to user space that
includes the trigger property, which in this case will be
link-statue=Bad.
This will allow userspace to parse the uevent property and better
understand the reason for the previous modeset failure.
Signed-off-by: Gil Dekel
V2:
Currently, link-training fallback is only implemented for SST, so having
modeset_retry_work in intel_connector makes sense. However, we hope to
implement link training fallback for MST in a follow-up patchset, so
moving modeset_retry_work to indel_dp will make handling both SST and
MST connectors
Before sending a uevent to userspace in order to trigger a corrective
modeset, we change the failing connector's link-status to BAD. However,
the downstream MST branch ports are left in their original GOOD state.
This patch utilizes the drm helper function
drm_dp_set_mst_topology_link_status() to
Unlike SST, MST can support multiple displays connected to a single
connector. However, this also means that if the DisplayPort link to the
top-level MST branch device becomes unstable, then every single branch
device has an unstable link.
Since there are multiple downstream ports per connector,
Currently, MST link training has no fallback. This means that if an MST
base connector fails to link-train once, the training completely fails,
which makes this case significantly more common than a complete SST link
training failure.
Similar to the final failure state of SST, this patch zeros
Instead of silently giving up when all link-training fallback values are
exhausted, this patch modifies the fallback's failure branch to reduces
both max_link_lane_count and max_link_rate to zero (0) and continues to
emit uevents until userspace stops attempting to modeset.
By doing so, we ensure
Next version of https://patchwork.freedesktop.org/series/122850/
v4:
Another blunder. I uploaded the patches from my ChromeiumOS kernel dev repo
instead of drm-tip/drm-tip. Apologies for the noise :(
v3:
Still learning the ropes of upstream workflow. Apologies for mucking up v2.
This is
== Series Details ==
Series: drm/i915/color: cleanups and refactoring (rev2)
URL : https://patchwork.freedesktop.org/series/122588/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13562 -> Patchwork_122588v2
Summary
---
== Series Details ==
Series: drm/i915/dp_link_training: Define a final failure state when link
training fails
URL : https://patchwork.freedesktop.org/series/122850/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/122850/revisions/1/mbox/ not
Thanks,
Oak
> -Original Message-
> From: Roper, Matthew D
> Sent: August 24, 2023 11:54 AM
> To: Zeng, Oak
> Cc: intel-gfx@lists.freedesktop.org; Shyti, Andi ;
> chris.p.wil...@linux.intel.com; Das, Nirmoy
> Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Enable GGTT blitting in MTL
Thanks,
Oak
> -Original Message-
> From: Roper, Matthew D
> Sent: August 24, 2023 11:52 AM
> To: Zeng, Oak
> Cc: intel-gfx@lists.freedesktop.org; Shyti, Andi ;
> chris.p.wil...@linux.intel.com; Das, Nirmoy
> Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915: Create a blitter context for
== Series Details ==
Series: drm/i915/color: cleanups and refactoring (rev2)
URL : https://patchwork.freedesktop.org/series/122588/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: drm/i915/color: cleanups and refactoring (rev2)
URL : https://patchwork.freedesktop.org/series/122588/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: drm, cec and edid updates
URL : https://patchwork.freedesktop.org/series/122841/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13562 -> Patchwork_122841v1
Summary
---
**SUCCESS**
No
From: Nirmoy Das
Apply WABB blit for Wa_16018031267 / Wa_16018063123.
Additionally, update the lrc selftest to exercise the new
WABB changes.
Co-developed-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +
drivers/gpu/drm/i915/gt/intel_gt.h
From: Nirmoy Das
Set copy engine arbitration into round robin mode
for part of Wa_16018031267 / Wa_16018063123 mitigation.
Signed-off-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.
v2:
- Rename old platform check in second patch to match
declaration in first patch.
- Refactor second patch name to match first patch.
v3:
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.
v2:
- Rename old platform check in second patch to match
declaration in first patch.
- Refactor second patch name to match first patch.
v3:
From: Nirmoy Das
Apply WABB blit for Wa_16018031267 / Wa_16018063123.
Additionally, update the lrc selftest to exercise the new
WABB changes.
Co-developed-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +
drivers/gpu/drm/i915/gt/intel_gt.h
From: Nirmoy Das
Set copy engine arbitration into round robin mode
for part of Wa_16018031267 / Wa_16018063123 mitigation.
Signed-off-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
== Series Details ==
Series: drm, cec and edid updates
URL : https://patchwork.freedesktop.org/series/122841/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: drm/i915/rpl: Add new RPL PCI-IDs
URL : https://patchwork.freedesktop.org/series/122831/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13559_full -> Patchwork_122831v1_full
Summary
---
Hi Dave and Daniel,
here is this week's PR for drm-misc-next. One of the patches is a
change to nouveau's UAPI.
Best regards
Thomas
drm-misc-next-fixes-2023-08-24:
Short summary of fixes pull:
* gpuva: Cleanups
* kunit: Documentation fixes
* nouveau:
* UAPI: Avoid implicit NO_PREFETCH
On Wed, Aug 23, 2023 at 11:51:03AM -0700, Jonathan Cavitt wrote:
> From: Nirmoy Das
>
> Apply WABB blit for Wa_16018031267 / Wa_16018063123.
> Additionally, update the lrc selftest to exercise the new
> WABB changes.
>
> Signed-off-by: Jonathan Cavitt
> Co-developed-by: Nirmoy Das
> ---
>
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev2)
URL : https://patchwork.freedesktop.org/series/122589/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13559_full -> Patchwork_122589v2_full
> Subject: RE: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed bpp in
> U6.4 format
>
> > Subject: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed
> > bpp in
> > U6.4 format
> >
> > DSC parameter bits_per_pixel is stored in U6.4 format.
> > The 4 bits represent the
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 27
> +
> include/drm/display/drm_dp_helper.h | 1 +
> 2 files changed, 28 insertions(+)
>
> diff --git
> Subject: [Intel-gfx] [PATCH 3/9] drm/i915/display: Consider fractional vdsc
> bpp while computing m_n values
>
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate this precision while computing m_n values.
>
>
> > Add helper to get the DSC bits_per_pixel precision for the DP sink.
> >
> > Signed-off-by: Ankit Nautiyal
Wouldn't we also need to send this patch to dri-devel
Regards,
Suraj Kandpal
> > ---
> > drivers/gpu/drm/display/drm_dp_helper.c | 27
> > +
> >
> Subject: [Intel-gfx] [PATCH 4/9] drm/i915/audio : Consider fractional vdsc bpp
> while computing tu_data
>
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate the precision during calculation of transfer
> Subject: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed bpp in
> U6.4 format
>
> DSC parameter bits_per_pixel is stored in U6.4 format.
> The 4 bits represent the fractional part of the bpp.
> Currently we use compressed_bpp member of dsc structure to store only the
> integral part
> >> Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out
> >> of the main _max_lane_count() func
> >>
> >> From: Luca Coelho
> >>
> >> This makes the code a bit more symmetric and readable, especially
> >> when we start adding more display version-specific alternatives.
> >>
> >>
Hi @Jani Nikula ,
Thanks for your feedback. Please find my comments below:
On Thu, Aug 24, 2023 at 4:27 AM Jani Nikula wrote:
>
> On Fri, 18 Aug 2023, Manasi Navare wrote:
> > Dual refresh rate (DRR) fastset seamlessly lets refresh rate
> > throttle without needing a full modeset.
> > However
On Wed, Aug 23, 2023 at 12:49:36PM -0700, Matt Roper wrote:
On Wed, Aug 23, 2023 at 10:07:21AM -0700, Lucas De Marchi wrote:
From: Matt Roper
FBC is no longer limited by pipe.
It looks like we lost the part of this patch that adds this to the
xe2_lpd_display device info structure.
ack,
On Thu, Aug 24, 2023 at 08:49:42AM -0700, Lucas De Marchi wrote:
> On Wed, Aug 23, 2023 at 11:03:42AM -0700, Matt Roper wrote:
> > On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
> > > From: Balasubramani Vivekanandan
> > >
> > > Add Lunar Lake platform definitions for i915
Hi Ville and Jani,
Thanks for your review and feedback.
To rightly explain the use case here:
Case 1: We are at 120 Hz refresh rate so by default VRR registers are
programmed for 120Hz case. And say the VRR range is 30-120Hz we get
the full range here.
Case 2: When we switch to downclock mode of
On Tue, Aug 22, 2023 at 11:28:59AM -0400, Oak Zeng wrote:
> From: Nirmoy Das
>
> MTL can hang because of a HW bug while parallel reading/writing
> from/to LMEM/GTTMMADR BAR so try to reduce GGTT update
> related pci transactions with blitter command as recommended
> for Wa_22018444074.
Drive-by
On Tue, Aug 22, 2023 at 11:28:57AM -0400, Oak Zeng wrote:
> From: Nirmoy Das
>
> Create a separate blitter context if a platform requires
> GGTT updates using MI_UPDATE_GTT blitter command.
>
> Subsequent patch will introduce methods to update
> GGTT using this blitter context and MI_UPDATE_GTT
On Wed, Aug 23, 2023 at 11:03:42AM -0700, Matt Roper wrote:
On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
From: Balasubramani Vivekanandan
Add Lunar Lake platform definitions for i915 display. The support for
LNL will be added to the xe driver, with i915 only driving the
On Thu, Aug 24, 2023 at 11:58:40AM +0530, Dnyaneshwar Bhadane wrote:
> Update pci device ids as per bspec for
> RPL P/U.
> Bpsec: 55376
>
> v2:
> - Append new id's instead of replacing the existing in device
> id list define
>
> v3:
> - Fixed the commit messege with revision details.
>
>
On Wed, Aug 23, 2023 at 10:55:34AM -0700, Matt Roper wrote:
On Wed, Aug 23, 2023 at 10:07:09AM -0700, Lucas De Marchi wrote:
From: Balasubramani Vivekanandan
Add IS_LUNARLAKE in the compat-i915-headers. That macro, to be used by
the xe driver, checks for the platform, whereas the macro on the
Before sending a uevent to userspace in order to trigger a corrective
modeset, we change the failing connector's link-status to BAD. However,
the downstream MST branch ports are left in their original GOOD state.
This patch utilizes the drm helper function
drm_dp_set_mst_topology_link_status() to
When a link-training attempt fails, emit a uevent to user space that
includes the trigger property, which in this case will be
link-statue=Bad.
This will allow userspace to parse the uevent property and better
understand the reason for the previous modeset failure.
Change-Id:
Currently, link-training fallback is only implemented for SST, so having
modeset_retry_work in intel_connector makes sense. However, we hope to
implement link training fallback for MST in a follow-up patchset, so
moving modeset_retry_work to indel_dp will make handling both SST and
MST connectors
Unlike SST, MST can support multiple displays connected to a single
connector. However, this also means that if the DisplayPort link to the
top-level MST branch device becomes unstable, then every single branch
device has an unstable link.
Since there are multiple downstream ports per connector,
Currently, MST link training has no fallback. This means that if an MST
base connector fails to link-train once, the training completely fails,
which makes this case significantly more common than a complete SST link
training failure.
Similar to the final failure state of SST, this patch zeros
Instead of silently giving up when all link-training fallback values are
exhausted, this patch modifies the fallback's failure branch to reduces
both max_link_lane_count and max_link_rate to zero (0) and continues to
emit uevents until userspace stops attempting to modeset.
By doing so, we ensure
Next version of https://patchwork.freedesktop.org/series/122643/
v3:
Still learning the ropes of upstream workflow. Apologies for mucking up v2.
This is just a re-upload.
v2:
Reorganize into:
1) Add for final failure state for SST and MST link training fallback.
2) Add a DRM helper for
Hi Suraj,
On Thu, Aug 24, 2023 at 05:43:15AM +, Kandpal, Suraj wrote:
-Original Message-
From: Intel-gfx On Behalf Of Lucas
De Marchi
Sent: Wednesday, August 23, 2023 10:37 PM
To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Coelho, Luciano
Subject:
On Thu, Aug 24, 2023 at 11:34:22AM +, Coelho, Luciano wrote:
On Wed, 2023-08-23 at 10:07 -0700, Lucas De Marchi wrote:
From: Luca Coelho
Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.
We use
== Series Details ==
Series: drm/i915/rpl: Update pci ids for RPL P/U (rev3)
URL : https://patchwork.freedesktop.org/series/122712/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13558_full -> Patchwork_122712v3_full
-Original Message-
From: Andi Shyti
Sent: Thursday, August 24, 2023 7:54 AM
To: Cavitt, Jonathan
Cc: intel-gfx@lists.freedesktop.org; Mistat, Tomasz ;
Vivi, Rodrigo ; Germano, Gregory F
; Roper, Matthew D ;
Das, Nirmoy
Subject: Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Add WABB blit
Hi Jonathan,
> + /* Wa_16018031267, Wa_16018063123 */
> + if (engine->class == COPY_ENGINE_CLASS &&
> + NEEDS_FASTCOLOR_BLT_WABB(i915))
maybe we should have something like
gt_needs_wa_XXX(struct intel_gt *gt)
engine_needs_wa_XXX(struct intel_engine_ce *engine)
Hi Jonathan,
few little things...
On Wed, Aug 23, 2023 at 11:51:03AM -0700, Jonathan Cavitt wrote:
> From: Nirmoy Das
>
> Apply WABB blit for Wa_16018031267 / Wa_16018063123.
> Additionally, update the lrc selftest to exercise the new
> WABB changes.
>
> Signed-off-by: Jonathan Cavitt
>
== Series Details ==
Series: eDP DSC fixes (rev3)
URL : https://patchwork.freedesktop.org/series/122792/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13561 -> Patchwork_122792v3
Summary
---
**SUCCESS**
No
== Series Details ==
Series: eDP DSC fixes (rev3)
URL : https://patchwork.freedesktop.org/series/122792/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning:
== Series Details ==
Series: eDP DSC fixes (rev3)
URL : https://patchwork.freedesktop.org/series/122792/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
On Thu, 2023-08-17 at 18:53 +0300, Jani Nikula wrote:
> Split out register macros to a separate file, and move more color
> register access to intel_color.c.
Reviewed-by: Jouni Högander
for the whole set.
>
> Jani Nikula (6):
> drm/i915/regs: split out intel_color_regs.h
> drm/i915/color:
CEC needs the source physical address. Parsing it is trivial with the
existing EDID CEA DB infrastructure.
Default to CEC_PHYS_ADDR_INVALID (0x) instead of 0 to cater for
easier CEC usage.
Cc: Hans Verkuil
Cc: linux-me...@vger.kernel.org
Signed-off-by: Jani Nikula
---
In the drm subsystem, the source physical address is, in most cases,
available without having to parse the EDID again. Add notes about
preferring to use the pre-parsed address instead.
Cc: Hans Verkuil
Cc: linux-me...@vger.kernel.org
Signed-off-by: Jani Nikula
---
Avoid parsing the EDID again for source physical address. Also gets rids
of a few remaining raw EDID usages.
Cc: Hans Verkuil
Cc: linux-me...@vger.kernel.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 5
== Series Details ==
Series: HDCP MST aux issue fix (rev4)
URL : https://patchwork.freedesktop.org/series/122267/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/122267/revisions/4/mbox/ not
applied
Applying: drm/i915/hdcp: Use intel_connector
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