On Tue, 2023-09-05 at 13:05 +0530, Animesh Manna wrote:
> Modify existing PSR implementation to enable panel replay feature of
> DP 2.0
> which is similar to PSR feature of EDP panel. There is different DPCD
> address to check panel capability compare to PSR and vsc sdp header
> is different.
>
>
== Series Details ==
Series: Add DSC fractional bpp support (rev5)
URL : https://patchwork.freedesktop.org/series/111391/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13617 -> Patchwork_111391v5
Summary
---
**FAILUR
== Series Details ==
Series: Add DSC fractional bpp support (rev5)
URL : https://patchwork.freedesktop.org/series/111391/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add DSC fractional bpp support (rev5)
URL : https://patchwork.freedesktop.org/series/111391/
State : warning
== Summary ==
Error: dim checkpatch failed
212219eebdff drm/display/dp: Add helper function to get DSC bpp prescision
8ca519027e97 drm/i915/display: Store c
This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series: https://patchw
From: Ankit Nautiyal
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.
v2:
-Fixed tu_data calculation while dealing with U6.4 f
From: Vandita Kulkarni
Consider the fractional bpp while reading the qp values.
v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
Signed-off-by: Vandita Kulkarni
Signed-off-by: Ankit Nautiyal
---
.../gpu/drm/i915/display/intel_qp_tables.c| 3 ---
drivers/gpu/drm/i
From: Swati Sharma
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if
From: Ankit Nautiyal
This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 37 ++
From: Swati Sharma
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.
v2:
-Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
-Fix comment (Suraj)
Signed-off-by: S
From: Ankit Nautiyal
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractiona
From: Ankit Nautiyal
Add helper to get the DSC bits_per_pixel precision for the DP sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/display/drm_dp_helper.c | 27 +
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/dri
From: Ankit Nautiyal
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drive
== Series Details ==
Series: drm/i915/spi: spi access for discrete graphics
URL : https://patchwork.freedesktop.org/series/123510/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/spi: spi access for discrete graphics
URL : https://patchwork.freedesktop.org/series/123510/
State : warning
== Summary ==
Error: dim checkpatch failed
eb746b900d2f drm/i915/spi: add spi device for discrete graphics
Traceback (most recent call last):
Fil
Check SPI access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/spi/intel_spi.c | 25
drivers/gpu/drm/i915/spi/intel_spi.h | 1 +
drivers/gpu/drm/i915/s
Enable runtime PM in spi driver to notify i915 that
whole card should be kept awake while spi operations are
performed through this driver.
CC: Lucas De Marchi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 44
1 file changed, 44 inserti
GSC SPI HW errors on quad access overlapping 1K border.
Align 64bit read and write to avoid readq/writeq over 1K border.
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i91
From: Tomas Winkler
Implement mtd read, erase, and write handlers.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-o
From: Tomas Winkler
Register the on-die spi device with the mtd subsystem.
Refcount spi object on _get and _put mtd callbacks.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 118 ++
From: Tomas Winkler
Add auxiliary driver for i915 on-die spi device.
CC: Rodrigo Vivi
Signed-off-by: Tomas Winkler
Signed-off-by: Lucas De Marchi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile| 3 +
drivers/
From: Tomas Winkler
Implement spi_read() spi_erase() spi_write() functions.
CC: Lucas De Marchi
CC: Rodrigo Vivi
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
Signed-off-by: Vitaly Lubart
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 199 +++
1 file cha
From: Tomas Winkler
In i915-spi, there is no access to the spi controller,
the information is extracted form the descriptor region.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 193 +
From: Tomas Winkler
Add the dGFX spi region map and convey it via auxiliary device
to the spi child device.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
---
drivers/gpu/drm/i915/spi/intel_spi.c | 8
drivers/gpu/drm/i915/spi/inte
From: Jani Nikula
Enable access to internal spi on DGFX devices via a child device.
The spi child device is exposed via auxiliary bus.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Jani Nikula
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/Make
Add driver for access to the discrete graphics card
internal SPI device.
Expose device on auxiliary bus and provide driver to register
this device with MTD framework.
This series is intended to be upstreamed through drm tree.
Signed-off-by: Alexander Usyskin
Alexander Usyskin (3):
drm/i915/sp
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