== Series Details ==
Series: ALPM AUX Wake Configuration
URL : https://patchwork.freedesktop.org/series/127954/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14041 -> Patchwork_127954v1
Summary
---
**SUCCESS**
No
== Series Details ==
Series: ALPM AUX Wake Configuration
URL : https://patchwork.freedesktop.org/series/127954/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1:
== Series Details ==
Series: ALPM AUX Wake Configuration
URL : https://patchwork.freedesktop.org/series/127954/
State : warning
== Summary ==
Error: dim checkpatch failed
a8f0d5148cb5 drm/i915/alpm: Add ALPM register definitions
-:10: WARNING:COMMIT_MESSAGE: Missing commit description - Add
== Series Details ==
Series: drm/i915/guc: Add MCR type check for wa registers
URL : https://patchwork.freedesktop.org/series/127935/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14041_full -> Patchwork_127935v1_full
== Series Details ==
Series: Enable Adaptive Sync SDP Support for DP (rev3)
URL : https://patchwork.freedesktop.org/series/126829/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14041 -> Patchwork_126829v3
Summary
---
On Mon, 18 Dec 2023 22:07:38 -0800, Umesh Nerlige Ramappa wrote:
>
> On Mon, Dec 18, 2023 at 09:48:39PM -0800, Dixit, Ashutosh wrote:
> > On Mon, 18 Dec 2023 21:28:33 -0800, Dixit, Ashutosh wrote:
> >>
> >> On Mon, 18 Dec 2023 16:05:43 -0800, Umesh Nerlige Ramappa wrote:
> >> >
> >>
> >> Hi Umesh,
== Series Details ==
Series: Enable Adaptive Sync SDP Support for DP (rev3)
URL : https://patchwork.freedesktop.org/series/126829/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Lunarlake has some configurations in ALPM_CTL register for legacy ALPM as
well. Write these.
Bspec: 71477
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
ALPM Entry Check represents the number of lines needed to put the main link
to sleep and keep it in the sleep state before it can be taken out of the
SLEEP state (eDP requires the main link to be in the SLEEP state for a
minimum of 5us).
Bspec: 71477
Signed-off-by: Jouni Högander
---
Add new alpm_parameters struct into intel_psr for all calculated
alpm parameters.
Signed-off-by: Jouni Högander
---
.../drm/i915/display/intel_display_types.h| 8 --
drivers/gpu/drm/i915/display/intel_psr.c | 28 ++-
2 files changed, 21 insertions(+), 15
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 103 ++
1 file changed, 103 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index efe4306b37e0..9410a43e901b 100644
---
This patch set is adding some missing AUX wake related configuration
for Lunarlake.
Also ALPM parameters are moved to separate struct because amount of
parameters is about to increase in upcoming patches.
Additionally all ALPM related register definitions are added for
Lunarlake.
Jouni Högander
Add necessary functions definitions to enable
and compute AS SDP data. The new `intel_dp_compute_as_sdp`
function computes AS SDP values based on the display
configuration, ensuring proper handling of Variable Refresh
Rate (VRR).
--v2:
- Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit]
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
Add structure representing Adaptive Sync Secondary Data
Packet (AS SDP). Also, add Adaptive Sync SDP logging in
drm_dp_helper.c to facilitate debugging.
--v2:
- Update logging. [Jani, Ankit]
- use as_sdp instead of async [Ankit]
- Correct define placeholders to where it is being actually used.
An Adaptive Sync SDP allows a DP protocol converter to
forward Adaptive Sync video with minimal buffering overhead
within the converter. An Adaptive-Sync-capable DP protocol
converter indicates its support by setting the related bit
in the DPCD register.
Computes AS SDP values based on the
On Mon, Dec 18, 2023 at 09:48:39PM -0800, Dixit, Ashutosh wrote:
On Mon, 18 Dec 2023 21:28:33 -0800, Dixit, Ashutosh wrote:
On Mon, 18 Dec 2023 16:05:43 -0800, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> On XEHP platforms user is not able to find MMIO triggered reports in the
> OA buffer
On Mon, 18 Dec 2023 21:28:33 -0800, Dixit, Ashutosh wrote:
>
> On Mon, 18 Dec 2023 16:05:43 -0800, Umesh Nerlige Ramappa wrote:
> >
>
> Hi Umesh,
>
> > On XEHP platforms user is not able to find MMIO triggered reports in the
> > OA buffer since i915 squashes the context ID fields. These context ID
On Mon, 18 Dec 2023 16:05:43 -0800, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> On XEHP platforms user is not able to find MMIO triggered reports in the
> OA buffer since i915 squashes the context ID fields. These context ID
> fields hold the MMIO trigger markers.
>
> Update logic to not squash
== Series Details ==
Series: drm/i915/perf: Update handling of MMIO triggered reports
URL : https://patchwork.freedesktop.org/series/127946/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14041 -> Patchwork_127946v1
Summary
== Series Details ==
Series: Revert "drm/i915/gt: Temporarily disable CPU caching into DMA for MTL"
(rev3)
URL : https://patchwork.freedesktop.org/series/127763/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14041 -> Patchwork_127763v3
== Series Details ==
Series: drm/i915/hdcp: Fail Repeater authentication if Type1 device not present
(rev5)
URL : https://patchwork.freedesktop.org/series/127414/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14041 -> Patchwork_127414v5
== Series Details ==
Series: drm/i915/guc: Add MCR type check for wa registers
URL : https://patchwork.freedesktop.org/series/127935/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14041 -> Patchwork_127935v1
Summary
== Series Details ==
Series: drm/i915/guc: Add MCR type check for wa registers
URL : https://patchwork.freedesktop.org/series/127935/
State : warning
== Summary ==
Error: dim checkpatch failed
9cab6f43c361 drm/i915/guc: Add MCR type check for wa registers
-:56: WARNING:BRACES: braces {} are
== Series Details ==
Series: Early Transport for Panel Replay and PSR
URL : https://patchwork.freedesktop.org/series/127918/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14040 -> Patchwork_127918v1
Summary
---
== Series Details ==
Series: Early Transport for Panel Replay and PSR
URL : https://patchwork.freedesktop.org/series/127918/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Early Transport for Panel Replay and PSR
URL : https://patchwork.freedesktop.org/series/127918/
State : warning
== Summary ==
Error: dim checkpatch failed
1d6235f22b22 drm: Add eDP 1.5 early transport definition
2127c2ba9e9e drm/i915/psr: Extend SU area to cover
On XEHP platforms user is not able to find MMIO triggered reports in the
OA buffer since i915 squashes the context ID fields. These context ID
fields hold the MMIO trigger markers.
Update logic to not squash the context ID fields of MMIO triggered
reports.
Fixes: cba94bbcff08 ("drm/i915/perf:
On Mon, Dec 18, 2023 at 02:00:10PM +0100, Andrzej Hajda wrote:
> On 15.12.2023 11:59, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On MTL the stolen region starts at offset 8MiB from the start of
> > LMEMBAR. The dma addresses are thus also offset by 8MiB. However the
> > mm_node/etc. is
== Series Details ==
Series: drm/i915/xelpg: Add fake PCH for xelpg
URL : https://patchwork.freedesktop.org/series/127916/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14039 -> Patchwork_127916v1
Summary
---
== Series Details ==
Series: drm/i915/xelpg: Add fake PCH for xelpg
URL : https://patchwork.freedesktop.org/series/127916/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/xe: Fix build without CONFIG_FAULT_INJECTION
URL : https://patchwork.freedesktop.org/series/127911/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/127911/revisions/1/mbox/ not
applied
Applying: drm/xe: Fix build
On Mon, Dec 18, 2023 at 10:51:03AM -0800, Dixit, Ashutosh wrote:
> On Mon, 18 Dec 2023 06:57:14 -0800, Thomas Hellström wrote:
> >
> >
> > On 12/18/23 15:30, Rodrigo Vivi wrote:
> > > Ideally this header could be included without the CONFIG_FAULT_INJECTION
> > > and it would take care itself for
On Mon, Dec 18, 2023 at 04:33:13PM +0530, Haridhar Kalvala wrote:
> Correct the implementation trying to detect MTL PCH with
> the MTL fake PCH id.
>
> On MTL, both the North Display (NDE) and South Display (SDE) functionality
> reside on the same die (the SoC die in this case), unlike many past
Oh, and one more thing I forgot to mention before hitting send...the
title for this patch doesn't make sense. Xe_LPG is the graphics IP used
by MTL; that's completely unrelated to the display IP (which is
Xe_LPD+).
Since we're assigning the fake PCH value based off the platform
(IS_METEORLAKE)
Hi Dave and Sima,
Here goes our latest drm-intel-next pull-request towards 6.8.
drm-intel-next-2023-12-18:
- Drop pointless null checks and fix a scaler bug (Ville)
- Meteor Lake display fixes and clean-ups (RK, Jani, Andrzej, Mika, Imre)
- Clean-up around flip done IRQ (Ville)
- Fix eDP Meteor
Some of the wa registers are MCR registers, which have different
read/write process with normal MMIO registers.
Add function intel_gt_is_mcr_reg to check whether it is mcr register
or not.
Signed-off-by: Shuicheng Lin
Cc: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 27
On Mon, 18 Dec 2023 06:57:14 -0800, Thomas Hellström wrote:
>
>
> On 12/18/23 15:30, Rodrigo Vivi wrote:
> > Ideally this header could be included without the CONFIG_FAULT_INJECTION
> > and it would take care itself for the includes it needs.
> > So, let's temporary workaround this by moving this
Hi Jonathan,
On Tue, Nov 28, 2023 at 08:25:05AM -0800, Jonathan Cavitt wrote:
> Never block for outstanding work on userptr object upon receipt of a
> mmu-notifier. The reason we originally did so was to immediately unbind
> the userptr and unpin its pages, but since that has been dropped in
>
On Wed, 2023-11-15 at 23:21 +0200, Ville Syrjälä wrote:
> On Tue, Nov 14, 2023 at 03:41:41PM +0200, Jouni Högander wrote:
> > After switching to directly using dma_fence instead of
> > i915_sw_fence we
> > have left some dead code around intel_atomic_helper->free_list.
> > Remove that
> > dead
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of
> Patchwork
> Sent: Wednesday, December 13, 2023 11:08 PM
> To: Ville Syrjälä
> Cc: intel-gfx@lists.freedesktop.org
> Subject: ✗ Fi.CI.BAT: failure for drm/i915: Cursor vblank evasion
>
> Patch Details
> Series: drm/i915:
On Tue, 12 Dec 2023, Kai Vehmanen wrote:
> This reverts commit 6fb89f11e23453b081ec4695e5e66ccb4deb2fd0.
>
> Signed-off-by: Kai Vehmanen
> ---
> sound/pci/hda/patch_hdmi.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
> index
On 15.12.2023 11:59, Ville Syrjala wrote:
From: Ville Syrjälä
On MTL the stolen region starts at offset 8MiB from the start of
LMEMBAR. The dma addresses are thus also offset by 8MiB. However the
mm_node/etc. is zero based, and i915_pages_create_for_stolen() will
add the appropriate
-Original Message-
From: Andi Shyti
Sent: Monday, December 18, 2023 8:06 AM
To: Cavitt, Jonathan
Cc: intel-gfx@lists.freedesktop.org; Gupta, saurabhg
; chris.p.wil...@linux.intel.com
Subject: Re: [Intel-gfx] [PATCH] drm/i915/gem: Atomically invalidate userptr on
mmu-notifier
>
> Hi
On 12/18/23 15:30, Rodrigo Vivi wrote:
Ideally this header could be included without the CONFIG_FAULT_INJECTION
and it would take care itself for the includes it needs.
So, let's temporary workaround this by moving this below and including
only when CONFIG_FAULT_INJECTION is selected to avoid
In order to introduce a pwm api which can be used from atomic context,
we will need two functions for applying pwm changes:
int pwm_apply_might_sleep(struct pwm *, struct pwm_state *);
int pwm_apply_atomic(struct pwm *, struct pwm_state *);
This commit just deals with renaming
There is a new register used to configure selective update area size
for early transport.
Configure PIPE_SRCSZ_ERLY_TPT using calculated selective update area
carried in crtc_state->su_area.
Bspec: 68927
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display.c | 10
Check source and sink support for psr2 early transport and enable
it if not disabled by debug flag.
Bspec: 68934
Signed-off-by: Jouni Högander
---
.../drm/i915/display/intel_display_types.h| 16 --
drivers/gpu/drm/i915/display/intel_psr.c | 22 ++-
Early transport validation is currently incomplete. Due to this disable the
feature by default.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
In case early transport is enabled SU area needs to be extended
to cover cursor area fully when cursor is in SU area.
Bspec: 68927
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 38 +++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff
Su_area is needed when configuring CUR_POS_ERLY_TPT and
PIPE_SRC_SZ_ERLY_TPT. Store it into intel_crtc_state->psr2_su_area.
Signed-off-by: Jouni Högander
---
.../drm/i915/display/intel_display_types.h| 2 +
drivers/gpu/drm/i915/display/intel_psr.c | 62 ++-
2 files
New register CUR_POS_ERLY_TPT related to early transport is
supposed to be configured when early transport is in use.
This register is used to configure cursor vertical postion
from beginning of selective update area.
Bspec: 68927
Signed-off-by: Jouni Högander
---
Add DP_PSR_ENABLE_SU_REGION_ET to enable panel early transport.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index
This patch set is implementing driver support for selective update
region early transport for Panel Replay and PSR on Intel hardware.
On Intel hardware selective update area has to cover cursor fully if
selective update region early transport is enabled. This is taken care
in these patches by
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.
On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC die in this case), unlike many past
platforms where the SDE was on a separate PCH die. The code is (badly)
On 15.12.2023 11:59, Ville Syrjala wrote:
From: Ville Syrjälä
When multiple pipes are enabled by the BIOS we try to read out each
in turn. But we do the readout for the second only after the inherited
vma for the first has been rebound into its original place (and thus
the PTEs have been
On Mon, 18 Dec 2023, Kai Vehmanen wrote:
> Hi,
>
> On Mon, 18 Dec 2023, Jani Nikula wrote:
>
>> On Tue, 12 Dec 2023, Kai Vehmanen wrote:
>> > --- a/sound/pci/hda/patch_hdmi.c
>> > +++ b/sound/pci/hda/patch_hdmi.c
>> > @@ -1993,7 +1993,6 @@ static const struct snd_pci_quirk
>> >
On Fri, Dec 15, 2023 at 12:34:48PM +0100, Javier Martinez Canillas wrote:
> Ville Syrjala writes:
>
> Hello Ville,
>
> > From: Ville Syrjälä
> >
> > The original rationale for
> > commit cd456f8d06d2 ("drm: Restrict stackdepot usage to builtin drm.ko")
> > was that depot_save_stack() (which is
Hi,
On Mon, 18 Dec 2023, Jani Nikula wrote:
> On Tue, 12 Dec 2023, Kai Vehmanen wrote:
> > --- a/sound/pci/hda/patch_hdmi.c
> > +++ b/sound/pci/hda/patch_hdmi.c
> > @@ -1993,7 +1993,6 @@ static const struct snd_pci_quirk
> > force_connect_list[] = {
> > SND_PCI_QUIRK(0x103c, 0x871a, "HP",
Ideally this header could be included without the CONFIG_FAULT_INJECTION
and it would take care itself for the includes it needs.
So, let's temporary workaround this by moving this below and including
only when CONFIG_FAULT_INJECTION is selected to avoid build breakages.
Another solution would be
== Series Details ==
Series: drm/i915/display: Remove dead code around
intel_atomic_helper->free_list (rev9)
URL : https://patchwork.freedesktop.org/series/126250/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14034_full -> Patchwork_126250v9_full
== Series Details ==
Series: drm/i915/display: Remove dead code around
intel_atomic_helper->free_list (rev9)
URL : https://patchwork.freedesktop.org/series/126250/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14034 -> Patchwork_126250v9
== Series Details ==
Series: drm/i915/display: Remove dead code around
intel_atomic_helper->free_list (rev9)
URL : https://patchwork.freedesktop.org/series/126250/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
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