> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, April 3, 2024 1:20 AM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 18/22] drm/i915: Handle joined pipes inside
> hsw_crtc_disable()
>
> On Mon, Apr 01, 2024 at 06:46:20AM +, Murthy,
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: c0b832517f627ead3388c6f0c74e8ac10ad5774b Add linux-next specific
files for 20240402
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202404021504.ytp51bl3-...@intel.com
https
have used the drm-misc tree from next-20240402 for today.
--
Cheers,
Stephen Rothwell
pgpHuhSODs95K.pgp
Description: OpenPGP digital signature
On Mon, Apr 01, 2024 at 06:46:20AM +, Murthy, Arun R wrote:
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Ville
> > Syrjala
> > Sent: Friday, March 29, 2024 6:43 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH 18/22] drm/i915: Handle joined pipes inside
>
== Series Details ==
Series: drm/i915/display: fix display param dup for NULL char * params
URL : https://patchwork.freedesktop.org/series/131949/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14516 -> Patchwork_131949v1
== Series Details ==
Series: drm/i915/display: fix display param dup for NULL char * params
URL : https://patchwork.freedesktop.org/series/131949/
State : warning
== Summary ==
Error: dim checkpatch failed
b15c6c58c760 drm/i915/display: fix display param dup for NULL char * params
-:11:
== Series Details ==
Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev3)
URL : https://patchwork.freedesktop.org/series/131700/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14516 -> Patchwork_131700v3
== Series Details ==
Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev3)
URL : https://patchwork.freedesktop.org/series/131700/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Thanks Charlton for the patch.
I think in general it is a good idea to log this when the max rate is
dropped to HBR3 for SST case.
Please find my comments below,
On Thu, Feb 29, 2024 at 11:49 PM Charlton Lin wrote:
>
> Driver currently limits link rate up to HBR3 in SST mode. Log a
> message
== Series Details ==
Series: drm: ensure drm headers are self-contained and pass kernel-doc
URL : https://patchwork.freedesktop.org/series/131944/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14516 -> Patchwork_131944v1
== Series Details ==
Series: drm: ensure drm headers are self-contained and pass kernel-doc
URL : https://patchwork.freedesktop.org/series/131944/
State : warning
== Summary ==
Error: dim checkpatch failed
54d61aa07c56 drm: ensure drm headers are self-contained and pass kernel-doc
Traceback
On Tue, 02 Apr 2024, Easwar Hariharan wrote:
> On 4/2/2024 7:32 AM, Jani Nikula wrote:
>> On Tue, 02 Apr 2024, Easwar Hariharan wrote:
>>> On 4/2/2024 12:48 AM, Jani Nikula wrote:
On Fri, 29 Mar 2024, Easwar Hariharan wrote:
> I2C v7, SMBus 3.2, and I3C specifications have replaced
On Tue, 02 Apr 2024, Lucas De Marchi wrote:
> On Tue, Apr 02, 2024 at 06:55:34PM +0300, Jani Nikula wrote:
>>The display param duplication deviates from the original param
>>duplication in that it converts NULL params to to allocated empty
>>strings. This works for the vbt_firmware parameter, but
== Series Details ==
Series: drm/i915: Bigjoiner prep work
URL : https://patchwork.freedesktop.org/series/131942/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Bigjoiner prep work
URL : https://patchwork.freedesktop.org/series/131942/
State : warning
== Summary ==
Error: dim checkpatch failed
79f3132bda07 drm/i915: Remove DRM_MODE_FLAG_DBLSCAN checks from .mode_valid()
hooks
24b6b2eb8c3b drm/i915: Shuffle DP
On Tue, Apr 02, 2024 at 06:55:34PM +0300, Jani Nikula wrote:
The display param duplication deviates from the original param
duplication in that it converts NULL params to to allocated empty
strings. This works for the vbt_firmware parameter, but not for
dmc_firmware_path, the user of which
The display param duplication deviates from the original param
duplication in that it converts NULL params to to allocated empty
strings. This works for the vbt_firmware parameter, but not for
dmc_firmware_path, the user of which interprets NULL and the empty
string as distinct values.
From: Ville Syrjälä
if the new dbuf slices are a superset of the old
dbuf slices then we don't have to do anything in
intel_dbuf_post_plane_update(). Restructure the code
to skip such redundant dbuf slice updates. The main
benefit is slightly less confusing logs.
Reviewed-by: Uma Shankar
From: Ville Syrjälä
No point in throwing around u8 when we're dealing with
just an integer. Use a plain old boring 'int'.
Reviewed-by: Uma Shankar
Reviewed-by: Gustavo Sousa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
From: Stanislav Lisovskiy
Currently we can't change MBUS join status without doing a modeset,
because we are lacking mechanism to synchronize those with vblank.
However then this means that we can't do a fastset, if there is a need
to change MBUS join state. Fix that by implementing such change.
From: Ville Syrjälä
The current cdclk/mbus programming sequence is as follows:
1. intel_set_cdclk_pre_plane_update()
2. update_mbus_pre_enable()
3. intel_set_cdclk_post_plane_update()
when the actual mdclk/cdclk programming is postponed to
intel_set_cdclk_post_plane_update() we must keep using
From: Stanislav Lisovskiy
In order to make sure we are not breaking the proper sequence
let's do updates step by step and don't change MBUS join value
during MDCLK/CDCLK programming stage.
MBUS join programming would be taken care by pre/post ddb hooks.
v2: - Reworded comment about using old
From: Ville Syrjälä
Add some debugs so that we can actually observe what is
actually happening during the mbus/dbuf programming steps.
We can just shove them into fairly low level functions as
none of them are called during any critical sections/etc.
Reviewed-by: Uma Shankar
Reviewed-by:
From: Ville Syrjälä
Extract the stuff that writes the dbuf/mbus ratio stuff
into its own function. Will help with correctly sequencing
the operations done during mbus programming.
Reviewed-by: Uma Shankar
Reviewed-by: Gustavo Sousa
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Extact the stuff that writes the joining bits in MBUS_CTL
into its own function. Will help with correctly sequencing
the operations done during mbus programming.
Reviewed-by: Uma Shankar
Reviewed-by: Gustavo Sousa
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
intel_mbus_dbox_update() will become static soon. Relocate it
into a place that avoids having to add a forward declaration
for it.
Reviewed-by: Uma Shankar
Reviewed-by: Gustavo Sousa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 166
From: Stanislav Lisovskiy
We need to loop through all active pipes, not just the ones, that
are in current state, because disabling and enabling even a particular
pipe affects credits in another one.
Reviewed-by: Uma Shankar
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Currently we just get a plain "Changing CDCLK to ..." in the
logs. It would actually be interesting to see whether we're
doing the programming during the pre or post plane phase of
the commit. Include that information in the debug message.
Reviewed-by: Uma Shankar
From: Ville Syrjälä
No one ever figured out why bumping the cdclk helped
with whatever issue we were having at the time.
Remove the hacks and start from scratch so that we
can actually see if any problems still remain.
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Currently we only consider the relationship of the
old and new CDCLK frequencies when determining whether
to do the repgramming from intel_set_cdclk_pre_plane_update()
or intel_set_cdclk_post_plane_update().
It is technically possible to have a situation where the
CDCLK
From: Ville Syrjälä
Currently we always reprogram CDCLK from the
intel_set_cdclk_pre_plane_update() when using squash/crawl.
The code only works correctly for the cd2x update or full
modeset cases, and it was simply never updated to deal with
squash/crawl.
If the CDCLK frequency is increasing
From: Ville Syrjälä
Get rid of the full modeset requirement for changing mbus
joining. Things got quite a bit more complicated than
originally envisioned due to the dynamic cdclk/mdclk ratio.
Sadly we have to do a fairly careful dance between the
dbuf and cdclk code to make sure everything is
On Fri, Mar 29, 2024 at 02:04:55PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjala (2024-03-27 14:45:33-03:00)
> >From: Ville Syrjälä
> >
> >Currently we only consider the relationship of the
> >old and new CDCLK frequencies when determining whether
> >to do the repgramming from
On Fri, Mar 29, 2024 at 03:23:34PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjala (2024-03-27 14:45:43-03:00)
> >From: Ville Syrjälä
> >
> >No point in throwing around u8 when we're dealing with
> >just an integer. Use a plain old boring 'int'.
>
> Learned and noted :-)
>
> Thanks for
On Tue, 02 Apr 2024, Easwar Hariharan wrote:
> On 4/2/2024 12:48 AM, Jani Nikula wrote:
>> On Fri, 29 Mar 2024, Easwar Hariharan wrote:
>>> I2C v7, SMBus 3.2, and I3C specifications have replaced "master/slave"
>>> with more appropriate terms. Inspired by and following on to Wolfram's
>>> series
On Fri, Mar 29, 2024 at 03:15:02PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjala (2024-03-27 14:45:42-03:00)
> >@@ -3663,24 +3659,42 @@ static void
> >intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
> > intel_atomic_get_old_dbuf_state(state);
> >
Ensure drm headers build, are self-contained, have header guards, and
have no kernel-doc warnings, when CONFIG_DRM_HEADER_TEST=y.
The mechanism follows similar patters used in i915, xe, and usr/include.
To cover include/drm, we need to recurse there using the top level
Kbuild and the new
From: Ville Syrjälä
There is no reason to make this debugfs file for a simple
boolean so complicated. Just use debugfs_create_bool().
Reviewed-by: Arun R Murthy
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_debugfs.c | 44 +--
1 file changed, 2
From: Ville Syrjälä
The MST code currently assumes that glk+ already supports MST+DSC,
which is incorrect. We need to check for TGL+ actually. ICL does
support SST+DSC, but supposedly it can't do MST+FEC which will
also rule MST+DSC.
Note that a straight TGL+ check doesn't work here because DSC
From: Ville Syrjälä
ICL supposedly doesn't support FEC on MST. Reject it.
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
From: Ville Syrjälä
Move some of the more trivial checks in the DP .mode_valid()
hooks upwards to lessen the noise amongst the more complex
checks.
Reviewed-by: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
From: Ville Syrjälä
Simplify our life by extracting the "do we need the glk scaler
clock gating w/a?" check into a small helper.
Reviewed-by: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 16 ++--
1 file changed, 10
From: Ville Syrjälä
glk_pipe_scaler_clock_gating_wa() is messy. Clean it up via
intel_de_rmw(), and also just pass in the whole crtc so the
caller doesn't have to dance around so much.
Reviewed-by: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
An extract of the large bigjoiner series, containing:
- the pure refactoring patches not directly related to bigjoiner
- Reject MST+DSC/FEC on ICL
- tweak the debugfs i915_bigjoiner_force_enable file
(needs corresponding IGT changes).
Test-with:
From: Ville Syrjälä
We never set connector->doublescan_allowed, so the probe helper
already filters out all doublescan modes for us.
Sadly we still need to keep the explicit doublescan checks
in .compute_config as outlined in commit e4dd27aadd20
("drm/i915: Allow DBLSCAN user modes with
On Fri, Mar 29, 2024 at 11:39:39AM -0700, Manasi Navare wrote:
> Hi Imre,
>
> While we are adding these checks here for DSC for MST, I see that in
> intel_dp_mst_mode_valid_ctx() we still check against DISPLAY_VER() >
> 10 for checking for DSC where as in all other places we rely on
> runtime
== Series Details ==
Series: Panel replay selective update support (rev4)
URL : https://patchwork.freedesktop.org/series/128193/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14515 -> Patchwork_128193v4
Summary
---
== Series Details ==
Series: Panel replay selective update support (rev4)
URL : https://patchwork.freedesktop.org/series/128193/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Panel replay selective update support (rev4)
URL : https://patchwork.freedesktop.org/series/128193/
State : warning
== Summary ==
Error: dim checkpatch failed
a184a7194320 drm/i915/psr: Add some documentation of variables used in psr code
12561b72f253
Hello,
There is an upcoming planned shutdown in Intel labs due to mandatory
building maintenance. We will disable CI pipelines 8am CEST April 12th
and enable them back as soon as possible on Monday, April 15th.
Please plan your work accordingly :)
Thanks, Ryszard
On Mon, 2024-02-05 at 04:50 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Friday, February 2, 2024 1:17 PM
> > To: Manna, Animesh ; intel-
> > g...@lists.freedesktop.org
> > Subject: Re: [PATCH v3 04/21] drm/i915/psr: Rename
> >
We are re-using PSR module parameters for panel replay. Update module
parameter descriptions with panel replay information:
enable_psr:
-1 (default) == follow what is in VBT
0 == disable PSR/PR
1 == Allow PSR1 and PR full frame update
2 == allow PSR1/PSR2 and PR Selective Update
Add panel replay selective update support to debugfs status interface. In
case of sink supporting panel replay we will print out:
Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes
and PSR mode will look like this if printing out enabled panel replay
selective
Part of intel_psr2_config_valid is valid for panel replay. rename it as
intel_sel_update_config_valid. Split psr2 specific part and name it as
intel_psr2_config_valid.
v3:
- move early transport check to psr2 specific check
- check intel_psr2_config_valid only for non-Panel Replay case
v2:
There are some workarounds that are not applicable for panel replay. Do not
apply these if panel replay is used.
Bspec: 66624, 50422
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
DP Panel replay uses SRD_STATUS to track it's status despite selective
update mode.
Bspec: 53370, 68920
v2:
- use intel_dp_is_edp to differentiate
- modify debugfs status as well
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 8 +---
1 file changed, 5
Add new boolean to store panel replay selective update support of sink into
intel_psr struct. Detect panel replay selective update support and store
it into this new boolean.
v3: Clear sink_panel_replay_su_support in intel_dp_detect
v2: Merge adding new boolean into this patch
Signed-off-by:
Currently intel_dp_get_su_granularity doesn't support panel replay.
This fix modifies it to support panel replay as well.
v2: rely on PSR definitions on common bits
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 62
Add definitions for panel replay selective update
v2: Remove unnecessary Cc from commit message
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
include/drm/display/drm_dp.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/display/drm_dp.h
We are about to reuse psr2_enabled for panel replay as well. Rename
it as sel_update_enabled to avoid confusion.
v3: Rebase
v2: Rebase
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_psr.c
We are going to reuse has_psr2 for panel_replay as well. Rename it
as has_sel_update to avoid confusion.
v2: Rebase
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 10 +-
drivers/gpu/drm/i915/display/intel_display.c
Panel replay has to be enabled on sink side before link training. Take this
into account in fastset check and in initial fastset check.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 12
Unify enabling and disabling of psr/panel replay for a sink. Modify
intel_psr_enable_sink accordingly and use it for both cases.
v3:
- move psr2_su_region_et_valid to be check for PSR2 only
v2:
- enable panel replay for sink before link training
- write ALPM_CONFIG only for PSR
- add
Currently panel replay is supporting only main link on mode -> Do not
update phy power state for non-eDP panel replay.
Bspec: 53370
v2: use intel_dp_is_edp to differentiate
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 12
1 file changed, 8
Currently panel replay dpcd capability isn't properly checked after
plugging in DP panel. Fix this by calling intel_psr_init_dpcd in
intel_dp_detect.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Bspec is saying this
mask register: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug]
are used in panel replay mode.
Status register: Only SRD_STATUS[SRD state] field is used in panel replay
mode.
Due to this stop writing and reading registers and bits not used by panel
replay if panel
On HPD interrupt we want to check if the reason for HPD was some panel
replay error detected by monitor/panel. This is already done for PSR. We
want to do this for panel replay as well. Modify intel_psr_short_pulse to
support panel replay as well.
Signed-off-by: Jouni Högander
Reviewed-by:
Currently intel_psr_pause and intel_psr_resume do nothing in case of panel
replay. Change them to perform pause and return also in case of panel
replay.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
1 file changed, 2
Current code is setting only intel_crtc_state->has_panel_replay in panel
replay case. There are lots of stuff behind intel_crtc_state->has_psr that
is needed for panel replay as well. Instead of converting each check to
has_psr || has_panel_replay set has_psr in case of panel replay as
well. Code
This patch set is implementing panel replay selective update support
for Intel hardware.
It is also fixing several exisiting issues in current panel replay
implementation:
Several needed functions are not executed for panel replay
Ensure link training follows enabling panel replay on sink side
We are adding more boolean variable into intel_psr and intel_crtc_state
structs. Add some documentation about these for sake of clarity.
v2: Modify has_psr + has_panel_replay to mean panel replay
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
On Thu, 2024-03-28 at 05:33 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Friday, March 22, 2024 4:00 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Ville Syrjälä ; Manna, Animesh
> > ; Murthy, Arun R
> > ;
> > Hogander, Jouni
> >
On Thu, 21 Mar 2024, Jani Nikula wrote:
> Jani Nikula (4):
> drm/edid: add drm_edid_get_product_id()
> drm/edid: add drm_edid_print_product_id()
> drm/i915/bios: switch to struct drm_edid and struct
> drm_edid_product_id
> drm/i915/bios: return drm_edid_product_id from
On Fri, 22 Mar 2024, Lucas De Marchi wrote:
> oh, now I understand. You mean that xe module doesn't have the param
> because it's only declared in drivers/gpu/drm/i915/i915_params.c.
>
> Could you extend the commit message with something like this?
>
> The dmc_firmware_path parameter is
[Adding a few folks and list while dropping the stable list, as this is
unrelated to it]
On 31.03.24 07:59, Andrei Gaponenko wrote:
>
> I noticed a regression with the mailine kernel pre-compiled by EPEL.
> I have just tried linux-6.9-rc1.tar.gz from kernel.org, and it still
> misbehaves.
>
>
On Thu, 28 Mar 2024, "Arnd Bergmann" wrote:
> On Thu, Mar 28, 2024, at 11:46, Jani Nikula wrote:
>> On Thu, 28 Mar 2024, "Arnd Bergmann" wrote:
>>> On Thu, Mar 28, 2024, at 11:24, Jani Nikula wrote:
Use localized __diag_push(), __diag_ignore_all() with rationale, and
__diag_pop() for
Hi Pekka,
On Tue, Apr 02, 2024 at 10:46:08AM +0300, Pekka Paalanen wrote:
> On Tue, 26 Mar 2024 11:42:48 -0400 Christopher Michael wrote:
>
> > The 2024 X.Org Foundation membership renewal period has been extended
> > one additional week and elections will start the following week on 01
> >
On Fri, 29 Mar 2024, Easwar Hariharan wrote:
> I2C v7, SMBus 3.2, and I3C specifications have replaced "master/slave"
> with more appropriate terms. Inspired by and following on to Wolfram's
> series to fix drivers/i2c/[1], fix the terminology for users of
> I2C_ALGOBIT bitbanging interface, now
On Tue, 26 Mar 2024 11:42:48 -0400
Christopher Michael wrote:
> The 2024 X.Org Foundation membership renewal period has been extended
> one additional week and elections will start the following week on 01
> April 2024.
>
> Please note that only current members can vote in the upcoming
Hello Ville, Thank you very much for the series. 6K detects fine and works.
Tested-by: Vidya Srinivas
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Friday, March 29, 2024 6:43 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 22/22] drm/i915: Use
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