[Intel-gfx] [PATCH 1/3] [v2] drm: Add new DRM_IOCTL_MODE_GETPLANE2

oishbar.org> Cc: "Kristian H. Kristensen" <hoegsb...@gmail.com> References: https://patchwork.kernel.org/patch/9482393/ Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- drivers/gpu/drm/arc/arcpgu_crtc.c | 1 + drivers/gpu/drm/arm/hdlcd_crtc.c|

Re: [Intel-gfx] [PATCH 1/1] drm/i915: Copy user requested buffers into the error state

arlier patch by Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> (v1) Cc: Ben Widawsky <b...@bwidawsk.net> Cc: Matt Turner <matts...@gmail.com> Cc: Abdiel Janulgue <abdiel.janul...@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add format modifiers for Intel

On 17-01-12 20:32:07, Ville Syrjälä wrote: On Thu, Jan 12, 2017 at 10:00:55AM -0800, Ben Widawsky wrote: On 17-01-12 12:51:20, Ville Syrjälä wrote: >On Wed, Jan 11, 2017 at 04:51:17PM -0800, Ben Widawsky wrote: >> This was based on a patch originally by Kristian. It has been modified

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add format modifiers for Intel

On 17-01-12 12:51:20, Ville Syrjälä wrote: On Wed, Jan 11, 2017 at 04:51:17PM -0800, Ben Widawsky wrote: This was based on a patch originally by Kristian. It has been modified pretty heavily to use the new callbacks from the previous patch. Cc: Kristian H. Kristensen <hoegsb...@gmail.

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for GET_PLANE2 w/ i915 implementation

This is expected because it's based on Ville's patch series to define the new modifiers. On 17-01-12 01:01:31, Patchwork wrote: == Series Details == Series: GET_PLANE2 w/ i915 implementation URL : https://patchwork.freedesktop.org/series/17873/ State : failure == Summary == LD [M]

[Intel-gfx] [PATCH 0/3] GET_PLANE2 w/ i915 implementation

ube) https://github.com/bwidawsk/kmscube/commit/55519640f5a1a21983e267fb39e4cf48f6312ef9 References: (libdrm) https://lists.freedesktop.org/archives/dri-devel/2016-December/127942.html Ben Widawsky (3): drm: Add new DRM_IOCTL_MODE_GETPLANE2 drm/i915: Add format modifiers for Intel

[Intel-gfx] [PATCH 3/3] drm/i915: Add support for GET_PLANE2 CCS modifiers

Cc: Kristian Høgsberg <k...@bitplanet.net> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- drivers/gpu/drm/i915/intel_display.c | 10 -- drivers/gpu/drm/i915/intel_sprite.c | 2 ++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/int

[Intel-gfx] [PATCH 1/3] drm: Add new DRM_IOCTL_MODE_GETPLANE2

array a sentinel based structure instead of a sized one. Upon discussion on IRC, it was determined that having an invalid modifier might make sense in general as well. References: https://patchwork.kernel.org/patch/9482393/ Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- drivers/gpu/d

[Intel-gfx] [PATCH 2/3] drm/i915: Add format modifiers for Intel

This was based on a patch originally by Kristian. It has been modified pretty heavily to use the new callbacks from the previous patch. Cc: Kristian H. Kristensen <hoegsb...@gmail.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- drivers/gpu/drm/i915/intel_dis

Re: [Intel-gfx] [PATCH v6] drm: add fourcc codes for 16bit R and RG

On 17-01-11 17:05:04, Ville Syrjälä wrote: On Thu, Jan 05, 2017 at 02:45:37PM +0100, Christian König wrote: Am 05.01.2017 um 12:37 schrieb Ville Syrjälä: > On Wed, Jan 04, 2017 at 07:38:55PM +0100, Rainer Hochecker wrote: >> From: Rainer Hochecker >> >> This adds fourcc

Re: [Intel-gfx] [PATCH 0/9] drm/i915: SKL+ render decompression support

would be hard to figure out which parts came from where. Entire series available here: git://github.com/vsyrjala/linux.git fb_format_dedup_4_ccs Cc: Vandana Kannan <vandana.kan...@intel.com> Cc: Daniel Vetter <dan...@ffwll.ch> Cc: Ben Widawsky <b...@bwidawsk.net> Cc: Jason Ekstrand &

Re: [Intel-gfx] [PATCH 8/9] drm/i915: Implement .get_format_info() hook for CCS

ndana.kan...@intel.com> Cc: Daniel Vetter <dan...@ffwll.ch> Cc: Ben Widawsky <b...@bwidawsk.net> Cc: Jason Ekstrand <ja...@jlekstrand.net> Reviewed-by: Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> ---

Re: [Intel-gfx] [PATCH 9/9] drm/i915: Add render decompression support

g. 90/270 degree rotation is not supported in combination with decompression either. This patch may contain work from at least the following people: * Vandana Kannan <vandana.kan...@intel.com> * Daniel Vetter <dan...@ffwll.ch> * Ben Widawsky <b...@bwidawsk.net> Cc: Vandana Ka

Re: [Intel-gfx] [PATCH 1/9] drm: Add mode_config .get_format_info() hook

aurent) Don't pass 'dev' to the new hook (Laurent) Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com> Cc: Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> --- drivers/gpu/drm/drm_fb_cma_helper.c | 2 +- drivers/gpu/drm/d

Re: [Intel-gfx] [PATCH] drm/i915: Update SKL SRV GT4 pci ids reference.

On 17-01-03 11:27:52, Rodrigo Vivi wrote: No functional changes. Apparently spec has been changed the valid table showing 0x192A as Server GT4 while 0x193A is Server GT4e. Libdrm and Mesa already have this right. So let's fix the ref here. Cc: Ben Widawsky <benjamin.widaw...@intel.com>

Re: [Intel-gfx] [PATCH] drm/i915: Copy user requested buffers into the error state

ss/drm/cardN/error) following a GPU hang involving this batch. Use this at your discretion, the contents of the error state. although compressed, are allocated with GFP_ATOMIC (i.e. limited) and kept for all eternity (until the error state is destroyed). Based on an earlier patch by Ben Widaw

Re: [Intel-gfx] [PATCH i-g-t v1] tests/kms_ccs: Add test for render compression

Acked-by: Ben Widawsky <b...@bwidawsk.net> On 16-12-06 16:06:50, Tomeu Vizoso wrote: Add a few subtests that check that lossless compressed render targets are properly displayed. Also test a few error conditions. Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Cc: Ben

Re: [Intel-gfx] [Mesa-dev] [PATCH 00/27] Renderbuffer Decompression (and GBM modifiers)

On 16-12-29 17:34:19, Ben Widawsky wrote: On 16-12-06 13:34:02, Paulo Zanoni wrote: 2016-12-01 20:09 GMT-02:00 Ben Widawsky <benjamin.widaw...@intel.com>: From: Ben Widawsky <b...@bwidawsk.net> This patch series ultimately adds support within the i965 driver for Renderbuffer D

Re: [Intel-gfx] [Mesa-dev] [PATCH 00/27] Renderbuffer Decompression (and GBM modifiers)

On 16-12-06 13:34:02, Paulo Zanoni wrote: 2016-12-01 20:09 GMT-02:00 Ben Widawsky <benjamin.widaw...@intel.com>: From: Ben Widawsky <b...@bwidawsk.net> This patch series ultimately adds support within the i965 driver for Renderbuffer Decompression with GBM. In short, this fea

Re: [Intel-gfx] [PATCH 37/37] drm/i915: Implement .get_format_info() hook for CCS

e wise. Cc: Ben Widawsky <b...@bwidawsk.net> Cc: intel-gfx@lists.freedesktop.org Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> I have a comment below however, you can consider it: Reviewed-by: Ben Widawsky <b...@bwidawsk.net> --- drivers/gpu/drm/i

[Intel-gfx] [PATCH] intel: Add Geminilake PCI IDs

From: Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- intel/intel_chipset.h | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 514f659..41fc0da 100644

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Try to print INSTDONE bits for all slice/subslice

On 16-09-15 17:30:10, Mika Kuoppala wrote: Imre Deak <imre.d...@intel.com> writes: From: Ben Widawsky <benjamin.widaw...@intel.com> v2: (Imre) - Access only subslices that are known to exist. - Reset explictly the MCR selector to slice/sub-slice ID 0 after the readout. - Use

Re: [Intel-gfx] [PATCH] drm/i915: Add missing ring_mask to Pineview

add a WARN_ON() if we find > > > > ourselves with a device without any rings. > > > > > > > > Fixes: 73ae478cdf6a ("drm/i915: Replace has_bsd/blt/vebox with a mask") > > > > Fixes: 88d2ba2e95c8 ("drm/i915: Unify engine init loop&

Re: [Intel-gfx] [PATCH i-g-t] assembler/: Fix lex warnings for %empty and %nonassoc.

> | ABS { $$ = 1; } > > ; > > > > -execsize: /* empty */ %prec EMPTEXECSIZE > > +execsize: %empty /* empty */ %prec EMPTEXECSIZE > > { > > $$ = ffs(program_defaults.execute_

Re: [Intel-gfx] [PATCH] drm/i915: Provide a modparam to disable firmware loading

On Thu, Apr 14, 2016 at 11:27:25AM +0300, Jani Nikula wrote: > On Wed, 13 Apr 2016, Ben Widawsky <b...@bwidawsk.net> wrote: > > +module_param_named_unsafe(disable_firmware_loading, > > i915.disable_firmware_loading, uint, 0400); > > +MODULE_PARM_DESC(disable_firmwa

Re: [Intel-gfx] [PATCH] drm/i915/skl: Update eDRAM calculation

On Thu, Apr 14, 2016 at 07:48:13AM -0700, Ben Widawsky wrote: > On Thu, Apr 14, 2016 at 11:14:48AM +0300, Jani Nikula wrote: > > On Thu, 14 Apr 2016, Jani Nikula <jani.nik...@linux.intel.com> wrote: > > > On Wed, 13 Apr 2016, Ben Widawsky <b...@bwidawsk.net> wr

Re: [Intel-gfx] [PATCH] drm/i915/skl: Update eDRAM calculation

On Thu, Apr 14, 2016 at 11:14:48AM +0300, Jani Nikula wrote: > On Thu, 14 Apr 2016, Jani Nikula <jani.nik...@linux.intel.com> wrote: > > On Wed, 13 Apr 2016, Ben Widawsky <b...@bwidawsk.net> wrote: > >> The two behavioral changes here are the correct detection of the

Re: [Intel-gfx] [PATCH] drm/i915: Provide a modparam to disable firmware loading

On Wed, Apr 13, 2016 at 06:45:32PM +0100, Dave Gordon wrote: > On 13/04/16 17:57, Ben Widawsky wrote: > > For debug and development purposes only. > > > > Cc: Mika Kuoppala <mika.kuopp...@intel.com> > > Signed-off-by: Ben Widawsky <b...@bwidawsk.net

[Intel-gfx] [PATCH] drm/i915: Provide a modparam to disable firmware loading

For debug and development purposes only. Cc: Mika Kuoppala <mika.kuopp...@intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- drivers/gpu/drm/i915/i915_debugfs.c | 13 + drivers/gpu/drm/i915/i915_gpu_error.c | 3 +++ drivers/gpu/drm/i915/i915_params

[Intel-gfx] [PATCH] drm/i915/skl: Update eDRAM calculation

The two behavioral changes here are the correct detection of the eDRAM size on gen9 (SKL + KBL), and unconditional printing of the eLLC size. Cc: Eero Tamminen <eero.t.tammi...@intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- drivers/gpu/drm/i915/intel_u

Re: [Intel-gfx] [PATCH 2/2] drm/i915/skl: Fix spurious gpu hang with gt3/gt4 revs

red this with this big > blanket back then already, as E0 vs F0 discrepancy was suspicious > enough. > > Previously the WaForceEnableNonCoherent has been tied to > context non-coherence, atleast in relevant hsds. So keep this tie > and extended this alongside. > > Cc: Abdiel

[Intel-gfx] [PATCH 2/2] intel_gpu_top: Add param to force ring reads for busyness

Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- man/intel_gpu_top.man | 3 +++ tools/intel_gpu_top.c | 25 + 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/man/intel_gpu_top.man b/man/intel_gpu_top.man index d90a7ee..be0f1be 100644 ---

[Intel-gfx] [PATCH 1/2] intel_gpu_top: Skip head/tail reads on HSW

down by default on HSW, and prints a warning. An upcoming patch will provide an override for the insane. References: https://lists.freedesktop.org/archives/mesa-dev/2013-July/041692.html Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- man/intel_gpu_top.man | 2 ++ tools/intel_gpu_top.

[Intel-gfx] [PATCH] Add missing SKL PCI ID

Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- src/i915_pciids.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/i915_pciids.h b/src/i915_pciids.h index f970209..4d1c11d 100644 --- a/src/i915_pciids.h +++ b/src/i915_pciids.h @@ -279,7 +279,8 @@ #

Re: [Intel-gfx] [PATCH] [v2] drm/i915: Check for get_pages instead of shmem (filp)

Do you guys get the CI mails? This version has regressions. v1 did not. I don't know what to trust. On Tue, Feb 09, 2016 at 11:44:12AM -0800, Ben Widawsky wrote: > This behavior of checking for a shmem backed GEM object was introduced here: > commit 4c914c0c7c787b8f730128a8cdcca9c50b

Re: [Intel-gfx] [PATCH] [v2] drm/i915: Check for get_pages instead of shmem (filp)

On Wed, Feb 10, 2016 at 04:23:08PM +, Chris Wilson wrote: > On Wed, Feb 10, 2016 at 07:42:23AM -0800, Ben Widawsky wrote: > > Do you guys get the CI mails? This version has regressions. v1 did not. I > > don't > > know what to trust. > > I didn't even see v2 its

[Intel-gfx] [PATCH] [v2] drm/i915: Check for get_pages instead of shmem (filp)

ordon <david.s.gor...@intel.com> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> Tested-by: Jordan Justen <jordan.l.jus...@intel.com> (v1) Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com> (v1) --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed,

Re: [Intel-gfx] [PATCH] drm/i915: Check for get_pages instead of shmem (filp)

On Tue, Feb 09, 2016 at 11:30:34AM +, Dave Gordon wrote: > On 09/02/16 00:20, Kristian Høgsberg wrote: > >On Fri, Feb 5, 2016 at 5:48 PM, Ben Widawsky > ><benjamin.widaw...@intel.com> wrote: > >>This behavior of checking for a shmem backed GEM object w

[Intel-gfx] [PATCH] drm/i915: Check for get_pages instead of shmem (filp)

t from a change, but whatever. NOTE: I manually retyped this from a test machine. So I haven't even compiled this exact patch. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Kristian Høgsberg <k...@bitplanet.net> Cc: Jordan Justen <jordan.l.jus...@intel.com> Signed-off-by: Ben

Re: [Intel-gfx] [PATCH] drm/i915: Make wa_tail_dwords flexible for future platforms.

rms. > > Cc: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Ben Widawsky <benjamin.widaw...@intel.com> > > Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> I don't claim to understand the reason this patch ends up being required, but it looks fine to me. I wo

[Intel-gfx] [PATCH 4/5] drm/i915: Add basic execlist info to error state

3 Status: 0x00010018 Context 4 Status: 0x0001 Context 5 Status: 0x009d0018 hangcheck: hung [40] bsd command stream: START: 0x00039000 HEAD: 0x0018 ... Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- drivers/gpu/drm/i915/i915_d

[Intel-gfx] [PATCH 5/5] drm/i915: Use CSB helper in debugfs

Since we extracted it for use in error state, we may as well use it in debugfs too. Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugf

[Intel-gfx] [PATCH 2/5] drm/i915: Change WARN to ERROR in CSB count

There is no point in emitting a WARN since the backtrace will always be the same. Errors have actually become easier to spot given the large number of WARNs which exist today in modesetting paths. Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- drivers/gpu/drm/i915/intel_lrc

[Intel-gfx] [PATCH 3/5] drm/i915: Extract CSB status read

This is a useful thing to have around as a function because the mechanism may change in the future. There is a net increase in LOC here, and it will continue to be the case on GEN8 and GEN9 - but future GENs may have an alternate mechanism for doing this. Signed-off-by: Ben Widawsky

[Intel-gfx] [PATCH 0/5] Some minor CSB/execlist stuff

as much as possible - but I'll live without it. Ben Widawsky (5): drm/i915: Cleanup some of the CSB handling drm/i915: change WARN to ERROR in CSB count drm/i915: Extract CSB status read drm/i915: Add basic execlist info to error state drm/i915: Use CSB helper in debugfs drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/5] drm/i915: Cleanup some of the CSB handling

_buffer. This is safe because right above this, we already did a modulus operation. Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- drivers/gpu/drm/i915/intel_lrc.c| 15 +-- drivers/gpu/drm/i915/intel_lrc.h| 18

Re: [Intel-gfx] Suspend To RAM failure in >= 4.1 - bissected to "drm/i915: Track GEN6 page table usage"

On Mon, Jan 04, 2016 at 09:12:11PM +0100, Pavel Machek wrote: > Hi! > > > > I then ran a git bissect between v4.0 and v4.1 from Linus's tree and > > > found the "guilty" commit was > > > > > > commit 317b4e903636305cfe702ab3e5b3d68547a69e72 >

[Intel-gfx] [PATCH] drm/i915: Fix whitespace (trivial)

Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index ca5c0e8..973487a 100644 --- a/drivers/gpu/dr

Re: [Intel-gfx] [PATCH] [v2] drm/i915: Limit VF cache invalidate workaround usage to gen9

On Thu, Dec 17, 2015 at 10:49:24PM +0200, Imre Deak wrote: > On Thu, 2015-12-17 at 09:49 -0800, Ben Widawsky wrote: > > It is unclear if this is even required on BXT. > > I'm not sure either, I only added it on the premise that it was marked > as SKL+ originally in BSpec. The

[Intel-gfx] [PATCH] drm/i915: HWSTAM is not a thing on SKL+

Compile tested only. Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 42a7be1..a9bc207

[Intel-gfx] [PATCH] drm/i915: Limit VF cache invalidate workaround usage to gen9

It is unclear if this is even required on BXT. Cc: Imre Deak <imre.d...@intel.com> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH] drm/i915: Correct MI_STORE_DWORD_INDEX usage

patch just clears up the confusion. NOTE: This patch was compile tested only. NOTE2: The modern docs call it MI_STORE_DATA_INDEX not MI_STORE_DWORD_INDEX Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: Ben Widawsky <benjam

Re: [Intel-gfx] [PATCH] drm/i915: Correct MI_STORE_DWORD_INDEX usage

On Wed, Dec 16, 2015 at 12:18:20AM +, Chris Wilson wrote: > On Tue, Dec 15, 2015 at 04:13:49PM -0800, Ben Widawsky wrote: > > This has been incorrect since the original commit from Oscar Mateo here: > > commit 4da46e1e5bb7e7396fad172cdaffbe496562f3d8 > > Author:

Re: [Intel-gfx] [PATCH 5/7] drm/i915: sseu: convert subslice count fields to subslice mask

struct intel_csr { > > struct sseu_dev_info { > u8 slice_mask; > - u8 subslice_total; > - u8 subslice_per_slice; > + u8 subslice_mask; I know we have situations for GT1 parts where the number of subslices per slice is less than that of the same GEN of a different SKU. AFAIK, this never carries over into higher GT (ie. GT2 would always have 3 subslices per slice, but GT1 may have 2 subslices per slice). However. I am not certain this is the case - I hope you've double checked that. > u8 eu_total; > u8 eu_per_subslice; > /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ > @@ -795,6 +794,11 @@ struct sseu_dev_info { > u8 has_eu_pg:1; > }; > > +static inline unsigned int sseu_subslice_total(const struct sseu_dev_info > *sseu) > +{ > + return hweight32((sseu)->slice_mask) * hweight32((sseu)->subslice_mask); hweight8 basically s/hweight32/hweight8 on the whole file > +} > + > struct intel_device_info { > u32 display_mmio_offset; > u16 device_id; > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > b/drivers/gpu/drm/i915/intel_lrc.c > index 4130ff1..158f008 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -2209,7 +2209,7 @@ make_rpcs(struct drm_device *dev) > > if (INTEL_INFO(dev)->sseu.has_subslice_pg) { > rpcs |= GEN8_RPCS_SS_CNT_ENABLE; > - rpcs |= INTEL_INFO(dev)->sseu.subslice_per_slice << > + rpcs |= hweight32(INTEL_INFO(dev)->sseu.subslice_mask) << > GEN8_RPCS_SS_CNT_SHIFT; > rpcs |= GEN8_RPCS_ENABLE; > } Reviewed-by: Ben Widawsky <benjamin.widaw...@intel.com> -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 7/7] drm/i915/bdw: sseu: fix sseu status parsing

use for_each_set_bit here too. > u8 subslice_7eu = INTEL_INFO(dev)->sseu.subslice_7eu[s]; > > stat->eu_total -= hweight8(subslice_7eu); 6 & 7 are: Reviewed-by: Ben Widawsky <benjamin.widaw...@intel.com> 1-7 are al

Re: [Intel-gfx] [PATCH 4/7] drm/i915: sseu: convert slice count field to mask

rivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -783,7 +783,7 @@ struct intel_csr { > #define SEP_SEMICOLON ; > > struct sseu_dev_info { > - u8 slice_total; > + u8 slice_mask; > u8 subslice_total; > u8

Re: [Intel-gfx] [PATCH 1/7] drm/i915: sseu: move sseu_dev_status to i915_drv.h

cer. struct slice_attributes { u8 slice_count; u8 eu_total; /* This is sort of useless since if eu_total isn't trivially * eu_per_subslice * subslice_count * slice_count, then we * need to know exactly which subslice is missing EUs. */

Re: [Intel-gfx] [PATCH 2/7] drm/i915: sseu: use sseu_dev_info in device info

On Wed, Oct 21, 2015 at 06:40:32PM +0300, Imre Deak wrote: > Move all slice/subslice/eu related properties to the sseu_dev_info > struct. > > No functional change. > > Signed-off-by: Imre Deak <imre.d...@intel.com> Reviewed-by: Ben Widawsky <benjamin.widaw...@intel

Re: [Intel-gfx] [PATCH 3/7] drm/i915: sseu: simplify debugfs status/info printing

On Wed, Oct 21, 2015 at 06:40:33PM +0300, Imre Deak wrote: > Signed-off-by: Imre Deak <imre.d...@intel.com> Reviewed-by: Ben Widawsky <benjamin.widaw...@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 55 > +++-- > 1 file ch

Re: [Intel-gfx] [PATCH] tools/null_state/gen9: Send all components in VF state

Date: Fri Jul 31 16:27:07 2015 +0100 > > > > tools/null_state/gen9: Send atleast one valid component in VF state > > > > to honor the Reviewed-by, send all four components as noted by > > Ben in his review. > > > > Cc: Ben Widawsky <benjamin.wida

[Intel-gfx] [PATCH] igt/intel_aubdump: Use the right ring

This prevents the simulator from barfing when it sees commands from another ring. I've been using this locally for a very long time. Cc: Kristian Høgsberg <k...@bitplanet.net> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- tools/aubdump.c | 2 +- 1 file changed, 1 ins

Re: [Intel-gfx] [PATCH 3/5] drm/i915/kbl: Kabylake A0 is based on Skylake H0.

On Tue, Oct 06, 2015 at 08:51:13PM +, Rodrigo Vivi wrote: > cc'ing Ben to get his opinion... > Of course anything is possible wrt the delta of KBL features vs SKL. With the knowledge we have, we can make a pretty educated guess that there will be no changes, and with an equally high level of

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Try to print INSTDONE bits for all slice/subslice

On Fri, Oct 02, 2015 at 01:58:13PM +0300, Imre Deak wrote: > On Thu, 2015-10-01 at 16:00 -0700, Ben Widawsky wrote: > > On Wed, Sep 30, 2015 at 11:00:46PM +0300, Imre Deak wrote: > > > From: Ben Widawsky <benjamin.widaw...@intel.com> > > > > > > Sign

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Try to print INSTDONE bits for all slice/subslice

On Wed, Sep 30, 2015 at 11:00:46PM +0300, Imre Deak wrote: > From: Ben Widawsky <benjamin.widaw...@intel.com> > > Signed-off-by: Ben Widawsky <b...@bwidawsk.net> > > --- > Changes (Imre): > - use the new INSTDONE capturing by default on new GENs (On Ben's requ

Re: [Intel-gfx] [PATCH 3/5] drm/i915: rename INSTDONE1 to GEN4_INSTDONE1

; #define INSTPS 0x02070 /* 965+ only */ > -#define INSTDONE10x0207c /* 965+ only */ > +#define GEN4_INSTDONE1 0x0207c /* 965+ only, aka INSTDONE_2 on SNB */ > #define ACTHD_I965 0x02074 > #define HWS_PGA 0x02080 > #define HWS_ADDRESS_MASK

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Try to print INSTDONE bits for all slice/subslice

On Wed, Sep 30, 2015 at 11:00:46PM +0300, Imre Deak wrote: > From: Ben Widawsky <benjamin.widaw...@intel.com> > > Signed-off-by: Ben Widawsky <b...@bwidawsk.net> > > --- > Changes (Imre): > - use the new INSTDONE capturing by default on new GENs (On Ben's requ

Re: [Intel-gfx] [PATCH] lib/rendercopy_gen9: Setup Push constant pointer before sending BTP commands

On Tue, Aug 18, 2015 at 05:25:55PM +0300, Joonas Lahtinen wrote: Hi, On pe, 2015-08-14 at 10:58 +0200, Daniel Vetter wrote: On Thu, Aug 13, 2015 at 03:49:35PM -0700, Ben Widawsky wrote: On Thu, Aug 13, 2015 at 10:33:00AM +0300, Joonas Lahtinen wrote: Hi, On ke, 2015-08-12

Re: [Intel-gfx] [PATCH] tools/null_state/gen9: Send all components in VF state

the Reviewed-by, send all four components as noted by Ben in his review. Cc: Ben Widawsky benjamin.widaw...@intel.com Cc: Arun Siluvery arun.siluv...@linux.intel.com Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com Thanks. (STILL in favor of just dropping it :P ) Reviewed-by: Ben

Re: [Intel-gfx] [PATCH] lib/rendercopy_gen9: Setup Push constant pointer before sending BTP commands

On Thu, Aug 13, 2015 at 10:33:00AM +0300, Joonas Lahtinen wrote: Hi, On ke, 2015-08-12 at 18:35 -0700, Ben Widawsky wrote: On Wed, Aug 12, 2015 at 03:10:18PM +0300, Joonas Lahtinen wrote: On ke, 2015-08-12 at 12:26 +0100, Arun Siluvery wrote: From Gen9, by default push constant

Re: [Intel-gfx] [PATCH] lib/rendercopy_gen9: Setup Push constant pointer before sending BTP commands

set shader is enabled. This patch updates the batch to follow this requirement otherwise it results in gpu hang. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89959 Set shader need to be disabled if legacy behaviour is required. Cc: Ben Widawsky benjamin.widaw

Re: [Intel-gfx] [PATCH] drm/i915:gen9: Add WA for disable gather at set shader bit

because userspace may set it. If userspace really need it to be set then they need to do in every batch. Cc: Ben Widawsky benjamin.widaw...@intel.com Cc: Mika Kuoppala mika.kuopp...@intel.com Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1

Re: [Intel-gfx] [PATCH] tools/null_state/gen9: Send atleast one valid component in VF state

On Wed, Aug 05, 2015 at 11:13:46AM +0300, Mika Kuoppala wrote: Ben Widawsky benjamin.widaw...@intel.com writes: On Fri, Jul 31, 2015 at 04:27:07PM +0100, Arun Siluvery wrote: A programming restriction exists for this instruction, atleast one component of one valid vertex element must

Re: [Intel-gfx] [PATCH] tools/null_state/gen9: Send atleast one valid component in VF state

On Fri, Jul 31, 2015 at 04:27:07PM +0100, Arun Siluvery wrote: A programming restriction exists for this instruction, atleast one component of one valid vertex element must be enabled. Cc: Ben Widawsky benjamin.widaw...@intel.com Cc: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Arun

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915:gen9: Add disable gather at set shader w/a

by two different registers, use a better option (Ben). Cc: Ben Widawsky benjamin.widaw...@intel.com Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH] drm/i915/gen9: Update null batch to follow VF state restriction

On Fri, Jul 31, 2015 at 04:28:45PM +0100, Arun Siluvery wrote: Atleast one component of one valid vertex element must be enabled. Cc: Ben Widawsky benjamin.widaw...@intel.com Cc: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com --- drivers

Re: [Intel-gfx] [PATCH v1 1/2] drm/i915:skl: Add WaEnableGapsTsvCreditFix

On Mon, Aug 03, 2015 at 08:24:56PM +0100, Arun Siluvery wrote: Cc: Ben Widawsky benjamin.widaw...@intel.com Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH v1 2/2] drm/i915:gen9: Add disable gather at set shader w/a

On Mon, Aug 03, 2015 at 08:24:57PM +0100, Arun Siluvery wrote: This WA is implemented in init_context as well as WA batch init. There are also some dependent bits need to be set in other registers for this to be complete. Cc: Ben Widawsky benjamin.widaw...@intel.com Cc: Joonas Lahtinen

Re: [Intel-gfx] [PATCH v2 1/2] i965/gen9: Pass alignment as function parameter in drm_intel_gem_bo_alloc_internal()

On Thu, Jun 25, 2015 at 07:11:21PM +0100, Chris Wilson wrote: On Thu, Jun 25, 2015 at 11:01:44AM -0700, Ben Widawsky wrote: On Wed, Jun 24, 2015 at 08:28:13AM +0100, Chris Wilson wrote: On Tue, Jun 23, 2015 at 04:44:52PM -0700, Anuj Phogat wrote: On Mon, Jun 22, 2015 at 1:04 PM, Chris

Re: [Intel-gfx] [PATCH v2 1/2] i965/gen9: Pass alignment as function parameter in drm_intel_gem_bo_alloc_internal()

On Wed, Jun 24, 2015 at 08:28:13AM +0100, Chris Wilson wrote: On Tue, Jun 23, 2015 at 04:44:52PM -0700, Anuj Phogat wrote: On Mon, Jun 22, 2015 at 1:04 PM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Mon, Jun 22, 2015 at 09:51:08PM +0200, Daniel Vetter wrote: On Mon, Jun 22, 2015

Re: [Intel-gfx] [Mesa-dev] [PATCH mesa] i965/gen8+: bo in state base address must be in 32-bit address range

Hi. Feel free to Cc me on patches of this nature. I am far behind on mesa-dev, and no longer read intel-gfx. I'm probably one of the sensible people to look at this... On Tue, Jun 23, 2015 at 01:21:27PM +0100, Michel Thierry wrote: Gen8+ supports 48-bit virtual addresses, but some objects must

Re: [Intel-gfx] [PATCH 2/2] Set alignment value in drm_intel_add_validate_buffer()

restriction. It didn't seem doable with the current interfaces, but it's something to think about. With or without the first recommendation: Reviewed-by: Ben Widawsky b...@bwidawsk.net ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http

Re: [Intel-gfx] [PATCH 1/2] i965/gen9: Pass alignment as function parameter in drm_intel_gem_bo_alloc_internal()

On Fri, Jun 19, 2015 at 03:50:44PM -0700, Anuj Phogat wrote: +Ben. On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote: and use it to initialize the align variable in drm_intel_bo. In case of YF/YS tiled buffers libdrm need not know about the tiling format because

Re: [Intel-gfx] [PATCH 1/6] intel: Defer setting madv on the bo cache

-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Ben Widawsky benjamin.widaw...@intel.com --- intel/intel_bufmgr_gem.c | 27 --- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel

Re: [Intel-gfx] [PATCH] drm/i915/skl: Implement WaBarrierPerformanceFixDisable (again)

On Wed, 03 Jun 2015 09:49:43 +0300 Jani Nikula jani.nik...@linux.intel.com wrote: On Wed, 03 Jun 2015, Ben Widawsky benjamin.widaw...@intel.com wrote: in commit 65ca7514e21adbee25b8175fc909759c735d00ff Author: Damien Lespiau damien.lesp...@intel.com Date: Mon Feb 9 19:33:22 2015 +

[Intel-gfx] [PATCH] drm/i915/skl: Implement WaBarrierPerformanceFixDisable (again)

of that is, but it /seems/ wrong. Don't know if this fixes anything since I have many other problems with my platform. Cc: Damien Lespiau damien.lesp...@intel.com Cc: Nick Hoath nicholas.ho...@intel.com Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/intel_ringbuffer.c | 14

Re: [Intel-gfx] [PATCH 1/2] intel: Defer setting madv on the bo cache

, it looks fine to me. Like I said above wrt adding the patch before this, I am curious how much difference you see just messing with the expiration times versus the two state model. -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing

Re: [Intel-gfx] [PATCH] drm/i915: Force HW context restore on resume.

. The force is required because the LRCA might be [*should be*] be the same across suspend resume. Cc: Ben Widawsky b...@bwidawsk.net Cc: U. Artie Eoff ullysses.a.e...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com Debugged-by?: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH] drm/i915: Force HW context restore on resume.

and when we resume we can force a restore if default is really there and object is bound. Cc: Ben Widawsky b...@bwidawsk.net Cc: U. Artie Eoff ullysses.a.e...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com Bleh, you don't need to overload enable as the context switch should

Re: [Intel-gfx] [PATCH] drm/i915: Setup all page directories for gen8

-by: Valtteri Rantala valtteri.rant...@intel.com Cc: Michel Thierry michel.thie...@intel.com Cc: Ben Widawsky benjamin.widaw...@intel.com Cc: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed

[Intel-gfx] [PATCH 1/2] drm/i915: Track last register written (debug)

useful this is/would be. Cc: Paulo Zanoni przan...@gmail.com Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_drv.h | 11 +-- drivers/gpu/drm/i915/intel_uncore.c | 11 ++- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH 2/2] drm/i915: Add the last written reg to error state

Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 11 +++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6fa22db..49bc296 100644

[Intel-gfx] [PATCH 5/6] drm/i915: Extract checking the necessity of flush

Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_gem.c | 53 +++-- 1 file changed, 30 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 5bfb332..4d5a69d 100644

[Intel-gfx] [PATCH 2/6] drm/i915: Pass eb_vmas to execbuffer implementations

be separate. Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_drv.h| 13 +++-- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 26 ++ drivers/gpu/drm/i915/intel_lrc.c | 8 +--- drivers/gpu/drm/i915/intel_lrc.h

[Intel-gfx] [PATCH 3/6] drm/i915: Opportunistically reduce flushing at execbuf

missed something in the code, it should only effect non-LLC i915 platforms. I haven't yet run any numbers for other benchmarks, nor have I attempted to check if various conformance tests still pass. v2: Rewrite the patch to be i915 only Obtain whether or not we wbinvd up front. Signed-off-by: Ben

[Intel-gfx] [PATCH 6/6] drm/i915: obey wbinvd threshold in more places

Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_drv.h | 4 drivers/gpu/drm/i915/i915_gem.c | 32 drivers/gpu/drm/i915/i915_gem_gtt.c | 13 ++--- 3 files changed, 42 insertions(+), 7 deletions(-) diff --git

[Intel-gfx] [PATCH 1/6] drm/i915: Remove the useless flush_chipset

flush_chipset makes no sense with execlists because the former is for strictly prior to gen6, while the latter is for gen = 8 Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/intel_lrc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH 4/6] drm/i915: Add debugfs knobs for wbinvd threshold

Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_debugfs.c | 34 ++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index b315f01..e0fd3ba 100644 --- a/drivers/gpu

[Intel-gfx] [PATCH 0/6] Prefer wbinvd() where appropriate

didn't check that I rebased things properly. Do what you want with them... Ben Widawsky (6): drm/i915: Remove the useless flush_chipset drm/i915: Pass eb_vmas to execbuffer implementations drm/i915: Opportunistically reduce flushing at execbuf drm/i915: Add debugfs knobs for wbinvd

Re: [Intel-gfx] [PATCH] drm/i915/fbc: fix the check for already reserved fbc size

been introduced in commit 5e59f7175f96550ede91f58d267d2b551cb6fbba Author: Ben Widawsky benjamin.widaw...@intel.com Date: Mon Jun 30 10:41:24 2014 -0700 drm/i915: Try harder to get FBC Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88975 Suggested-by: Chris Wilson ch...@chris

Re: [Intel-gfx] [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a

On Mon, Feb 02, 2015 at 01:21:19PM +, Damien Lespiau wrote: On Mon, Feb 02, 2015 at 02:33:48PM +0200, Ville Syrjälä wrote: On Thu, Jan 08, 2015 at 07:59:10PM -0800, Ben Widawsky wrote: Implements a required workaround whose implications aren't entirely clear to me from

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