flush_chipset makes no sense with execlists because the former is for strictly
prior to gen6, while the latter is for gen >= 8
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lr
>
> The bug has been introduced in
>
> commit 5e59f7175f96550ede91f58d267d2b551cb6fbba
> Author: Ben Widawsky
> Date: Mon Jun 30 10:41:24 2014 -0700
>
> drm/i915: Try harder to get FBC
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88975
> S
On Mon, Feb 02, 2015 at 01:21:19PM +, Damien Lespiau wrote:
> On Mon, Feb 02, 2015 at 02:33:48PM +0200, Ville Syrjälä wrote:
> > On Thu, Jan 08, 2015 at 07:59:10PM -0800, Ben Widawsky wrote:
> > > Implements a required workaround whose implications aren't entirely clear
Signed-off-by: Ben Widawsky
---
tests/gem_render_copy.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/tests/gem_render_copy.c b/tests/gem_render_copy.c
index 006b6f5..6348eee 100644
--- a/tests/gem_render_copy.c
+++ b/tests/gem_render_copy.c
On Fri, Jan 16, 2015 at 09:12:15AM +, tim.g...@intel.com wrote:
> From: Tim Gore
>
> getsubopt is not available in android. The "get" option
> doesn't really need sub-options, just display all the
> current frequency settings (as per discussion with
> Ben
On Thu, Jan 15, 2015 at 05:05:30PM +, Tvrtko Ursulin wrote:
>
> On 01/15/2015 04:54 PM, Ben Widawsky wrote:
> >On Thu, Jan 15, 2015 at 11:21:30AM +, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin
> >>
> >>This eliminates six needless spin
On Thu, Jan 15, 2015 at 02:00:06PM +, Dave Gordon wrote:
> On 12/01/15 03:35, Ben Widawsky wrote:
> > WARNING: very minimally tested
> >
> > In general you should not need this tool. It's primary purpose is for
> > benchmarking, and for debugging performance
On Thu, Jan 15, 2015 at 05:27:50PM +, tim.g...@intel.com wrote:
> From: Tim Gore
>
> getsubopt is not available in android. The "get" option
> doesn't really need sub-options, just display all the
> current frequency settings (as per discussion with
> Ben
V (bench_OglBatch4 bench_OglDeferred respectively).
With 95% confidence t-test on n=5
>
> Kindly benchmarked by Ben Widawsky.
FWIW, as I mentioned on IRC, I think the reduction of the unnecessary forcewake
(someone should fix the shadow register list) is probably more beneficial than
removing th
On Wed, Jan 14, 2015 at 09:42:24AM -0800, O'Rourke, Tom wrote:
> On Tue, Jan 13, 2015 at 02:36:56PM -0800, Ben Widawsky wrote:
> > On Tue, Jan 13, 2015 at 09:19:04PM +, O'Rourke, Tom wrote:
> > > >Sent: Sunday, January 11, 2015 7:48 PM
> > > >
> >
> >On Sun, Jan 11, 2015 at 07:35:21PM -0800, Ben Widawsky wrote:
> >> WARNING: very minimally tested
> >>
> >> In general you should not need this tool. It's primary purpose is for
> >> benchmarking, and for debugging performance issues.
On Mon, Jan 12, 2015 at 06:09:12PM +, Dave Gordon wrote:
> On 12/01/15 18:02, Ben Widawsky wrote:
> > On Mon, Jan 12, 2015 at 02:02:34PM +0200, Ville Syrjälä wrote:
> >> On Sun, Jan 11, 2015 at 07:14:57PM -0800, Ben Widawsky wrote:
> >>> On Sun, Jan 11, 201
On Mon, Jan 12, 2015 at 02:02:34PM +0200, Ville Syrjälä wrote:
> On Sun, Jan 11, 2015 at 07:14:57PM -0800, Ben Widawsky wrote:
> > On Sun, Jan 11, 2015 at 07:05:21PM -0800, Kenneth Graunke wrote:
> > > On Sunday, January 11, 2015 05:46:09 PM Ben Widawsky wrote:
> > > &
On Sun, Jan 11, 2015 at 07:35:21PM -0800, Ben Widawsky wrote:
> WARNING: very minimally tested
>
> In general you should not need this tool. It's primary purpose is for
> benchmarking, and for debugging performance issues.
I noticed the "it's" vs "its&quo
ommit message in the source code. (me)
Signed-off-by: Ben Widawsky
Reviewed-by: Jordan Justen
Cc: Kenneth Graunke
Here are some sample usages:
$ sudo intel_frequency --get=cur,min,max,eff
cur: 200 MHz
min: 200 MHz
RP1: 200 MHz
max: 1200 MHz
$ sudo intel_frequency -g
cur: 200 MHz
min: 200 MHz
RP1
On Sun, Jan 11, 2015 at 07:05:21PM -0800, Kenneth Graunke wrote:
> On Sunday, January 11, 2015 05:46:09 PM Ben Widawsky wrote:
> > On Sun, Jan 11, 2015 at 04:05:25PM -0800, Kenneth Graunke wrote:
> > > On Sunday, January 11, 2015 01:49:41 PM Ben Widawsky wrote:
> > > &
On Sun, Jan 11, 2015 at 06:53:32PM -0800, Kenneth Graunke wrote:
[snip]
>
> Jesse had suggested setting it in broadwell_init_clock_gating on January 5th,
> and Valtteri tried it on January 7th. He found "no noticeable difference".
> I tried it again, and confirmed his result: there was zero per
On Sun, Jan 11, 2015 at 04:05:25PM -0800, Kenneth Graunke wrote:
> On Sunday, January 11, 2015 01:49:41 PM Ben Widawsky wrote:
> > On Sat, Jan 10, 2015 at 06:44:49PM -0800, Kenneth Graunke wrote:
> > > This is an important optimization for avoiding read-after-write (RAW)
>
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
>
I think you should do this as two separate patches, 1 per platform. For the BSW
patch (given that I had the same functionality in the kernel patch I asked you
to look at ;-) and FWIW, Jordan has numbers on BSW B-step with my kernel
Ken gave me the good idea of -d, --defaults to go back to the hardware specified
defaults. I will send out a v2 if nobody else has any complaints.
On Sat, Jan 10, 2015 at 08:19:29PM -0800, Ben Widawsky wrote:
> WARNING: very minimally tested
>
> In general you should not need this t
Signed-off-by: Ben Widawsky
---
tools/Makefile.sources | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/tools/Makefile.sources b/tools/Makefile.sources
index 48b89db..b85a6b8 100644
--- a/tools/Makefile.sources
+++ b/tools/Makefile.sources
@@ -8,32
ality. What it does
provide is an easy to package (for distros) tool that handles the most common
scenarios.
Signed-off-by: Ben Widawsky
Here are some sample usages:
$ sudo intel_frequency --get=cur,min,max,eff
cur: 200 MHz
min: 200 MHz
RP1: 200 MHz
max: 1200 MHz
$ sudo intel_frequency -g
cur: 20
Implements a required workaround whose implications aren't entirely clear to me
from the description. In particular I do not know if this effects legacy
contexts, execlists, or both.
I couldn't find a real workaround name, so I made up:
WaHdcCtxNonCoherent
Signed-off-by: Be
We know certain future platforms need things. Don't let them go unnoticed as
they did for SKL by adding an error message and falling back to the possibly
more conservative SKL values.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 4
1 file changed, 4 inser
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 62318a4..b8a445b 100644
--- a/drivers/gpu
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b8a445b..e14748d 100644
--- a/drivers/gpu/drm/i915
On Fri, Dec 19, 2014 at 08:05:30PM +, Chris Wilson wrote:
> On Fri, Dec 19, 2014 at 06:34:07PM +, Chris Wilson wrote:
> > Just a patch a few days ago that to fix a very ontologically similar bug
> > for ivb+.
>
> Oh boy. I just double checked the error states from those bugs I marked
> as
On Fri, Dec 19, 2014 at 08:20:04AM +, Chris Wilson wrote:
> On Thu, Dec 18, 2014 at 06:20:18PM -0800, Ben Widawsky wrote:
> > From: Ben Widawsky
> >
> > The docs specify this needs to be set on HSW GT1 parts. I've implemented it
> > as
> > such since i
From: Ben Widawsky
The docs specify this needs to be set on HSW GT1 parts. I've implemented it as
such since it should only be needed when using RC6, but it can probably go
anywhere.
This patch fixes extremely reproducible hangs on our Jenkins setup.
The interesting failure signatu
On Tue, Dec 16, 2014 at 07:57:39AM +, Chris Wilson wrote:
> On Mon, Dec 15, 2014 at 01:06:40PM -0800, Ben Widawsky wrote:
> > On Mon, Dec 15, 2014 at 08:39:35PM +, Chris Wilson wrote:
> > > On Mon, Dec 15, 2014 at 11:56:05AM -0800, Ben Widawsky wrote:
> > > >
On Sat, Dec 13, 2014 at 08:15:22PM -0800, Matt Turner wrote:
> On Sat, Dec 13, 2014 at 7:08 PM, Ben Widawsky
> wrote:
> > Any GEM driver which has very large objects and a slow CPU is subject to
> > very
> > long waits simply for clflushing incoherent objects. General
On Mon, Dec 15, 2014 at 08:39:35PM +, Chris Wilson wrote:
> On Mon, Dec 15, 2014 at 11:56:05AM -0800, Ben Widawsky wrote:
> > On Mon, Dec 15, 2014 at 08:20:50AM +, Chris Wilson wrote:
> > > On Mon, Dec 15, 2014 at 08:55:32AM +0100, Daniel Vetter wrote:
> > > >
From: Ben Widawsky
When the original drm code was written there were no centralized functions for
doing a coordinated wbinvd across all CPUs. Now (since 2010) there are, so use
them instead of rolling a new one.
v2: On x86 UP systems the wbinvd_on_all_cpus() is defined as a static inline in
On Mon, Dec 15, 2014 at 08:20:50AM +, Chris Wilson wrote:
> On Mon, Dec 15, 2014 at 08:55:32AM +0100, Daniel Vetter wrote:
> > On Sun, Dec 14, 2014 at 03:37:36PM -0800, Ben Widawsky wrote:
> > > On Sun, Dec 14, 2014 at 03:12:21PM +0200, Ville Syrjälä wrote:
> > > &
On Sun, Dec 14, 2014 at 08:06:20PM -0800, Jesse Barnes wrote:
> On 12/14/2014 4:59 AM, Chris Wilson wrote:
> >One of the things wbinvd is considered evil for is that it blocks the
> >CPU for an indeterminate amount of time - upsetting latency critcial
> >aspects of the OS. For example, the x86/mm h
On Sun, Dec 14, 2014 at 03:12:21PM +0200, Ville Syrjälä wrote:
> On Sat, Dec 13, 2014 at 07:08:24PM -0800, Ben Widawsky wrote:
> > If we're moving a bunch of buffers from the CPU domain to the GPU domain,
> > and
> > we've already blown out the entire cache
. It would be nice to hear what
other developers who depend on this code think.
Cc: Intel GFX
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/drm_cache.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cac
very minimally considered for the sake of getting
the data for the profile.
Cc: Intel GFX
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/drm_cache.c | 34 +-
include/drm/drmP.h | 13 ++---
2 files changed, 35 insertions(+), 12 deletions(-)
diff --
fer and attempt to flush it first, the results would be even more desirable.
Cc: DRI Development
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h| 3 ++-
drivers/gpu/drm/i915/i915_gem.c| 12 +---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +-
When the original drm code was written there were no centralized functions for
doing a coordinated wbinvd across all CPUs. Now (since 2010) there are, so use
them instead of rolling a new one.
Cc: Intel GFX
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/drm_cache.c | 12 +++-
1 file
On Thu, Dec 11, 2014 at 01:28:09PM -0800, Jordan Justen wrote:
> This will allow us to read the number of dispatched compute threads
> for GL_ARB_pipeline_statistics_query.
>
> Signed-off-by: Jordan Justen
> Cc: Ben Widawsky
Reviewed-by: Ben W
On Fri, Aug 22, 2014 at 08:15:28AM -0400, Alex Deucher wrote:
> On Thu, Aug 21, 2014 at 11:12 PM, Ben Widawsky
> wrote:
> > This was a quick proof of concept to show the new API for prelocating
> > buffers.
> >
>
> What are prelocated buffers?
http://lists.freedesk
t the first time I've written this patch.
XXX: This patch was never tested pre-GEN8. After rebase it was compile
tested only on GEN8.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 78 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 2
pdate functions
insert and clear entries.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 60 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 57 insertions(+), 8 deletions(-)
diff --
destroy it at teardown. (A similar argument can be made
for PDPs when not using sparse addresses).
Almost none of the fanciness here will exercised since the switch isn't
flipped until later.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c
Words
Signed-off-by: Ben Widawsky
---
intel/intel_bufmgr.h | 8
intel/intel_bufmgr_gem.c | 102 +++
2 files changed, 102 insertions(+), 8 deletions(-)
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 9383c72..e4ecc44 100644
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ---
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8d46993..00d9ab3 100644
--- a/drivers/gpu
Signed-off-by: Ben Widawsky
---
intel/intel_bufmgr_gem.c | 69
1 file changed, 40 insertions(+), 29 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 0e1cb0d..d7d3769 100644
--- a/intel/intel_bufmgr_gem.c
+++ b
-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 398 +---
drivers/gpu/drm/i915/i915_gem_gtt.h | 23 +--
2 files changed, 147 insertions(+), 274 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index
This patch is a proof of concept hack which repurposes the MSB of the
size field in created. Userptr already has the gup code, and all we need
to do is reuse it.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h| 12 -
drivers/gpu/drm/i915/i915_gem.c
This was a quick proof of concept to show the new API for prelocating
buffers.
It needs way more testing, to not ifdef the no-relocs, and to do a
libdrm ABI dep bump.
---
src/mesa/drivers/dri/i965/Makefile.am | 1 +
src/mesa/drivers/dri/i965/brw_performance_monitor.c | 6 +++---
src
and track unmaps as opposed to destruction.
v2: Consolidate pagetable/pagedirectory events
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 35 +++
drivers/gpu/drm/i915/i915_trace.h | 32
2 files changed, 59
1. Always force invalidate. This doesn't fix any bugs, but it makes the
time to failure longer.
2. Make TLB validation explicit
I can't say I've spent too much time with these, however, it seems if I
use each individually, I get no observable stability improvement. When I
use them together though
page table
level and here is no exception. Having extra variables (such as the
PPGTT) distracts and provides room to add bugs since the function
shouldn't be touching anything in the higher order page tables.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915
v2: 0 pad the new 8B fields or else intel_error_decode has a hard time.
Note, regardless we need an igt update.
v3: Make reloc_offset 64b also.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 17 +
2 files
needs libdrm
---
tests/Makefile.am| 4 +-
tests/Makefile.sources | 1 +
tests/gem_exec_noreloc.c | 172 +++
3 files changed, 175 insertions(+), 2 deletions(-)
create mode 100644 tests/gem_exec_noreloc.c
diff --git a/tests/Makefile.am b/te
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 52 -
drivers/gpu/drm/i915/i915_gem_gtt.c | 33 +++
drivers/gpu/drm/i915/i915_gem_gtt.h | 9 +++
3 files changed, 82 insertions(+), 12 deletions(-)
diff --git a
Similar to the patch a few back in the series, we can always map and
unmap page directories when we do their allocation and teardown. Page
directory pages only exist on gen8+, so this should only effect behavior
on those platforms.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915
v2: s/i915_gem_bind_vma/i915_gem_vma_bind/
s/i915_gem_unbind_vma/i915_gem_vma_unbind/
(Chris)
v3: Missed one spot
v4: Don't change the trace events (Daniel)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h| 3 +++
drivers/gpu/drm/i915/i915_gem.c
These values are never quite useful for dynamic allocations of the page
tables. Getting rid of them will help prevent later confusion.
TODO: this probably needs to be earlier in the series
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 -
drivers/gpu/drm/i915
nt
to keep reset enabled but still get error state.
Since I found the patch pretty useful, I decided to clean it up and
submit it. It was mostly meant as a one-off hack originally though.
If a maintainer decides it's useful, then here it is.
Signed-off-by: Ben Widawsky
---
drivers/gp
trivial.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 4af3150..0199c5a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 43 ++---
1 file changed, 31 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 65b1c58..5447a99 100644
--- a/drivers
PTEs allows the iterator to stay coherent
through a VMA mapping operation spanning multiple page table levels.
This looks really ugly for now, but once we move toward not separately
allocating and updating PTEs, it will make a lot of sense.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm
The latter point only matters with full PPGTT. The former point would
only effect 32b platforms, or platforms with less than 4GB memory.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 34 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 -
2 fil
We have some fanciness coming up. This patch just breaks out the logic.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
Like with gen6/7, we can enable bitmap tracking with all the
preallocations to make sure things actually don't blow up.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 101 +++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 12 +
2
oes to him.
References: 20140320115742.ga4...@nuc-i3427.alporthouse.com
Cc: Mika Kuoppala
Cc: Chris Wilson
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 52 +++--
1 file changed, 32 insertions(+), 20 deletions(-)
diff --git a/drivers/gp
navoidable wart
throughout the series. (in other words, not extra flagrant).
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915
Therefore we can do it from our general init function. Eventually, I
hope to have a lot more commonality like this. It won't arrive yet, but
this was a nice easy one.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +
1 file changed, 1 insertion(+), 4 dele
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 54 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +++
2 files changed, 39 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915
taking
off the active list because of the missing retire seqno for a VMA.
Like some of the other fixes I've submitted recently, this should be
fixed by the eventual work Daniel will do.
This is pretty easy to reproduce whenever mesa uses the blit engine.
Signed-off-by: Ben Widawsky
---
submit a batch. This is the case today, and has been
the case since the inception of hardware contexts. A note in the comment
let's the user know.
Signed-off-by: Ben Widawsky
squash! drm/i915: Force pd restore when PDEs change, gen6-7
It's not just for gen8. If the current context
requiring just this.
A nice benefit of this is we should no longer be able to clobber GTT
only objects from the aliasing PPGTT.
v2: Only add aliasing binds for the GGTT/Aliasing PPGTT at execbuf
v3: Rebase resolution with changed size of flags
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915
7;ve unmapped things.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 371 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 16 +-
2 files changed, 324 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm
It's useful to have it not as a macro for some upcoming work. Generally
since we try to avoid macros anyway, I think it doesn't hurt to put this
as its own patch.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c| 4 ++--
drivers/gpu/drm/i915/i915_gem_gt
l4 for the top level, and the pdp is just one of the entries
being pointed to by a pml4e.
This patch addresses some carelessness done throughout development wrt
assumptions made of the root page tables.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_g
The page directory freer is left here for now as it's still useful given
that GEN8 still preallocates. Once the allocation functions are broken
up into more discrete chunks, we'll follow suit and destroy this
leftover piece.
comments
Signed-off-by: Ben Widawsky
---
drivers/gp
;ll need a function for
that in the future as well.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 96 -
1 file changed, 52 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_g
meliorated shortly.
NOTE: The pun in the subject was intentional.
Signed-off-by: Ben Widawsky
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 174 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 23 +++--
2 files ch
ned-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h| 14 --
drivers/gpu/drm/i915/i915_gem.c| 31 +++---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c| 12 ++--
drive
This reverts commit 0d68b25e9ceb344fe2f93373b1c0311d33814265.
At one time I bisected reset breakage to this patch by using a mesa that is
guaranteed to generate a hang when using the fs, and then running the following
test case:
./bin/shader_runner tests/shaders/glsl-algebraic-add-zero.shader_te
sing PPGTT is not managed here. The patch which actually
begins dynamic allocation/teardown explains the reasoning forthis.
v2: s/pdp.pagedir/pdp.pagedirs
Make a scratch page allocation helper
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_g
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_trace.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index f5aa006..cbf5521 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers
dated trace event to spit out a name
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 -
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c
quire newlines, or local
variables to make it fit cleanly.
Notice that even the page allocation shares this same attribute. For
now, I am leaving that code untouched because the macro version would be
a bit on the big side - but it's a nice cleanup as well (IMO)
Signed-off-by: Ben Widawsky
--
In gen8, 32b PPGTT has always had one "pdp" (it doesn't actually have
one, but it resembles having one). The #define was confusing as is, and
using "PDPE" is a much better description.
sed -i 's/GEN8_LEGACY_PDPS/GEN8_LEGACY_PDPES/' drivers/gpu/drm/i915/
Upcoming patches will use the terms map and unmap in references to the
page table entries. Having this distinction will really help with code
clarity at that point.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++--
1 file changed, 6 insertions(+), 6
ing around with such things trivial.
v2: Updated commit message to explain why this patch exists
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 226 +++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
2 files changed, 147 insertions(+), 83
be a
discrete operation.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 147 +---
1 file changed, 85 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8df3b15..4b
Move the remaining members over to the new page table structures.
This can be squashed with the previous commit if desire. The reasoning
is the same as that patch. I simply felt it is easier to review if split.
Signed-off-by: Ben Widawsky
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
There is never a case where we don't want to do it. Since we've broken
up the allocations into nice clean helper functions, it's both easy and
obvious to do the dma mapping at the same time.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915
e.
It was tricky to track this down as we don't have much insight into what
happens in a context save.
This is required for the next patch which enables dynamic page tables.
I need to go back and test this pre-GEN8
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c |
This is a spec requirement for all rings.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 61b36f9..ef256ae 100644
--- a/drivers
f future patches.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ab863bb..861df21 100644
--- a/drivers/gpu/drm/
lt;<22) == 512);
assert(gen6_pde_count(base + 0x1000, 512<<22) == 512);
assert(gen6_pde_count(base + (1<<22), 512<<22) == 511);
}
int main()
{
test_pde(0);
while (1)
test_pte(rand() & ~((1<<22) - 1));
return 0;
}
v
Split out single mappings which will help with upcoming work. Also while
here, rename the function because it is a better description - but this
function is going away soon.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 ++---
1 file
Broadwell is perfectly capable of full PPGTT. I've been using it for
some time, and seen no especially ill effects.
Signed-off-by: Ben Widawsky
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
The current code will both potentially print a WARN, and setup part of
the PPGTT structure. Neither of these harm the current code, it is
simply for clarity, and to perhaps prevent later bugs, or weird
debug messages.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5
This transitional patch doesn't do much for the existing code. However,
it should make upcoming patches to use the full 48b address space a bit
easier to swallow. The patch also introduces the PML4, ie. the new top
level structure of the page tables.
Signed-off-by: Ben Widawsky
---
driver
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