TODO: Do header files need a copyright?
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.h | 162 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 57 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 225
3
Split out single mappings which will help with upcoming work. Also while
here, rename the function because it is a better description - but this
function is going away soon.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39
Upcoming patches will use the terms map and unmap in references to the
page table entries. Having this distinction will really help with code
clarity at that point.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++--
1 file changed, 6
the ability to map things sparsely, which also will
greatly limit the effective virtual address space we can use.
Ben Widawsky (26):
drm/i915: Split out verbose PPGTT dumping
drm/i915: Extract switch to default context
drm/i915: s/pd/pdpe, s/pt/pde
drm/i915: rename map/unmap to dma_map/unmap
shortly.
NOTE: The pun in the subject was intentional.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 175 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 24 +++--
2 files
init, now that GEN8 exists.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 22 +-
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1620211
) == 511);
}
int main()
{
test_pde(0);
while (1)
test_pte(rand() ~((122) - 1));
return 0;
}
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 90 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 125
newlines, or local
variables to make it fit cleanly.
Notice that even the page allocation shares this same attribute. For
now, I am leaving that code untouched because the macro version would be
a bit on the big side - but it's a nice cleanup as well (IMO)
Signed-off-by: Ben Widawsky b
be a
discrete operation.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 147 +---
1 file changed, 85 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5f3666a..04d40fa 100644
--- a/drivers/gpu
Start using size/length through the GEN8 code. The same approach was
taken for gen7. The difference with gen8 to this point is we need to
take care to the do the page directory allocations, as well as the page
tables.
This patch is meant to show how things will look (more or less) if I
keep up in
Move the remaining members over to the new page table structures.
This can be squashed with the previous commit if desire. The reasoning
is the same as that patch. I simply felt it is easier to review if split.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Conflicts:
drivers/gpu/drm
There is never a case where we don't want to do it. Since we've broken
up the allocations into nice clean helper functions, it's both easy and
obvious to do the dma mapping at the same time.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 78
is not managed here. The patch which actually
begins dynamic allocation/teardown explains the reasoning forthis.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 170 +---
drivers/gpu/drm/i915/i915_gem_gtt.h | 117
. At that point I will try to
combine functionality.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 61 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
2 files changed, 34 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm
We have some fanciness coming up. This patch just breaks out the logic.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_context.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers
which lead me to believe there are some corner cases that
will require it. I'm mostly depending on the reload of DCLV to
invalidate the old TLBs. We can try to remove this patch and see what
happens.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_context.c| 15
I have been seeing this for a long time, but ignored it because it's
typically not terribly important. Recently, I really needed this info,
and it was garbage. Proof that I should have fixed it sooner. Originally
wrong from:
commit 6c7a01ec3743a5a6ce9e53a69d7a6c2d8c715eb1
Author: Ben Widawsky
On Sat, Mar 15, 2014 at 12:08:56AM +0100, Daniel Vetter wrote:
Currently not an issue since we don't emit sempahores, but better
not forget about those.
As a little prep work extract the ipehr decoding for cleaner control
flow. And apply a bit of polish.
Cc: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_uncore.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index e6bb421..7e55ceb 100644
--- a/drivers/gpu/drm/i915
On Sat, Mar 15, 2014 at 03:20:23PM +, Chris Wilson wrote:
On Sat, Mar 15, 2014 at 12:47:22PM +0100, Daniel Vetter wrote:
On Fri, Mar 14, 2014 at 05:21:36PM -0700, Ben Widawsky wrote:
Broken by:
commit 0294ae7b44bba7ab0d4cef9a8736287f38bdb4fd
Author: Chris Wilson ch...@chris
The preliminary HW support check is no longer needed, and the
calculation is simplified while here.
Reported-by: David Woodhouse david.woodho...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 +
1 file changed, 1 insertion(+), 8
On Fri, Mar 14, 2014 at 07:40:30PM +0100, Daniel Vetter wrote:
On Fri, Mar 14, 2014 at 09:58:06AM -0700, Ben Widawsky wrote:
The preliminary HW support check is no longer needed, and the
calculation is simplified while here.
Reported-by: David Woodhouse david.woodho...@intel.com
Signed
On Thu, Mar 13, 2014 at 12:51 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
Upon resume, the hardware continues writing the breadcrumbs into the old
hws page (due to the stale TLB) and we try to read the seqno from the
new page, so as shown by the error-states it appears that the breadcrumb
, or at least change the comment/commit message to
be to reflect whatever light Chris sheds on the matter.
Anyway, the bits are definitely gone, and I also can't find a non-ring
based replacement.
Reviewed-by: Ben Widawsky b...@bwidawsk.net
--
Ben Widawsky, Intel Open Source Technology Center
On Tue, Mar 11, 2014 at 5:24 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Sat, Mar 08, 2014 at 11:59:42AM -0800, Ben Widawsky wrote:
On Sat, Mar 08, 2014 at 11:58:16AM -0800, Ben Widawsky wrote:
I'm not clear if the hardware is still subject to the same prefetching
issues that made us
at 9:46 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, Mar 11, 2014 at 09:39:30AM -0700, Ben Widawsky wrote:
On Tue, Mar 11, 2014 at 5:24 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Sat, Mar 08, 2014 at 11:59:42AM -0800, Ben Widawsky wrote:
On Sat, Mar 08, 2014 at 11:58
Cc: Mika Kuoppala mika.kuopp...@linux.intel.com
Cc: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Did you try playing around with setting last_context to
private_default_context? That is more in line with the original outlined
approach of every platform has
On Mon, Mar 10, 2014 at 11:05:42PM +0200, Imre Deak wrote:
On Tue, 2014-02-25 at 19:52 -0800, Ben Widawsky wrote:
These page table helpers make the code much cleaner. There is some
room to use the arch/x86 header files. The reason I've opted not to is
in several cases, the definitions
On Mon, Mar 10, 2014 at 09:30:22PM +0100, Daniel Vetter wrote:
On Mon, Mar 10, 2014 at 7:30 PM, Ben Widawsky b...@bwidawsk.net wrote:
On Mon, Mar 10, 2014 at 09:44:22AM +0100, Daniel Vetter wrote:
It can happen ...
Fix up the check to match pre-gen6 reality where we don't have hw
, for my curiosity, Chris, can you elaborate on why you think it
doesn't make sense?
--
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cannot test it at the moment.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5427d6d..0f39090 100644
On Sat, Mar 08, 2014 at 11:58:16AM -0800, Ben Widawsky wrote:
I'm not clear if the hardware is still subject to the same prefetching
issues that made us use a scratch page in the first place. In either
case, we're using garbage with the current code (we will end up using
offset 0).
This may
On Sat, Mar 08, 2014 at 08:58:24PM +0100, Daniel Vetter wrote:
On Sat, Mar 8, 2014 at 7:50 PM, Ben Widawsky b...@bwidawsk.net wrote:
I've seen this too. Though I think the WARN does coincide with what the
docs state - it doesn't seem to match reality. So I totally agree this
is the right
window is approaching and I think we need to
use the remaining time to ensure that our fallback option of using
aliasing ppgtt is in solid shape. Hence I think it's time to throw the
switch. While at it demote the helper from static inline status
because really.
Cc: Ben Widawsky b
On Thu, Mar 06, 2014 at 09:30:01PM +0100, Daniel Vetter wrote:
On Thu, Mar 06, 2014 at 10:17:12AM -0800, Ben Widawsky wrote:
On Thu, Mar 06, 2014 at 12:14:21PM +0100, Daniel Vetter wrote:
There are too many oustanding issues:
- Fence handling in the current code is broken. There's
such a thing at some point, but threw it
away because I didn't actually have a vlv diff at the time.
I had to re-review a lot of the uncore.lock stuff, but lgtm:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
--
Ben Widawsky, Intel Open Source Technology Center
On Wed, Mar 05, 2014 at 06:08:19PM +0200, Mika Kuoppala wrote:
There should not be a case where fifo count is other
than zero after a successful reset. Always set
count to zero, but be paranoid enough to warn.
v2: rebased
Suggested-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Mika
On Wed, Mar 05, 2014 at 07:33:11PM +0100, Daniel Vetter wrote:
On Wed, Mar 05, 2014 at 09:24:34AM +, Chris Wilson wrote:
On Tue, Mar 04, 2014 at 09:38:56AM -0800, Ben Widawsky wrote:
The actual post sync op is Write Immediate Data QWord. It is therefore
arguable that we should have
On Wed, Mar 05, 2014 at 07:24:37AM -0800, Ben Widawsky wrote:
On Wed, Mar 05, 2014 at 11:13:12AM +0200, Jani Nikula wrote:
On Wed, 05 Mar 2014, Ben Widawsky benjamin.widaw...@intel.com wrote:
The PDE needs to wrap after writing all the PTEs. Quite a small/silly
bug to find in the massive
On Wed, Mar 05, 2014 at 12:00:18PM +0100, Daniel Vetter wrote:
On Fri, Feb 21, 2014 at 04:06:47PM -0300, Paulo Zanoni wrote:
2014-02-20 21:01 GMT-03:00 Ben Widawsky benjamin.widaw...@intel.com:
This got lost when we shuffled around our internal branch and
GEN7_FEATURES macro. There were
On Wed, Mar 05, 2014 at 10:30:21PM +, Chris Wilson wrote:
On Wed, Mar 05, 2014 at 11:05:15AM -0800, Ben Widawsky wrote:
On Wed, Mar 05, 2014 at 07:33:11PM +0100, Daniel Vetter wrote:
On Wed, Mar 05, 2014 at 09:24:34AM +, Chris Wilson wrote:
On Tue, Mar 04, 2014 at 09:38:56AM
.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 94 +
1 file changed, 73 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5f7bee8
On Tue, Mar 04, 2014 at 03:45:56PM +0100, Daniel Vetter wrote:
On Tue, Feb 18, 2014 at 11:18:04AM -0800, Ben Widawsky wrote:
On Wed, Feb 12, 2014 at 07:18:40PM +, Chris Wilson wrote:
For stolen pages, since it is verboten to access them directly on many
architectures, we have to read
The PDE needs to wrap after writing all the PTEs. Quite a small/silly
bug to find in the massive change. It was introduced:
commit 307dc4f99f6d3a74a78b0e776838f35b2004f14d
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Thu Feb 20 11:51:21 2014 -0800
drm/i915/bdw: Reorganize PT
...@lists.freedesktop.org
[mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Ben Widawsky
Sent: Tuesday, November 05, 2013 12:15 PM
To: Intel GFX
Cc: Nikula, Jani; Ben Widawsky; Widawsky, Benjamin
Subject: [Intel-gfx] [PATCH 50/62] [v5] drm/i915/bdw: Support eDP PSR
Broadwell PSR
(and it was broken for me, but I had assumed it never
worked).
Regression from:
commit ed8546ac1f99b850879f07b1e9b06b42fb0a36d9
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Mon Nov 4 22:45:05 2013 -0800
drm/i915/bdw: Support eDP PSR
I am pretty certain PSR is disabled by default
of the unref in the above sequence
really mattered. Looking again though, I don't see anything familiar
- but my suggestion would put me completely at ease.
In either case:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
struct i915_hw_context *
--
Ben Widawsky, Intel Open Source Technology Center
. It was still present on
3.13.0. Actually, i915_gem_retire_work_handler is the only one even
showing up in powertop, which is how it should be IMO.
Therefore I'm not sure what we should do with this.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Ben Widawsky b...@bwidawsk.net
Cc: Ville Syrjälä
: that a similar paranoia could be applied to GGTT via making sure
all entries are invalid ASAP. I think the extra work required to fix
such a BIOS bug is unwarranted until proven necessary.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 16 +---
1 file
)
I915_WRITE(MI_MODE,
_MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
Patch 2, and 3 are:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
--
Ben Widawsky, Intel Open Source Technology Center
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http
that:
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
I think they're both stable material.
And:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
--
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___
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Intel-gfx
: that a similar paranoia could be applied to GGTT via making sure
all entries are invalid ASAP. I think the extra work required to fix
such a BIOS bug is unwarranted until proven necessary.
v2: Remove useless GFP_ZERO in the kcallocs
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915
apoligies.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Ben Widawsky b...@bwidawsk.net
I think Cc: stable too
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
These page table helpers make the code much cleaner. There is some
room to use the arch/x86 header files. The reason I've opted not to is
in several cases, the definitions are dictated by the CONFIG_ options
which do not always indicate the restrictions in the GPU.
Signed-off-by: Ben Widawsky b
On Tue, Feb 25, 2014 at 06:13:44PM -0800, Ben Widawsky wrote:
This patch converts insert_entries and clear_range, both functions which
are specific to the VM. These functions tend to encapsulate the gen
specific PTE writes. Passing absolute addresses to the insert_entries,
and clear_range
On Tue, Feb 25, 2014 at 11:27:15PM -0800, Ben Widawsky wrote:
On Tue, Feb 25, 2014 at 06:13:44PM -0800, Ben Widawsky wrote:
This patch converts insert_entries and clear_range, both functions which
are specific to the VM. These functions tend to encapsulate the gen
specific PTE writes
On Mon, Feb 24, 2014 at 01:27:09PM +0200, Ville Syrjälä wrote:
On Fri, Feb 21, 2014 at 11:38:48AM -0800, Ben Widawsky wrote:
On Fri, Feb 21, 2014 at 05:31:59PM +0200, mika.kuopp...@intel.com wrote:
From: Mika Kuoppala mika.kuopp...@intel.com
Sometimes generic driver code gets
On Mon, Feb 24, 2014 at 08:30:22AM +, Chris Wilson wrote:
On Sun, Feb 23, 2014 at 12:12:25PM -0800, Ben Widawsky wrote:
On Mon, Aug 26, 2013 at 12:06:43PM +0100, Chris Wilson wrote:
Obtaining the forcwake requires expensive and time consuming
serialisation. And we often try to obtain
On Mon, Feb 24, 2014 at 07:03:12PM +0200, Imre Deak wrote:
On Thu, 2014-02-20 at 11:51 -0800, Ben Widawsky wrote:
The previous allocation mechanism would get 2 contiguous allocations,
one for the page directories, and one for the page tables. As each page
table is 1 page, and there are 512
On Sat, Feb 22, 2014 at 08:08:23PM +, Chris Wilson wrote:
On Sat, Feb 22, 2014 at 11:40:43AM -0800, Ben Widawsky wrote:
On Sat, Feb 22, 2014 at 07:37:04PM +, Chris Wilson wrote:
On Sat, Feb 22, 2014 at 11:34:16AM -0800, Ben Widawsky wrote:
On Sat, Feb 22, 2014 at 01:37:16PM +
:
Runtime PM support for Broadwell from Paulo
http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=broadwell
Thanks for your attention.
--
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...@intel.com
This should already be included in the latest upstream libdrm.
commit a254cb50414a5def5c872a765c0dd1295a550c6b
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Thu Jan 2 11:36:59 2014 -0800
intel: Merge latest i915_drm.h
---
include/drm/i915_drm.h | 6 ++
1 file
On Thu, Jan 02, 2014 at 07:50:35PM -1000, Ben Widawsky wrote:
Will full PPGTT support it can be assumed that every file descriptor
gets its own hardware context. As such, there is no need to allocate
anew context in order to use the features provided by hardware contexts.
Eliminating
On Sat, Feb 22, 2014 at 11:34:16AM -0800, Ben Widawsky wrote:
On Sat, Feb 22, 2014 at 01:37:16PM +, Chris Wilson wrote:
On Mon, Feb 17, 2014 at 07:01:44PM -0800, Ben Widawsky wrote:
The names of the struct members for RPS are stupid. Every time I need to
do anything in this code I
On Sat, Feb 22, 2014 at 07:37:04PM +, Chris Wilson wrote:
On Sat, Feb 22, 2014 at 11:34:16AM -0800, Ben Widawsky wrote:
On Sat, Feb 22, 2014 at 01:37:16PM +, Chris Wilson wrote:
On Mon, Feb 17, 2014 at 07:01:44PM -0800, Ben Widawsky wrote:
The names of the struct members for RPS
, \
FORCEWAKE_ALL); \
} \
+ hsw_unclaimed_reg_check(dev_priv, reg); \
REG_WRITE_FOOTER; \
}
Would you mind rebasing this on Mika's recent fix here?
http://patchwork.freedesktop.org/patch/20798/
--
Ben Widawsky, Intel Open Source Technology Center
: Read side doesn't care about shadowed registers,
Remove __needs_put funkiness from gen8_write. (Ville)
Improved commit message.
References: https://bugs.freedesktop.org/show_bug.cgi?id=74007
Cc: Ben Widawsky benjamin.widaw...@intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
On Fri, Feb 21, 2014 at 11:38:48AM -0800, Ben Widawsky wrote:
On Fri, Feb 21, 2014 at 05:31:59PM +0200, mika.kuopp...@intel.com wrote:
From: Mika Kuoppala mika.kuopp...@intel.com
Sometimes generic driver code gets forcewake explicitly by
gen6_gt_force_wake_get(), which check
..
With the rework of the page table allocations, there is no longer a
distinction between number of page table pages, and number of page
directory entries. To avoid confusion, kill the redundant (and newer)
struct member.
Cc: Imre Deak imre.d...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
On Thu, Feb 20, 2014 at 12:37:19PM +0200, Imre Deak wrote:
On Wed, 2014-02-19 at 22:05 -0800, Ben Widawsky wrote:
This patch converts insert_entries and clear_range, both functions which
are specific to the VM. These functions tend to encapsulate the gen
specific PTE writes. Passing
At one time it was expected to be called in multiple places by kref_put.
At the current time however, it is all contained within
i915_gem_context.c.
This patch makes an upcoming required addition a bit nicer since it too
doesn't need to be defined in a header file.
Signed-off-by: Ben Widawsky b
). Instead this
patch pulls the ppgtt struct freeing out of the cleanup and leaves it to
the allocators/callers or the one doing the last kref_put as in standard
convention
Reported-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915
imre.d...@intel.com (v2)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.h | 6 +--
drivers/gpu/drm/i915/i915_gem_gtt.c | 90 +
2 files changed, 54 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
message (Imre)
Plug leaking gen8_pt_pages in both the error path, as well as general
free case (Imre)
v5: Rename leftover which_ variables (Imre)
Add the pde = 0 wrap that was missed from v3 (Imre)
Reviewed-by: Imre Deak imre.d...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers
This got lost when we shuffled around our internal branch and
GEN7_FEATURES macro. There were no HW changes to support FBC, so we just
need to set the flag.
v2: Don't allow FBC for any pipe but A on platforms with DDI. (Paulo)
Cc: Daisy Sun daisy@intel.com
Signed-off-by: Ben Widawsky b
...@intel.com
Either way:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_uncore.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index c628414..25ceac4
if it's non-zero... just
saying, and in such a case we could make the WARN gen specific, and the
dev_priv-uncore.fifo_count = 0 for all platforms.
Reviewed-by: Ben Widawsky b...@bwidawsk.net
--
Ben Widawsky, Intel Open Source Technology Center
___
Intel
On Thu, Feb 13, 2014 at 01:47:57PM +0200, Ville Syrjälä wrote:
On Wed, Feb 12, 2014 at 02:28:43PM -0800, Ben Widawsky wrote:
Rebased series from what I submitted a while ago:
http://lists.freedesktop.org/archives/intel-gfx/2013-December/037815.html
It was mostly a clean rebase
did it in the first place. This addresses one of Imre's
other issues.
Fix error path leak of page tables.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 114
1 file changed, 64 insertions(+), 50 deletions(-)
diff --git
by Imre
Moved number of pd pages assertion to the proper place (Imre)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 172 ++--
1 file changed, 124 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915
On Wed, Feb 19, 2014 at 09:11:46PM +0200, Imre Deak wrote:
On Wed, 2014-02-12 at 14:28 -0800, Ben Widawsky wrote:
The previous allocation mechanism would get 2 contiguous allocations,
one for the page directories, and one for the page tables. As each page
table is 1 page, and there are 512
On Wed, Feb 19, 2014 at 11:00:17PM +0200, Imre Deak wrote:
On Wed, 2014-02-19 at 12:06 -0800, Ben Widawsky wrote:
Create 3 clear stages in PPGTT init. This will help with upcoming
changes be more readable. The 3 stages are, allocation, dma mapping, and
writing the P[DT]Es
One nice
On Wed, Feb 19, 2014 at 11:20:51PM +0200, Imre Deak wrote:
On Wed, 2014-02-19 at 13:06 -0800, Ben Widawsky wrote:
On Wed, Feb 19, 2014 at 09:11:46PM +0200, Imre Deak wrote:
On Wed, 2014-02-12 at 14:28 -0800, Ben Widawsky wrote:
The previous allocation mechanism would get 2 contiguous
On Wed, Feb 19, 2014 at 11:50:51PM +0200, Imre Deak wrote:
On Wed, 2014-02-19 at 12:09 -0800, Ben Widawsky wrote:
Like cleanup in an earlier patch, the code becomes much more readable,
and easier to extend if we extract out helper functions for the various
stages of init.
Note
it's the second
iteration.
Ben Widawsky (9):
drm/i915/bdw: Free PPGTT struct
drm/i915/bdw: Reorganize PPGTT init
drm/i915/bdw: Split ppgtt initialization up
drm/i915: Make clear/insert vfuncs args absolute
drm/i915/bdw: Reorganize PT allocations
Revert drm/i915/bdw: Limit GTT to 2GB
drm
did it in the first place. This addresses one of Imre's
other issues.
Fix error path leak of page tables.
v4: Fix the fix of the error path leak. Original fix still leaked page
tables. (Imre)
Reviewed-by: Imre Deak imre.d...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu
message (Imre)
Plug leaking gen8_pt_pages in both the error path, as well as general
free case (Imre)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 130
2 files changed, 106
/map/etc. or use a common
helper, similar to the ringbuffer code. I don't see a benefit to doing
this just yet, but who knows...
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 141
GEN8 never freed the PPGTT struct. As GEN8 doesn't use full PPGTT, the
leak is small and only found on a module reload. ie. I don't think this
needs to go to stable.
Reported-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915
need
a significant amount more memory simply for the page tables. To address
this, the allocations will be split up in finer amounts.
v2: Replace size_t with uint64_t (Chris, Imre)
Reviewed-by: Imre Deak imre.d...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915
patches fixed/merged:
Reviewed-by: Imre Deak imre.d...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fcde3c7
I keep meaning to do this... by now almost the entire file has been
written by an Intel employee (including Daniel post-2010).
Reviewed-by: Imre Deak imre.d...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
1 file changed, 1 insertion
This cleanup is similar to the GEN8 cleanup (though less necessary).
Having everything split will make cleaning the initialization path error
paths easier to understand.
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915
by Imre
Moved number of pd pages assertion to the proper place (Imre)
v4:
Allocate dma address space for num_pd_pages, not num_pd_entries (Ben)
Don't use gen8_pt_dma_addr after free on error path (Imre)
With new fix from v4 of the previous patch.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3d5dd4a..5f7bee8 100644
--- a/drivers/gpu/drm/i915
(Ville)
Conditionally set .sync_to when semaphores are enabled (Ville)
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 119 +---
1 file changed, 62 insertions(+), 57
commit message
v3: Move everything in the is_semaphore_enabled() check
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 142 ++--
1 file changed, 97 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 39 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +++-
2 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu
-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 33 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
3 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm
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