From: Alex Dai yu@intel.com
Add overview design of GuC, plus some key points related to
the implementation.
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
Documentation/DocBook/drm.tmpl | 19 +++
1 file changed, 19 insertions
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_guc_reg.h | 102 +++
drivers/gpu/drm/i915/intel_guc_fwif.h | 236 ++
2 files changed, 338 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_guc_reg.h
create mode
From: Alex Dai yu@intel.com
Allocate a GEM object to hold GuC log data. A debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
v2:
Add struct members at point of use [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave
]
Rationalise type declarations [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_guc_submission.c | 661 +
drivers/gpu/drm/i915/intel_guc.h | 43 ++
drivers/gpu
@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 2 ++
drivers/gpu/drm/i915/i915_params.c | 9 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b0bb07d..9618f57 100644
: GuC submission setup, phase 1
drm/i915: Enable GuC firmware log
drm/i915: Integrate GuC-based command submission
Documentation/drm: kerneldoc for GuC
Dave Gordon (8):
drm/i915: Add i915_gem_object_create_from_data()
drm/i915: Embedded microcontroller (uC) firmware loading support
drm
This provides a means of reading status and counts relating
to GuC actions and submissions.
v2:
Remove surplus blank line in output [Chris Wilson]
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 40
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index a8f48dd..479c97b 100644
--- a/drivers/gpu/drm/i915
declarations [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 48 +++---
drivers/gpu/drm/i915
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 11 +--
drivers/gpu/drm/i915/intel_guc_loader.c | 51
On 01/07/15 14:02, Daniel Vetter wrote:
On Tue, Jun 30, 2015 at 11:14:54AM -0300, Paulo Zanoni wrote:
2015-06-30 10:54 GMT-03:00 Chris Wilson ch...@chris-wilson.co.uk:
On Tue, Jun 30, 2015 at 02:41:09PM +0100, Michel Thierry wrote:
@@ -1109,7 +1109,7 @@ static void setup_sink_crc(void)
complete environment
than the driver_load stage presents. This can be important for
embedded programmable devices that need firmware loaded from a file
before they can be used.
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm
On 29/06/15 12:39, Jani Nikula wrote:
On Wed, 06 May 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Apr 30, 2015 at 01:54:41PM +0100, Dave Gordon wrote:
On 29/04/15 17:10, yu@intel.com wrote:
From: Alex Dai yu@intel.com
This is to avoid bad IO access caused by writing NOOP
On 26/06/15 08:31, Chris Wilson wrote:
On Thu, Jun 25, 2015 at 01:57:16PM -0700, Yu Dai wrote:
On 06/25/2015 07:40 AM, Dave Gordon wrote:
GuC submission is basically execlist submission, but with the GuC
handling the actual writes to the ELSP and the resulting context
switch interrupts. So
On 24/06/15 11:04, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 07:45:42AM +0200, Sedat Dilek wrote:
I have seen this typo once and added an entry to codespell's dictionary.txt
file.
$ diff -uprN /usr/share/codespell/dictionary.txt.orig
/usr/share/codespell/dictionary.txt
---
On 23/06/15 13:21, Michel Thierry wrote:
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.
In specific, any resource used with flat/heapless (0x-0xf000)
General State Heap (GSH) or Intruction State Heap (ISH) must
On 25/06/15 18:51, Chris Wilson wrote:
On Thu, Jun 25, 2015 at 06:35:14PM +0300, Mika Kuoppala wrote:
During review of dynamic page tables series, I was able
to hit a lite restore bug with execlists. I assume that
due to incorrect pd, the batch run out of legit address space
and into the
On 25/06/15 19:38, Tomas Elf wrote:
On 24/06/2015 18:03, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
An earlier patch was added to reserve space in the ring buffer for the
commands issued during 'add_request()'. The initial version was
pessimistic in the
On 16/06/15 21:38, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:23PM +0100, Arun Siluvery wrote:
+/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
+if (IS_BROADWELL(ring-dev)) {
+struct drm_i915_private *dev_priv = ring-dev-dev_private;
dev_priv =
On 24/06/15 10:32, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 07:28:26PM +0100, Dave Gordon wrote:
On 18/06/15 15:31, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon wrote:
On 17/06/15 13:02, Daniel Vetter wrote:
On Wed, Jun 17, 2015 at 08:23:40AM +0100, Dave
the inline loop with a call.
This will allow a future patch to add a call from another
locations (for now, there are no other calls).
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_gem.c | 85
) and the GuC's debug log.
v2:
Remove redundant initialisation [Chris Wilson]
Defer adding struct members until needed [Chris Wilson]
Local functions should pass dev_priv rather than dev [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon
@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|2 ++
drivers/gpu/drm/i915/i915_params.c |9 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7942ac5..0362f25
From: Alex Dai yu@intel.com
Allocate a GEM object to hold GuC log data. A debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
v2:
Add struct members at point of use [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave
From: Alex Dai yu@intel.com
Add overview design of GuC, plus some key points related to
the implementation.
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
Documentation/DocBook/drm.tmpl | 19 +++
1 file changed, 19
This provides a means of reading status and counts relating
to GuC actions and submissions.
v2:
Remove surplus blank line in output [Chris Wilson]
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 40
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 11 +--
drivers/gpu/drm/i915/intel_guc_loader.c | 51
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_params.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index a8f48dd..479c97b 100644
--- a/drivers/gpu/drm/i915
/i915: Integrate GuC-based command submission
Documentation/drm: kerneldoc for GuC
Dave Gordon (10):
drm/i915: Add i915_gem_object_create_from_data()
drm/i915: Embedded microcontroller (uC) firmware loading support
drm/i915: Add GuC-related header files
drm/i915: Split late for_each_ring
, changing their names to
better describe what they do (they're related to logical ring
contexts rather than to execlists per se).
v2:
Replaces previous drm/i915: Move execlists defines from .c to .h
Issue: VIZ-4884
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_guc_reg.h | 102 ++
drivers/gpu/drm/i915/intel_guc_fwif.h | 236 +
2 files changed, 338 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_guc_reg.h
create mode
loader, thus reducing code duplication
and testing effort.
v2:
Local functions should pass dev_priv rather than dev [Chris Wilson]
Various other improvements per Chris Wilson's review comments
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Alex Dai yu@intel.com
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 45 +++
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915
with the unified firmware loading mechanism by Dave Gordon as well
as new firmware layout etc.
v2:
Various improvements per review comments by Chris Wilson
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/Makefile
be in non-GuC mode, and will be
allowed to complete even if the GuC cannot be loaded or used.
Issue: VIZ-4884
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_gem.c
]
Rationalise type declarations [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_guc_submission.c | 661
drivers/gpu/drm/i915/intel_guc.h | 43 ++
drivers/gpu
declarations [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c|2 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 48 +---
drivers/gpu/drm/i915
-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_gem.c | 39 +++
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b
On 17/06/15 13:43, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 07:36:18PM +0100, Dave Gordon wrote:
This patch series enables command submission via the GuC. In this mode,
instead of the host CPU driving the execlist port directly, it hands
over work items to the GuC, using a doorbell
On 16/06/15 10:28, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:32PM +0100, Dave Gordon wrote:
This provides a means of reading status and counts relating
to GuC actions and submissions.
Anything that ends to ease debugging also tends to ease
postmortem error analysis...
So maybe
On 15/06/15 21:20, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:22PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
intel_guc_api.h contains the subset of the GuC interface that we
will need for submission of commands through the GuC. These MUST
be kept in sync
On 22/06/15 13:37, Chris Wilson wrote:
On Mon, Jun 22, 2015 at 12:59:00PM +0100, Dave Gordon wrote:
On 19/06/15 09:44, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 07:07:46PM +0100, Dave Gordon wrote:
On 18/06/15 13:10, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon
On 17/06/15 16:01, Dave Gordon wrote:
On 15/06/15 21:20, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:22PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
intel_guc_api.h contains the subset of the GuC interface that we
will need for submission of commands through the GuC
On 17/06/15 13:41, Daniel Vetter wrote:
On Wed, Jun 17, 2015 at 02:22:19PM +0200, Daniel Vetter wrote:
On Wed, Jun 17, 2015 at 09:20:44AM +0100, Dave Gordon wrote:
On 16/06/15 10:24, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:30PM +0100, Dave Gordon wrote:
+static void
On 19/06/15 09:44, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 07:07:46PM +0100, Dave Gordon wrote:
On 18/06/15 13:10, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon wrote:
On 17/06/15 13:02, Daniel Vetter wrote:
Domain handling is required for all gem objects
On 22/06/15 16:35, Daniel Vetter wrote:
On Mon, Jun 22, 2015 at 03:18:12PM +0100, Chris Wilson wrote:
On Mon, Jun 22, 2015 at 04:11:01PM +0200, Daniel Vetter wrote:
On Fri, Jun 19, 2015 at 02:04:16PM +0100, Chris Wilson wrote:
Exclude active GPU pages from the purview of the background
On 17/06/15 08:59, Chris Wilson wrote:
On Wed, Jun 17, 2015 at 08:31:59AM +0100, Dave Gordon wrote:
On 16/06/15 10:37, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:26PM +0100, Dave Gordon wrote:
From: Michael H. Nguyen michael.h.ngu...@intel.com
Move defines from intel_lrc.c
On 16/06/15 10:40, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:24PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
The new node provides access to the status of the common uC loader
code and the GuC-specific loader; also the scratch registers used
for communicatio between
On 18/06/15 15:49, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 01:11:34PM +0100, Dave Gordon wrote:
On 17/06/15 13:05, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 07:36:20PM +0100, Dave Gordon wrote:
Current devices may contain one or more programmable microcontrollers
that need to have
On 17/06/15 13:18, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 07:36:25PM +0100, Dave Gordon wrote:
In order to fully initialise the default contexts, we have to execute
batchbuffer commands on the GPU engines. But in the case of GuC-based
batch submission, we can't do that until any required
On 16/06/15 10:35, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:25PM +0100, Dave Gordon wrote:
+static int i915_gem_context_first_open(struct drm_device *dev)
+{
+struct drm_i915_private *dev_priv = dev-dev_private;
+int ret;
+
+/*
+ * We can't enable contexts until
On 18/06/15 21:12, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 10:53:10AM -0700, Yu Dai wrote:
On 06/15/2015 01:30 PM, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:23PM +0100, Dave Gordon wrote:
+ /* Set the source address for the new blob */
+ offset = i915_gem_obj_ggtt_offset
On 15/06/15 22:32, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:27PM +0100, Dave Gordon wrote:
+static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device
*dev,
+u32 size)
+{
+struct drm_i915_gem_object *obj
On 16/06/15 10:22, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:31PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added
On 19/06/15 18:02, Dave Gordon wrote:
On 15/06/15 22:32, Chris Wilson wrote:
[snip]
Try to keep comments to explain why rather than what. Most of the
comments here fall into the i++; // postincrement i category.
-Chris
Most of the what comments in this file are associated with accesses
On 15/06/15 22:55, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:29PM +0100, Dave Gordon wrote:
+/* Get valid workqueue item and return it back to offset */
+static int guc_get_workqueue_space(struct i915_guc_client *gc, u32 *offset)
+{
+struct guc_process_desc *desc;
+void *base
On 17/06/15 13:02, Daniel Vetter wrote:
On Wed, Jun 17, 2015 at 08:23:40AM +0100, Dave Gordon wrote:
On 15/06/15 21:09, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:19PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
i915_gem_object_write() is a generic function to copy data
On 17/06/15 13:05, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 07:36:20PM +0100, Dave Gordon wrote:
Current devices may contain one or more programmable microcontrollers
that need to have a firmware image (aka binary blob) loaded from an
external medium and transferred to the device's memory
On 16/06/15 14:54, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 03:48:09PM +0200, Daniel Vetter wrote:
On Mon, Jun 08, 2015 at 06:33:59PM +0100, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 06:03:21PM +0100, Tomas Elf wrote:
In preparation for per-engine reset add way for setting context reset
On 15/06/15 21:30, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:23PM +0100, Dave Gordon wrote:
+/* We can't enable contexts until all firmware is loaded */
+ret = intel_guc_ucode_load(dev, false);
Pardon. I know context initialisation is broken, but adding to that
breakage
On 18/06/15 13:10, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon wrote:
On 17/06/15 13:02, Daniel Vetter wrote:
Domain handling is required for all gem objects, and the resulting bugs if
you don't for one-off objects are absolutely no fun to track down
On 18/06/15 15:31, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon wrote:
On 17/06/15 13:02, Daniel Vetter wrote:
On Wed, Jun 17, 2015 at 08:23:40AM +0100, Dave Gordon wrote:
On 15/06/15 21:09, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:19PM +0100, Dave
On 17/06/15 12:04, Daniel Vetter wrote:
On Fri, Jun 12, 2015 at 09:25:36PM +0100, Dave Gordon wrote:
Updated version split into two. The first tidies up the _ring_prepare()
functions and removes the corner case where we might have had to wait
twice; the second is a temporary workaround
On 16/06/15 10:37, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:26PM +0100, Dave Gordon wrote:
From: Michael H. Nguyen michael.h.ngu...@intel.com
Move defines from intel_lrc.c to i915_reg.h so they are accessible
to the GuC submission code; and expose a previously static function
On 15/06/15 21:09, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:19PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
i915_gem_object_write() is a generic function to copy data from a plain
linear buffer to a paged gem object.
We will need this for the microcontroller firmware
On 16/06/15 10:24, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:30PM +0100, Dave Gordon wrote:
+static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
+{
+struct intel_engine_cs *ring;
+int i, irqs;
+
+/* tell all command streamers to forward interrupts
On 15/06/15 21:20, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:22PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
intel_guc_api.h contains the subset of the GuC interface that we
will need for submission of commands through the GuC. These MUST
be kept in sync
On 15/06/15 11:53, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 11:33:37AM +0100, Dave Gordon wrote:
On 13/06/15 09:28, Chris Wilson wrote:
On Fri, Jun 12, 2015 at 06:30:56PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We tried to fix this in the following commit
On 15/06/15 21:41, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:11:37PM +0100, Dave Gordon wrote:
It still applies. If you submit say 1024 interrupted execbuffers they
What is an interrupted execbuffer? AFAICT we hold the struct_mutex while
stuffing the ringbuffer so we can only ever
On 13/06/15 09:28, Chris Wilson wrote:
On Fri, Jun 12, 2015 at 06:30:56PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We tried to fix this in the following commit:
commit fdc454c1484a20e1345cf4e4d7a9feaee814147f
Author: Michel Thierry michel.thie...@intel.com
On 12/06/15 22:30, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We tried to fix this in the following commit:
commit fdc454c1484a20e1345cf4e4d7a9feaee814147f
Author: Michel Thierry michel.thie...@intel.com
Date: Tue Mar 24 15:46:19 2015 +
drm/i915: Prevent
On 15/06/15 13:34, Daniel Vetter wrote:
On Fri, Jun 05, 2015 at 12:27:21PM +0300, Ville Syrjälä wrote:
On Fri, Jun 05, 2015 at 12:24:45PM +0300, Jani Nikula wrote:
On Thu, 04 Jun 2015, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Thu, Jun 04, 2015 at 04:56:18PM +0100, Damien Lespiau
requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_params.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 5134095..926a6df 100644
--- a/drivers/gpu/drm/i915
On 15/06/15 11:07, Daniel Vetter wrote:
On Thu, Jun 04, 2015 at 03:36:32PM +0100, Dave Gordon wrote:
On 04/06/15 06:59, Sagar Arun Kamble wrote:
Hi Daniel,
We already are grabbing RPM reference before start of DMC FW load and
release post load completion.
DC5/6 can happen without Runtime
loader, thus reducing code duplication
and testing effort.
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/Makefile |3 +
drivers/gpu/drm/i915/intel_uc_loader.c | 312
drivers/gpu
the GuC firmware and setting it running. Some of these also need
to be kept in sync with the firmware.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |4 +-
drivers/gpu/drm/i915/intel_guc.h
with the unified firmware loading mechanism by Dave Gordon as well
as new firmware layout etc.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/Makefile |3 +
drivers/gpu/drm/i915/i915_dma.c
@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|2 ++
drivers/gpu/drm/i915/i915_params.c |9 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9094c06..731a1c8
be in non-GuC mode, and will be
allowed to complete even if the GuC cannot be loaded or used.
Issue: VIZ-4884
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_gem.c
) and the GuC's debug log.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/Makefile |3 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 122
drivers/gpu/drm/i915
From: Alex Dai yu@intel.com
Allocate a GEM object to hold GuC log data. A debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915
-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_guc_submission.c | 668
drivers/gpu/drm/i915/intel_guc.h |5 +
drivers/gpu/drm/i915/intel_guc_loader.c| 10 +
3 files changed, 683
From: Michael H. Nguyen michael.h.ngu...@intel.com
Move defines from intel_lrc.c to i915_reg.h so they are accessible
to the GuC submission code; and expose a previously static function
in the execlist code which will also be required for GuC submission.
Issue: VIZ-4884
Signed-off-by: Michael H.
-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 37 +++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 47636f3..c52a745 100644
--- a/drivers/gpu/drm
This provides a means of reading status and counts relating
to GuC actions and submissions.
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 41 +++
1 file changed, 41
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 11 +--
drivers/gpu/drm/i915/intel_guc_loader.c | 51
On 15/06/15 10:15, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 07:51:36PM +0100, Dave Gordon wrote:
The original idea of preallocating the OLR was implemented in
9d773091 drm/i915: Preallocate next seqno before touching the ring
and the sequence of operations was to allocate the OLR
: Implementation of GuC client
drm/i915: Integrate GuC-based command submission
Documentation/drm: kerneldoc for GuC
Dave Gordon (5):
drm/i915: Embedded microcontroller (uC) firmware loading support
drm/i915: Defer default hardware context initialisation until first
drm/i915: Interrupt routing for GuC
From: Alex Dai yu@intel.com
i915_gem_object_write() is a generic function to copy data from a plain
linear buffer to a paged gem object.
We will need this for the microcontroller firmware loading support code.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave
On 15/06/15 15:10, Siluvery, Arun wrote:
On 12/06/2015 18:03, Dave Gordon wrote:
On 12/06/15 12:58, Siluvery, Arun wrote:
On 09/06/2015 19:43, Dave Gordon wrote:
On 05/06/15 14:57, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies
On 12/06/15 19:12, Chris Wilson wrote:
On Fri, Jun 12, 2015 at 06:09:07PM +0100, Dave Gordon wrote:
When calculating the available space in a ringbuffer, we should
use the effective_size rather than the true size of the ring.
v2: rebase to latest drm-intel-nightly
v3: rebase to latest drm
described in the two commits mentioned above. So this
commit moves the calls to i915_gem_request_alloc() into the middle of
{__intel,logical}_ring_prepare() rather than either before or after them.
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c
of the ringbuffer), and
then again to get enough space for the new data that the caller
wants to add.
Now we just precalculate the total amount of space we'll need
*including* any for padding at the end of the ringbuffer and wait
for that much in one go.
Signed-off-by: Dave Gordon david.s.gor...@intel.com
On 12/06/15 19:05, Chris Wilson wrote:
On Fri, Jun 12, 2015 at 06:09:08PM +0100, Dave Gordon wrote:
The original idea of preallocating the OLR was implemented in
9d773091 drm/i915: Preallocate next seqno before touching the ring
and the sequence of operations was to allocate the OLR
Updated version split into two. The first tidies up the _ring_prepare()
functions and removes the corner case where we might have had to wait
twice; the second is a temporary workaround to solve a kernel OOPS that
can occur if logical_ring_begin is called while the ringbuffer is not
mapped because
When calculating the available space in a ringbuffer, we should
use the effective_size rather than the true size of the ring.
v2: rebase to latest drm-intel-nightly
v3: rebase to latest drm-intel-nightly
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c
Updates and supersedes the referenced patch,
Reinstate order of operations in {intel,logical}_ring_begin()
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now we have to fix it in both paths ...
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c| 64 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 63 +++---
2 files changed, 64 insertions(+), 63
On 12/06/15 12:58, Siluvery, Arun wrote:
On 09/06/2015 19:43, Dave Gordon wrote:
On 05/06/15 14:57, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
MI_LOAD_REGISTER_REG; Add GEN8 specific
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