Re: [Intel-gfx] [PATCH 1/5] drm/i915: Do a full device reset after being wedged

if (intel_has_reset_engine(dev_priv)) { > + if (intel_has_reset_engine(dev_priv) && > + !i915_terminally_wedged(_priv->gpu_error)) { NOT terminally wedged AND can reset individually reads clearer, but either way: Reviewed-by: Joonas Lahtinen Regards, Joonas

Re: [Intel-gfx] [PATCH 2/2] drm/i915/tracepoints: Remove DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option

e application/library/whatever userspace component to demonstrate the suitability of the kernel interface and act as a counterpart for the kernel interface that can be tested and debugged for changes. This too, is explained in more detail in the above linked documentation chapter. Regards, Joon

Re: [Intel-gfx] [PATCH 2/2] drm/i915/tracepoints: Remove DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option

Quoting Tvrtko Ursulin (2018-08-22 15:49:52) > > On 21/08/2018 13:06, Joonas Lahtinen wrote: > > Quoting Kukanova, Svetlana (2018-08-13 16:44:49) > >> Joonas, sorry for interfering; could you please explain more regarding the > >> options for tracing scheduling

Re: [Intel-gfx] [PATCH 2/2] drm/i915/tracepoints: Remove DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option

nk you, > Svetlana > > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Joonas Lahtinen > Sent: Monday, August 13, 2018 12:55 PM > To: Chris Wilson ; Intel-gfx@lists.freedesktop.org; > Tvrtko Ursulin ; Tvrtko Ursulin >

Re: [Intel-gfx] [PATCH 2/2] drm/i915/tracepoints: Remove DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option

Quoting Tvrtko Ursulin (2018-08-08 15:56:01) > On 08/08/2018 13:42, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-08-08 13:13:08) > This is true, no disagreement. My point simply was that we can provide > this info easily to anyone. There is a little bit of analogy with perf > scheduler

Re: [Intel-gfx] [PATCH] drm/i915/lpe: Mark LPE audio as "no callbacks"

xes: 183c00350ccd ("drm/i915: Fix runtime PM for LPE audio") > Testcase: igt/pm_rpm/basic-pci-d3-state > Testcase: igt/pm_rpm/basic-rte > Signed-off-by: Chris Wilson > Cc: Takashi Iwai > Cc: Pierre-Louis Bossart > Cc: Ville Syrjälä > Cc: sta...@vger.kernel.o

Re: [Intel-gfx] [PATCH] drm/i915: Interactive RPS mode

ock; Please describe the new mutex with a few words because it's not immediately obvious which members fall under it. This kind of a change could always use some Tested-by's. Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx m

Re: [Intel-gfx] [PATCH v6] drm/i915: Add IOCTL Param to control data port coherency.

Quoting Lis, Tomasz (2018-07-18 18:28:32) > > On 2018-07-18 16:42, Tvrtko Ursulin wrote: > > > > On 18/07/2018 14:24, Joonas Lahtinen wrote: > >> Quoting Tomasz Lis (2018-07-16 16:07:16) > >>> +++ b/include/uapi/drm/i915_drm.h > >>> @@ -1

Re: [Intel-gfx] [PATCH v9 7/7] drm/i915: add a sysfs entry to let users set sseu configs

Quoting Bloomfield, Jon (2018-07-18 19:44:14) > > -Original Message- > > From: Intel-gfx On Behalf Of > > Tvrtko Ursulin > > Sent: Thursday, June 14, 2018 1:29 AM > > To: Joonas Lahtinen ; Chris Wilson > > ; Landwerlin, Lionel G > > ; intel

Re: [Intel-gfx] [PATCH v6] drm/i915: Add IOCTL Param to control data port coherency.

Quoting Tomasz Lis (2018-07-16 16:07:16) > +static int emit_set_data_port_coherency(struct i915_request *rq, bool enable) > +{ > + u32 *cs; > + i915_reg_t reg; > + > + GEM_BUG_ON(rq->engine->class != RENDER_CLASS); > + GEM_BUG_ON(INTEL_GEN(rq->i915) < 9); > + > + cs =

Re: [Intel-gfx] [PATCH v1] drm/i915: Add IOCTL Param to control data port coherency.

Quoting Dunajski, Bartosz (2018-06-22 19:40:58) > Additionally, we are already on Arch: > https://aur.archlinux.org/packages/compute-runtime I'm not an Arch user myself, but my impression is that AUR [1] is equivalent of Ubuntu's PPA where anybody can very much upload anything outside of the

Re: [Intel-gfx] [PATCH v1] drm/i915: Add IOCTL Param to control data port coherency.

Quoting Lis, Tomasz (2018-06-21 16:47:45) > On 2018-06-21 08:39, Joonas Lahtinen wrote: > > Quoting Tomasz Lis (2018-06-20 18:03:07) > >> int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, > >>

Re: [Intel-gfx] [PATCH] drm/i915: Ignore applying the self-relocation BIAS if no relocations

e... > > References: https://bugs.freedesktop.org/show_bug.cgi?id=106744#c1 > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen Long commit message short; don't need to bias the batch buffer if it doesn't reference itself via an address... Reviewed-by: Joonas Lahtinen Regards

Re: [Intel-gfx] [PATCH] drm/i915: Redefine EINVAL for debugging

Quoting Chris Wilson (2018-06-21 11:01:50) > To aide debugging spurious EINVALs, include a debug message every time > we emit one from execbuf. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=106744 > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen That's sp

Re: [Intel-gfx] [PATCH v1] drm/i915: Add IOCTL Param to control data port coherency.

+ Dave Airlie (The DRM subsystem maintainer) for FYI Quoting Dunajski, Bartosz (2018-06-21 10:31:57) > I would like to add few things that were mentioned previously. > > According to adoption plan. > Our plan is to drop dependency on LLVM 4.0.1 (with custom patches) and > instead compile with

Re: [Intel-gfx] [PATCH v1] drm/i915: Add IOCTL Param to control data port coherency.

lates a plain OCL buffer (non-fine-grain) with > payload > for kern_worker. Once kern_master is done, kern_worker kicks-in and processes > the payload that kern_master produced. These two kernels work in a loop, one > after another. Since only kern_master requires coherency, kern_worker should >

Re: [Intel-gfx] [PATCH i-g-t 1/2] lib: Spin fast, retire early

000 NOPs add on order of 5us, which is often larger > than the target latency. > > Signed-off-by: Chris Wilson > Reviewed-by: Antonio Argenziano Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lis

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Avoid ERR_PTR dereference

-by: Dan Carpenter > Fixes: 09a4c02e58c1 ("drm/i915: Look for an active kernel context before > switching") > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Regards, Joonas _

Re: [Intel-gfx] [PATCH i-g-t 3/6] igt/gem_sync: Double the wakeups, twice the pain

Quoting Chris Wilson (2018-06-19 13:49:17) > To further defeat any contemplated spin-optimisations to avoid the irq > latency for synchronous wakeups, increase the queue length. > > Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen Reg

Re: [Intel-gfx] [PATCH i-g-t 2/6] igt/gem_sync: Alternate stress for nop+sync

they do not occur in practice). And the second role it fulfils, is that > it provides a very crude estimate for how long it takes for a nop to > execute from a running start (we already have a complimentary estimate > for an idle start). > > Signed-off-by: Chris Wilson > Cc: Joonas L

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] lib: Conservatively include residue buffers in the available ram estimate

conservative and only allow them to be swapped out. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=105967 > Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.

Re: [Intel-gfx] 4.18-rc1 i915 dma mapping warning

+ Chris, Somehow this message managed to dodge the mailing list? Regards, Joonas Quoting Dave Jones (2018-06-19 05:52:23) > The new DMA mapping debug option in 4.18-rc1 (CONFIG_DMA_API_DEBUG_SG) seems > to dislike something about i915.. > > [1.203923] i915 :00:02.0: DMA-API: mapping

Re: [Intel-gfx] [PATCH] drm/i915: Apply context workarounds directly

sh them though, because we would like to > check their validity using i-g-t, and that means making sure we have > a context loaded for ctx-residing WAs). > > Signed-off-by: Oscar Mateo > Cc: Chris Wilson > Cc: Joonas Lahtinen > Cc: Ville Syrjälä Reviewed-by: Joonas Lahtinen

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Pull the w/a LRI emission into a helper

nly need add new registers to that table > rather than try and remember important side-effects of earlier chunks of > GPU instructions. > > Suggested-by: Joonas Lahtinen > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen Not related to this patch, but the lack of OOB check for

Re: [Intel-gfx] [PATCH v2] drm/i915: Fix fallout of fake reset along resume

ring everything is powered up. > > Fixes: b2209e62a450 ("drm/i915/execlists: Reset the CSB head tracking on > reset/sanitization") > Fixes: 1288786b18f7 ("drm/i915: Move GEM sanitize from resume_early to > resume") > Signed-off-by: Chris Wilson > Cc:

Re: [Intel-gfx] [PATCH] drm/i915: Only show debug for state changes when banning

("drm/i915: Fix context ban and hang accounting for > client") > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://list

Re: [Intel-gfx] [PATCH] drm/i915: Enable provoking vertex fix on Gen9 systems.

gned-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen One note below. > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1575,11 +1575,21 @@ static u32 *gen9_init_indirectctx_bb(struct > intel_engine_cs *engine, u32 *batch) > /* WaFlushCoherentL3CacheLin

Re: [Intel-gfx] [PATCH v2] drm/i915: Dump the ringbuffer of the active request for debugging

-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 0/7] drm/i915: move towards kernel types

Quoting Jani Nikula (2018-06-15 12:08:23) > On Thu, 14 Jun 2018, Rodrigo Vivi wrote: > > On Wed, Jun 13, 2018 at 09:55:38AM +0300, Jani Nikula wrote: > >> On Tue, 12 Jun 2018, Lucas De Marchi wrote: > >> > On Tue, Jun 12, 2018 at 3:15 AM Jani Nikula > >> > wrote: > >> >> > >> >> On Tue, 12 Jun

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: Full ppgtt everywhere, no excuses

Chris Wilson > Cc: Ville Syrjälä > Cc: Joonas Lahtinen For the rather limited scope of the patch, can you Ville give a Tested-by? Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https:

Re: [Intel-gfx] [PATCH 1/2] drm/i915/gtt: Enable full-ppgtt by default everywhere

ive, in turn making GPU dispatch far more efficient and > more secure (due to better mm segregation). On the other hand, switching > over to a different GTT for every client does incur noticeable overhead. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Prevent writing into a read-only object via a GGTT mmap

ttempted writes. Fortunately, this is known a priori, so we > can at least reject in the call to create the mmap (with a sanity check > in the fault handler). > > v2: Check the vma->vm_flags during mmap() to allow readonly access. > > Signed-off-by: Chris Wilson > Cc: Jon

Re: [Intel-gfx] [PATCH 2/5] drm/i915/gtt: Read-only pages for insert_entries on bdw+

Chris Wilson > Cc: Joonas Lahtinen > Cc: Matthew Auld > Reviewed-by: Joonas Lahtinen #v1 > Reviewed-by: Matthew Auld #v1 > +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c > @@ -23,6 +23,7 @@ > */ > > #include "../i915_selftest.h" > +#inc

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Show CCID in engine dumps

here? Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Make the hexdump row offset visually distinct

Quoting Chris Wilson (2018-06-14 12:41:01) > Currently we use %08x for the row offset, and %08x for the binary > contents of the buffer. This makes it very easily to confuse the two, so > switch to using [%04x] for the start-of-row offset. > > Signed-off-by: Chris Wilson Revi

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Dump the ringbuffer of the active request for debugging

ht make it more readable by quick glance. Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Move GEM sanitize from resume_early to resume

resume phase, but as we are about to completely > restore the GTT mappings, we first need to stop the GPU using them i.e. > perform a GPU reset (i915_gem_sanitize()). > > Testcase: igt/gem_exec_suspend/basic-S4-devices > Signed-off-by: Chris Wilson > Cc: Imre Deak > Cc: Joonas Lahtin

Re: [Intel-gfx] [PATCH] drm/i915: Make closing request flush mandatory

-by: Chris Wilson No word about perf impact? The patch description matches what it does. Assuming we're not murdering any testcases; Reviewed-by: Joonas Lahtinen Regards, Joonas > --- > drivers/gpu/drm/i915/i915_gem.c| 4 ++-- > drivers/gpu/drm/i915/i915_gem_context.c

Re: [Intel-gfx] [PATCH v9 7/7] drm/i915: add a sysfs entry to let users set sseu configs

Quoting Tvrtko Ursulin (2018-06-12 15:02:07) > > On 12/06/2018 11:52, Lionel Landwerlin wrote: > > On 12/06/18 11:37, Chris Wilson wrote: > >> Quoting Lionel Landwerlin (2018-06-12 11:33:34) > >>> On 12/06/18 10:20, Joonas Lahtinen wrote: > >>&g

Re: [Intel-gfx] [PATCH v2] drm/i915: add support for perf configuration queries

Quoting Lionel Landwerlin (2018-06-12 19:54:41) > Listing configurations at the moment is supported only through sysfs. > This might cause issues for applications wanting to list > configurations from a container where sysfs isn't available. > > This change adds a way to query the number of

Re: [Intel-gfx] [PATCH v9 7/7] drm/i915: add a sysfs entry to let users set sseu configs

Quoting Chris Wilson (2018-06-11 18:02:37) > Quoting Lionel Landwerlin (2018-06-11 14:46:07) > > On 11/06/18 13:10, Tvrtko Ursulin wrote: > > > > > > On 30/05/2018 15:33, Lionel Landwerlin wrote: > > >> There are concerns about denial of service around the per context sseu > > >> configuration

Re: [Intel-gfx] [PATCH] drm/i915/oa: Check that OA is disabled before unpinning

Quoting Lionel Landwerlin (2018-05-17 13:29:56) > On 17/05/18 11:21, Chris Wilson wrote: > > Quoting Lionel Landwerlin (2018-05-17 11:18:16) > >> This should be sent to stable right? > > Yeah, my bad for not digging out the relevant Fixes: +cc Joonas for > > the next batch. -Chris > > I should

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Use unknown production revid as alpha quality flag

Quoting Mika Kuoppala (2018-06-08 16:42:03) > We don't need to have distinct flag for alpha quality if > we agree that setting the first production revid to be the > epoch for stepping out from alpha quality on that platform. Well, I'm hoping we won't be at the phase when the product is shipping

Re: [Intel-gfx] [PATCH 12/17] drm/i915/gtt: Free unused page tables on unbind the context

eing evicted) free the unused ptes. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld > Reviewed-by: Matthew Auld Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list I

Re: [Intel-gfx] [PATCH 11/17] drm/i915/gtt: Lazily allocate page directories for gen7

ser contexts, we need to be more prudent > in our allocations, and defer the page allocation until it is used. We > don't recover unused pages yet as we found that doing so on the fly > (i.e. altering TLB entries) would confuse the GPU. > > Signed-off-by: Chris Wilson > C

Re: [Intel-gfx] [PATCH 09/17] drm/i915/gtt: Make gen6 page directories evictable

ge directory into a first class and > unbindable vma. Hence, the creation of a custom vma to wrap the page > directory as opposed to a GEM object. > > In this patch, we leave the page directories pinned upon creation. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen &

Re: [Intel-gfx] [PATCH 08/17] drm/i915/gtt: Onionify error handling for gen6_ppgtt_create

f-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld > Reviewed-by: Matthew Auld Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesk

Re: [Intel-gfx] [PATCH 06/17] drm/i915/ringbuffer: Serialize load of PD_DIR

page tables). > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld Again, commit message checks out with code. Do you have your own bug-triaging flowchart that you come up with these W/As? :) Reviewed-by: Joonas

Re: [Intel-gfx] [PATCH 05/17] drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories

ed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 04/17] drm/i915: Wrap around the tail offset before setting ring->tail

el_ring_wrap()). > > v2: Double check execlists as well > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld > Cc: Tvrtko Ursulin Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-

Re: [Intel-gfx] [PATCH 03/17] drm/i915/ringbuffer: Fix context restore upon reset

Sandybridge has to agree to use LRI as well. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld > Cc: Tvrtko Ursulin Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 02/17] drm/i915/ringbuffer: Brute force context restore

trip through the kernel_context, > forcing the context to be saved and restored; thereby reloading the > PP_DIR registers and updating the modified page directory! > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld Commit message

Re: [Intel-gfx] [PATCH 01/17] drm/i915: Apply batch location restrictions before pinning

erences: https://bugs.freedesktop.org/show_bug.cgi?id=105720 > Fixes: 2889caa92321 ("drm/i915: Eliminate lots of iterations over the > execobjects array") > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Martin Peres Reviewed-by: Joonas Lahtinen Regards, Jo

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add WaKBLVECSSemaphoreWaitPoll

THSD#2227190, HSDES#1604216706, BSID#0917 > Signed-off-by: Mika Kuoppala Skip the RCS engine and this is; Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PULL] gvt-fixes for 4.17

Quoting Zhenyu Wang (2018-06-06 10:49:54) > On 2018.04.19 15:39:48 +0800, Zhenyu Wang wrote: > > > > Hi, > > > > Here's current gvt fixes for 4.17 with several kernel warning > > and other misc fixes as detailed below. > > > > p.s: I'll be on vacation from next week till May 2, Zhi will cover

Re: [Intel-gfx] [PATCH 06/11] drm/i915/gtt: Subclass gen6_hw_ppgtt

. This patch moves the gen6 only features out to > gen6_hw_ppgtt and pipes the new type everywhere that needs it. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld It's at times confusing when gen6_foo takes either the ppgtt or ppgt

Re: [Intel-gfx] [PATCH 05/11] drm/i915/gtt: Push allocation to hw ppgtt constructor

Quoting Chris Wilson (2018-06-05 10:19:43) > In the next patch, we will subclass the gen6 hw_ppgtt. In order, for the > two different generations of hw ppgtt stucts to be of different size, > push the allocation down to the constructor. > > Signed-off-by: Chris Wilson > Cc: Joo

Re: [Intel-gfx] [PATCH 03/11] drm/i915: Prepare for non-object vma

d the core code (such as i915_vma_pin/insert/bind/unbind) to work > regardless of the innards. > > The remaining eyesore here is vma->obj->cache_level and related (but > less of an issue) vma->obj->gt_ro. With a bit of care we should mirror > those on the vma itself. > > Si

Re: [Intel-gfx] [PATCH] drm/i915/ringbuffer: Make context pin/unpin symmetric

d, not least, to improve the readability of the > code. > > Suggested-by: Joonas Lahtinen > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld Regards, Joonas ___ Intel-gfx mailing list Inte

Re: [Intel-gfx] [PATCH 04/11] drm/i915: Decouple vma vfuncs from vm

the opportunity to later override the > operation for a custom vma. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h > @@ -58,6 +58,7 @@ > > struct drm_i915_file_pri

Re: [Intel-gfx] [PATCH 10/11] drm/i915/gtt: Only keep gen6 page directories pinned while active

ed a request. > > For the kernel_context (and thus aliasing_ppgtt), it remains pinned at > all times, as the kernel_context itself is pinned at all times. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld > @@ -1321,

Re: [Intel-gfx] [PATCH 02/11] drm/i915/gtt: Teach restore-gtt to walk the ggtt vma list not the object list

ggtt entries. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld Comment below. Reviewed-by: Joonas Lahtinen > @@ -3578,21 +3578,15 @@ void i915_gem_restore_gtt_mappings(struct > drm_i915_private *dev_priv) > ggtt->

Re: [Intel-gfx] [PATCH] drm/i915: Add new vGPU cap info bit VGT_CAPS_HUGE_GTT

> > Signed-off-by: Changbin Du Reviewed-by: Joonas Lahtinen I'll merge this. Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Apply the full CPU domain markup before freezing

simply mark the objects as being in the CPU domain, bypassing the > flushes. Let's call the full domain transfer function so that we have > less special case code (and symmetry with the suspend path) even though > it will be mostly redundant. > > Signed-off-by: Chris Wilson > Cc: Joonas

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Flush all writes before suspend

n some cases they will be mmio read to ensure the GGTT writes are > indeed flushed, and clflushes to ensure that cpu writes are in memory). > > It seems prudent and the safer course for us to ensure all writes are > flushed to memory before suspend. > > Signed-off-by: Chris Wilson >

Re: [Intel-gfx] [PATCH 2/6] drm/i915/gtt: Don't restore the non-existent PDE for GGTT

ciated ppgtt and so the restore works just fine. We would have a > similar problem if we tried disabling aliasing-ppgtt > (i915.enable_ppgtt=0). So skip the empty ppgtt, as being non-existent it > doesn't need restoring. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen

Re: [Intel-gfx] [PATCH 5/5] drm/i915/userptr: Enable read-only support on gen8+

ad-only flag for userptr! > > Testcase: igt/gem_userptr_blits/readonly* > Signed-off-by: Chris Wilson > Cc: Jon Bloomfield > Cc: Joonas Lahtinen Please add clarification to the commit message that this expands uAPI (by supporting RO userptrs), so Rodrigo will notice to highli

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Reject attempted pwrites into a read-only object

On Thu, 2018-05-31 at 12:35 +0100, Chris Wilson wrote: > If the user created a read-only object, they should not be allowed to > circumvent the write protection using the pwrite ioctl. > > Signed-off-by: Chris Wilson > Cc: Jon Bloomfield > Cc: Joonas Lahtinen > Cc: Mat

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Prevent writing into a read-only object via a GGTT mmap

e > readonly object pure. (It is easier to lift a restriction than to impose > it later!) > > Signed-off-by: Chris Wilson > Cc: Jon Bloomfield > Cc: Joonas Lahtinen > Cc: Matthew Auld As discussed in IRC, this is no change to previous uAPI as read-only objects have not been ava

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gtt: Read-only pages for insert_entries on bdw+

On Thu, 2018-05-31 at 10:19 +0100, Chris Wilson wrote: > From: Jon Bloomfield > > Hook up the flags to allow read-only ppGTT mappings for gen8+ > > Signed-off-by: Jon Bloomfield > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Matthew Auld Reviewed-by: J

Re: [Intel-gfx] [PATCH 1/3] drm/i915/gtt: Add read only pages to gen8_pte_encode

ings (necessary for > importing PROT_READ vma). > > Signed-off-by: Jon Bloomfield > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Matthew Auld Reviewed-by: Joonas Lahtinen Regards, Joonas -- Joonas Lahtinen Open Source

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, One potential Spectre vector plugging patch, a NULL deref fix and a DMI info fix reported by user. This is still based on -rc6 as my flight was delayed last week to the extent I missed possibility of sending the PR. For 4.19, Rodrigo will be picking up drm-next after Jani is done with

Re: [Intel-gfx] linux-next: build failure after merge of the drm-intel-fixes tree

Quoting Stephen Rothwell (2018-05-29 12:26:05) > Hi all, > > After merging the drm-intel-fixes tree, today's linux-next build (i386 > defconfig) failed like this: Thanks for reporting. I've added a patch to fix the issue now. I'll talk with our CI team about testing 32-bit building to try to

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Limit searching for PIN_HIGH

Quoting Chris Wilson (2018-05-18 13:07:16) > Quoting Joonas Lahtinen (2018-05-18 11:05:36) > > Quoting Chris Wilson (2018-05-13 10:50:09) > > > To no surprise (since we've flip-flopped over the use of PIN_HIGH a few > > > times), doing a search by address over

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Pin the ring high

ng evictions and GPU stalls. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Regards, Joonas _

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Limit searching for PIN_HIGH

nk searching a million holes while under > struct_mutex), limit the search for the highest available hole and > fallback to best-fit if it fails. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Some testcase

Re: [Intel-gfx] [PATCH 2/4] drm/mm: Add a search-by-address variant to only inspect a single hole

ilson <ch...@chris-wilson.co.uk> > Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> > +++ b/include/drm/drm_mm.h > @@ -109,6 +109,10 @@ enum drm_mm_insert_mode { > * Allocates the node from the bottom of the found hole. > */ > DRM_MM_I

Re: [Intel-gfx] [PATCH 1/4] drm/mm: Reject over-sized allocation requests early

need to invert our sorting. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Regards, Joonas ___

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, Nothing too big this time either, a missing W/A added and fix for rare HW race in addition to early IOCTL error check. We got kthread_park related splats to CI from -rc5, so the results are to be taken with a pinch of salt. The fix to factor around it is bit too much for -fixes and

Re: [Intel-gfx] [PATCH v6 14/14] drm/i915: Enable platform support for vGPU huge gtt pages

This is a purely a gvt patch too, so the patch subject should reflect that. Regards, Joonas Quoting changbin...@intel.com (2018-05-08 12:05:16) > From: Changbin Du > > Now GVTg supports shadowing both 2M/64K huge gtt pages. So let's turn on > the cap info bit

Re: [Intel-gfx] [PATCH v2] gpu: drm: i915: Change return type to vm_fault_t

Quoting Souptick Joarder (2018-04-17 22:02:02) > Use new return type vm_fault_t for fault handler. For > now, this is just documenting that the function returns > a VM_FAULT value rather than an errno. Once all instances > are converted, vm_fault_t will become a distinct type. > > Reference id ->

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, Not quite the explosion you were afraid of, but three fixes to avoid a some WARNs and *ERROR*s. I'm still trying to get an Ack for merging the ICL stolen early quirks through our tree and then including them in the next -fixes (I know we're bit late :( ) I'm travelling for the rest of

Re: [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Cache the priolist when rescheduling

hris Wilson <ch...@chris-wilson.co.uk> Comment below. Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 11 --- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_l

Re: [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Drop unused parameter to lookup_priolist()

Quoting Chris Wilson (2018-05-08 03:30:45) > lookup_priolist() no longer attaches the request into the priolist, it > just returns the priolist for the given priority instead. Drop the > unused parameter. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewe

Re: [Intel-gfx] [PATCH 1/2] x86/gpu: reserve ICL's graphics stolen memory

be needed, it was introduced in v4.17-rc1 only. Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Regards, Joonas > Cc: Ingo Molnar <mi...@kernel.org> > Cc: H. Peter Anvin <h...@zytor.com> > Cc: x...@kernel.org > Cc: Daniele Ceraolo Spurio <daniele.ce

Re: [Intel-gfx] [PATCH] drm/i915: Don't request a bug report for unsafe module parameters

ferences: https://bugs.freedesktop.org/show_bug.cgi?id=106423 > Fixes: d15d7538c6d2 ("drm/i915: Tune down init error message due to failure > injection") > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Imre Deak <imre.d...@intel.com> > Cc: Jani Nikula <jani.nik.

Re: [Intel-gfx] [PATCH] drm/i915/gtt: Tidy up duplicate branches in gen8_gmch_probe()

ille.syrj...@linux.intel.com> > References: f773568b6ff8 ("drm/i915: nuke the duplicated stolen discovery") > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Matthew Auld <matthew.a...@intel.com> > Cc: Joonas Lahtinen <joonas.lahti...@linux.inte

Re: [Intel-gfx] [RFC v1] drm/i915: Add Exec param to control data port coherency.

Quoting Lis, Tomasz (2018-03-20 19:23:03) > > > On 2018-03-19 15:26, Chris Wilson wrote: > > Quoting Lis, Tomasz (2018-03-19 14:14:19) > > > On 2018-03-19 13:43, Chris Wilson wrote: > > Quoting Tomasz Lis (2018-03-19 12:37:35) > > The patch adds a

Re: [Intel-gfx] [PATCH rdma-next 01/21] drm/i915: Move u64-to-ptr helpers to general header

ff-by: Leon Romanovsky <leo...@mellanox.com> Feel free to merge this through an appropriate tree, I guess you could get some acks from LKML. Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Regards, Joonas > --- > drivers/gpu/drm/i915/i915_utils.h | 12 ++---

Re: [Intel-gfx] [PATCH] drm/i915/icl, x86/gpu: implement ICL stolen memory support

Quoting Chris Wilson (2018-05-03 18:35:48) > Quoting Paulo Zanoni (2018-05-03 16:24:47) > > Em Qui, 2018-05-03 às 12:59 +0300, Joonas Lahtinen escreveu: > > > Please split the patch here and add a respective Fixes: tag to when > > > base Icelake support was introduced

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Expose RPCS (SSEU) configuration to userspace

Quoting Lionel Landwerlin (2018-04-26 13:22:30) > On 26/04/18 11:00, Joonas Lahtinen wrote: > > Quoting Lionel Landwerlin (2018-04-25 14:45:21) > >> From: Chris Wilson <ch...@chris-wilson.co.uk> > >> > >> We want to allow userspace to reconfigure the s

Re: [Intel-gfx] [PATCH i-g-t] igt/gem_wait: Relax assertion for wait completion

nite timeout afterwards. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> May wanna Cc igt-dev@... Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Regards, Joonas ___ Intel-gfx mailing list Intel-g

Re: [Intel-gfx] [PATCH] drm/i915: Micro-optimise i915_request_retire()

vrtko Ursulin <tvrtko.ursu...@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/icl, x86/gpu: implement ICL stolen memory support

Quoting Paulo Zanoni (2018-05-03 03:23:52) > ICL changes the registers and addresses to 64 bits. > > I also briefly looked at implementing an u64 version of the PCI config > read functions, but I concluded this wouldn't be trivial, so it's not > worth doing it for a single user that can't have

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Mark the hangcheck as idle when unparking the engines

on <ch...@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Regards, joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.fr

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Reset the hangcheck timestamp before repeating a seqno

15 > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Regards, Joonas ___ Intel-gfx mailing lis

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, Just the addition of Geminilake MODULE_FIRMWARE for DMC now when it's in linux-firmware.git. Regards, Joonas drm-intel-fixes-2018-05-02: Add DMC firmware for Geminilake. The following changes since commit 6da6c0db5316275015e8cc2959f12a17584aeb64: Linux v4.17-rc3 (2018-04-29

Re: [Intel-gfx] [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for Geminilake

Quoting Jani Nikula (2018-04-27 12:20:55) > On Wed, 25 Apr 2018, Ian W MORRISON wrote: > > Can I ask if this is on anyone's radar as I'm concerned this patch will > > stall otherwise? > > Pushed to drm-intel-next-queued, thanks for the patch. > > I opted to drop the Cc:

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Expose RPCS (SSEU) configuration to userspace

> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> > c: Dmitry Rogozhkin <dmitry.v.rogozh...@intel.com> > CC: Tvrtko Ursulin <tvrtko.ursu...@intel.com> > CC: Zhipeng Gong <zhipeng.

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, And welcome back! Hope you had a good one. We got a few -rc2 induced 3rd party bugs to CI (but that's nowadays more the rule than an exception), but other than that the results look solid. Main thing are the fixes for the user reported black screen (DP MST) and HDA codec interop issues

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