Min brightness value from vbt was missing for BXT platform.
This setting have to refer backlight ic spec to restrict
min backlight output. Without this restriction, driver would
allow to configure lower brightness value and violate
backlight ic requirement.
Fixes: 0fb890c01349 ("drm/i915/bxt: BLC
From: "Lee, Shawn C" <shawn.c@intel.com>
LFP flicker with latest drm-nightly on customer board. After increase
latency value and this symptom can't be reproduced.
TEST=Reboot DUT and no flicking on LFP.
Cc: Kumar, Mahesh <mahesh1.ku...@intel.com>
Cc: Gary C Wang
From: "Lee, Shawn C" <shawn.c@intel.com>
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status. If PSR exit and link trainign are ongoing at eDP
sink. And eDP source read these registers at the same time.
eDP sink will report EQ &
On 28/04/2017 10:58, Lee, Shawn C wrote:
>> From: "Lee, Shawn C" <shawn.c@intel.com>
>>
>> Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
>> eDP sink status. If PSR exit is ongoing at eDP sink, and eDP source
>> read these
On Fri, Apr 28, 2017 at 03:08:53AM +, Lee, Shawn C wrote:
> > From: "Lee, Shawn C" <shawn.c@intel.com>
> >
> > Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
> > eDP sink status. If PSR exit is ongoing at eDP sink,
From: "Lee, Shawn C" <shawn.c@intel.com>
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status. If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Thursday, April 27, 2017 10:39 PM
To: Lee, Shawn C <shawn.c@intel.com>
Cc: intel-gfx@lists.freedesktop.org; Chiou, Cooper <cooper.ch...@intel.com>;
Bride, Jim <jim.br...@intel.com
From: "Lee, Shawn C" <shawn.c@intel.com>
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status. If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will
From: "Lee, Shawn C" <shawn.c@intel.com>
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status.If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will
From: "Lee, Shawn C" <shawn.c@intel.com>
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status.If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will
From: "Lee, Shawn C" <shawn.c@intel.com>
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status.If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will
From: "Lee, Shawn C" <shawn.c@intel.com>
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status.If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will
From: "Lee, Shawn C" <shawn.c@intel.com>
Add the missing INTEL_OUTPUT_DP_MST case in bxt_get_dpll()
to correctly initialize the crtc_state and port plls when
link training a DP MST monitor on BXT/APL devices.
Fixes: a277ca7dc01d ("drm/i915: Split bxt_ddi_pll_s
From: "Lee, Shawn C" <shawn.c@intel.com>
When user space link status, display driver read DPCD register
0x202, 0x203 and 0x204 to identify sink status. When PSR exit
is ongoing before EQ done. Panel will report EQ & symbol lock
not done. Both of them are under progress
From: "Lee, Shawn C" <shawn.c@intel.com>
Kernel oops was trigger by DP MST monitor/hub connected.
DP MST series patch already upstream and MST should
be support also. MST monitor will display normally with this
change on bxt platform.
Fixes: a277ca7dc01d ("drm/i915: Spl
From: "Lee, Shawn C" <shawn.c@intel.com>
Kernel oops was trigger by DP MST monitor/hub connected.
DP MST series patch already upstream and MST should
be support also. MST monitor will display normally with this
change on bxt platform.
Cc: Jani Nikula <jani.nik...@
Understood. Thanks!
-Original Message-
From: Nikula, Jani
Sent: Monday, September 19, 2016 5:43 PM
To: Lee, Shawn C <shawn.c@intel.com>; intel-gfx@lists.freedesktop.org
Cc: Lee, Shawn C <shawn.c@intel.com>
Subject: Re: [PATCH] drm/i915 : Restore PWM_GRANULARITY
From: "Lee, Shawn C" <shawn.c@intel.com>
SPT_PWM_GRANULARITY (SOUTH_CHICKEN1, bit 0) controls the granularity
(minimum increment) of the PWM backlight control counter. PWM frequency
adjustment on 128 clock increments when this bit was 1. And 16 clock
increments when it was 0
panel->backlight.max = get_backlight_max_vbt(connector);
-Original Message-
From: Nikula, Jani
Sent: Monday, September 19, 2016 4:24 PM
To: intel-gfx@lists.freedesktop.org
Cc: Nikula, Jani <jani.nik...@intel.com>; Lee, Shawn C <shawn.c@intel.com>
Subject: [PA
From: "Lee, Shawn C" <shawn.c@intel.com>
SPT_PWM_GRANULARITY (SOUTH_CHICKEN1, bit 0) controls the granularity
(minimum increment) of the PWM backlight control counter. PWM frequency
adjustment on 128 clock increments when this bit was 1. And 16 clock
increments when it was 0
From: "Lee, Shawn C" <shawn.c@intel.com>
SPT_PWM_GRANULARITY (SOUTH_CHICKEN1, bit 0) controls the granularity
(minimum increment) of the PWM backlight control counter. PWM frequency
adjustment on 128 clock increments when this bit was 1. And 16 clock
increments when it was 0
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