(Chris)
v5: Pass filtering context ID by argument (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 565 +++--
drivers/gpu/drm/i915/i915_perf_types.h | 37 +-
2 files changed, 361 insertions(+), 241 deletions(-)
diff --git a/drivers/gpu/drm
Hi all,
This version pins the configuration context for the lifecycle of the
i915-perf stream.
The associated userspace change :
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4464
Cheers,
Lionel Landwerlin (4):
drm/i915/perf: break OA config buffer object in 2
drm/i915/perf
Chris doesn't like that.
v2: Don't forget to configure the kernel so that periodic reports are
written appropriately (Lionel)
v3: Keep the configuration context pinned for the lifecycle of
i915_perf_stream (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c
On 30/04/2020 17:55, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-30 14:55:35)
@@ -1382,6 +1446,12 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
BUG_ON(stream != perf->exclusive_stream);
+ err = intel_context_pin(stream->config_c
Chris doesn't like that.
v2: Don't forget to configure the kernel so that periodic reports are
written appropriately (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 153 +
drivers/gpu/drm/i915/i915_perf_types.h | 10 +-
2
Hi all,
Just adding Mesa MR links to the patches.
Cheers,
Lionel Landwerlin (4):
drm/i915/perf: break OA config buffer object in 2
drm/i915/perf: stop using the kernel context
drm/i915/perf: prepare driver to receive multiple ctx handles
drm/i915/perf: enable filtering on multiple
XEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
v3: Use a bitfield to select config parts to emit (Umesh)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 177 ---
1 file changed, 114 insertions(+), 63 deleti
(Chris)
v5: Pass filtering context ID by argument (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 584 +++--
drivers/gpu/drm/i915/i915_perf_types.h | 37 +-
2 files changed, 379 insertions(+), 242 deletions(-)
diff --git a/drivers/gpu/drm
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
Link: https://gitlab.freedesktop.org/mesa
On 29/04/2020 18:26, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-29 16:23:34)
On 29/04/2020 18:05, Chris Wilson wrote:
Wait until the GPU is idle before starting a fresh round of probing
gen8-unprivileged-single-ctx-counter. This avoids building up a huge
backlog of render copies
before starting again.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Reviewed-by: Lionel Landwerlin
Thanks,
-Lionel
---
tests/perf.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/tests/perf.c b/tests/perf.c
index 74fc8fd87..7bde46af8
Oh... Is that on a low end platform?
Looks alright :
Reviewed-by: Lionel Landwerlin
Thanks,
-Lionel
On 29/04/2020 17:51, Chris Wilson wrote:
Wait until the GPU is idle before starting a fresh round of probing
gen8-unprivileged-single-ctx-counter. This avoids building up a huge
backlog
XEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
v3: Use a bitfield to select config parts to emit (Umesh)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 177 ---
1 file changed, 114 insertions(+), 63 deleti
Hi all,
Just a small change on the key passed to bsearch().
Cheers,
Lionel Landwerlin (4):
drm/i915/perf: break OA config buffer object in 2
drm/i915/perf: stop using the kernel context
drm/i915/perf: prepare driver to receive multiple ctx handles
drm/i915/perf: enable filtering
(Chris)
v5: Pass filtering context ID by argument (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 594 +++--
drivers/gpu/drm/i915/i915_perf_types.h | 37 +-
2 files changed, 384 insertions(+), 247 deletions(-)
diff --git a/drivers/gpu/drm
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 58
Chris doesn't like that.
v2: Don't forget to configure the kernel so that periodic reports are
written appropriately (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 153 +
drivers/gpu/drm/i915/i915_perf_types.h | 10 +-
2
On 28/04/2020 13:23, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-28 11:08:15)
+static int ctx_id_equal(const void *key, const void *elem)
+{
+ const struct i915_perf_context_detail *details = elem;
+
+ return ((int)details->id) - *((int *)key);
+}
+
+static inline b
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 58
Chris doesn't like that.
v2: Don't forget to configure the kernel so that periodic reports are
written appropriately (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 153 +
drivers/gpu/drm/i915/i915_perf_types.h | 10 +-
2
(Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 594 +++--
drivers/gpu/drm/i915/i915_perf_types.h | 37 +-
2 files changed, 384 insertions(+), 247 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915
Hi all,
A quick fix to configure the kernel context and removing the useless
timeline creation.
Cheers,
Lionel Landwerlin (4):
drm/i915/perf: break OA config buffer object in 2
drm/i915/perf: stop using the kernel context
drm/i915/perf: prepare driver to receive multiple ctx handles
drm
XEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
v3: Use a bitfield to select config parts to emit (Umesh)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 177 ---
1 file changed, 114 insertions(+), 63 deleti
On 28/04/2020 13:19, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-28 11:08:14)
@@ -2837,6 +2851,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
{
struct drm_i915_private *i915 = stream->perf->i915;
struct i915_perf *perf = stream
Make all the internal necessary changes before we flip the switch.
v2: Use an unlimited number of intel contexts (Chris)
v3: Handle GEM context with multiple RCS0 logical contexts (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 553
Chris doesn't like that.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 141 -
drivers/gpu/drm/i915/i915_perf_types.h | 10 +-
2 files changed, 101 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu
use of this feature is now reviewed at :
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4464
Cheers,
Lionel Landwerlin (4):
drm/i915/perf: break OA config buffer object in 2
drm/i915/perf: stop using the kernel context
drm/i915/perf: prepare driver to receive multiple ctx handles
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 58
XEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
v3: Use a bitfield to select config parts to emit (Umesh)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 177 ---
1 file changed, 114 insertions(+), 63 deleti
Makes sense :
Reviewed-by: Lionel Landwerlin
Thanks,
-Lionel
On 24/04/2020 13:19, Chris Wilson wrote:
We want to verify that OA disables rc6 (so that its metrics are not
interrupted by the device sleeping), and once OA is finished, the device
is allowed to sleep again. If rc6 is broken
e anything on i915_request
v4: Fix compilation
[1] :
https://github.com/mikesart/gpuvis/wiki/TechDocs-Intel#gpu-generated-countersevents
Signed-off-by: Lionel Landwerlin
Fixes: 2935ed5339c4 ("drm/i915: Remove logical HW ID")
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
e anything on i915_request
[1] :
https://github.com/mikesart/gpuvis/wiki/TechDocs-Intel#gpu-generated-countersevents
Signed-off-by: Lionel Landwerlin
Fixes: 2935ed5339c4 ("drm/i915: Remove logical HW ID")
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm
m/mikesart/gpuvis/wiki/TechDocs-Intel#gpu-generated-countersevents
Signed-off-by: Lionel Landwerlin
Fixes: 2935ed5339c4 ("drm/i915: Remove logical HW ID")
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 19 +++
: Add OA trigger registers to the pardon list for isolated whitelist (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Umesh Nerlige Ramappa (v1)
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c| 18 ++
drivers/gpu
On 15/04/2020 21:55, Umesh Nerlige Ramappa wrote:
On Wed, Apr 15, 2020 at 01:00:30PM +0300, Lionel Landwerlin wrote:
On 13/04/2020 18:48, Umesh Nerlige Ramappa wrote:
A condition in wait_event_interruptible seems to be checked twice
before
waiting on the event to occur. These checks
On 13/04/2020 18:48, Umesh Nerlige Ramappa wrote:
A condition in wait_event_interruptible seems to be checked twice before
waiting on the event to occur. These checks are redundant when hrtimer
events will call oa_buffer_check_unlocked to update the oa_buffer tail
pointers. The redundant checks
I left some comments below, but I wonder about the values of these tests
compared to Chris' [1].
Much like the tests from Chris it mostly exercises the dma_fence_* API.
On the drm_syncobj API it's just replace_fence(), get_fence(),
add_point() (that last one cannot fail).
-Lionel
[1] :
Make all the internal necessary changes before we flip the switch.
v2: Use an unlimited number of intel contexts (Chris)
v3: Handle GEM context with multiple RCS0 logical contexts (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 553
Chris doesn't like that.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 141 -
drivers/gpu/drm/i915/i915_perf_types.h | 10 +-
2 files changed, 101 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 58
XEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
v3: Use a bitfield to select config parts to emit (Umesh)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 177 ---
1 file changed, 114 insertions(+), 63 deleti
On 14/04/2020 02:34, Umesh Nerlige Ramappa wrote:
- * When set globally, we use a low priority kernel context,
- * so it will effectively take effect when idle.
- */
- ret = emit_oa_config(stream, config, ce,
+ ret = emit_oa_config(stream, config,
+
-filtering? If so, have you considered
disabling context filtering with a parameter instead of actually
filtering for specific contexts? Is this privileged use case?
Thanks,
Umesh
On Thu, Apr 09, 2020 at 12:17:03PM +0300, Lionel Landwerlin wrote:
We want to enable performance monitoring on multiple
can built the HW tag to
process relationship when post processing perf & i915/perf data.
[1] :
https://github.com/mikesart/gpuvis/wiki/TechDocs-Intel#gpu-generated-countersevents
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 16
driver
On 10/04/2020 19:51, Venkata Sandeep Dhanalakota wrote:
From: Lionel Landwerlin
To allow faster engine to engine synchronization, peel the layer of
dma-fence-chain to expose potential i915 fences so that the
i915-request code can emit HW semaphore wait/signal operations in the
ring which
On 03/04/2020 12:12, Chris Wilson wrote:
A few very simple testcases to exercise the dma-fence-chain API.
Signed-off-by: Chris Wilson
---
drivers/dma-buf/Makefile | 3 +-
drivers/dma-buf/selftests.h | 1 +
drivers/dma-buf/st-dma-fence-chain.c | 713
On 09/04/2020 13:52, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-08 21:00:59)
On 03/04/2020 12:12, Chris Wilson wrote:
Whenever we walk along the dma-fence-chain, we prune signaled links to
keep the chain nice and tidy. This leads to situations where we can
prune a link and report
XEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 176 ---
1 file changed, 116 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/dri
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 58
Make all the internal necessary changes before we flip the switch.
v2: Use an unlimited number of intel contexts (Chris)
v3: Handle GEM context with multiple RCS0 logical contexts (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 556
Chris doesn't like that.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 152 +++--
drivers/gpu/drm/i915/i915_perf_types.h | 10 +-
2 files changed, 104 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu
On 03/04/2020 12:12, Chris Wilson wrote:
Whenever we walk along the dma-fence-chain, we prune signaled links to
keep the chain nice and tidy. This leads to situations where we can
prune a link and report the earlier fence as the target seqno --
violating our own consistency checks that the seqno
(Chris)
v9: After explanations on
https://lists.freedesktop.org/archives/dri-devel/2019-August/229287.html
drop the ordering check from v8 (Lionel)
v10: Set first extension enum item to 1 (Jason)
v11: Add wait on previous sync points in timelines (Sandeep)
Signed-off-by: Lionel Landwerlin
up!
Could you point to the changes in v11?
I haven't look at it in a while and I can't remember what you would have
changed.
Thanks a lot,
-Lionel
Signed-off-by: Lionel Landwerlin
Signed-off-by: Venkata Sandeep Dhanalakota
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 312
On 07/04/2020 19:22, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-07 13:35:39)
-static struct intel_context *oa_context(struct i915_perf_stream *stream)
-{
- return stream->pinned_ctx ?: stream->engine->kernel_context;
-}
Idle thought: create a
stream
On 08/04/2020 14:55, Andi Shyti wrote:
Hi Tvrtko,
I start by saying that this patch was mainly sent to kickstart a
discussion about cleanups required in debugfs and how debugfs can
be inconsistent and how much it looks to me that we are relying
on its current state.
The i915_sseu_status is
On 07/04/2020 19:22, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-07 13:35:39)
-static struct intel_context *oa_context(struct i915_perf_stream *stream)
-{
- return stream->pinned_ctx ?: stream->engine->kernel_context;
-}
Idle thought: create a
stream
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 58
XEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 176 ---
1 file changed, 116 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/dri
Make all the internal necessary changes before we flip the switch.
v2: Use an unlimited number of intel contexts (Chris)
v3: Handle GEM context with multiple RCS0 logical contexts (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 591
On 06/04/2020 17:27, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-06 15:07:30)
On 06/04/2020 16:59, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-06 14:54:38)
On 31/03/2020 21:08, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-03-31 12:48:21)
Add 2 new properties
On 06/04/2020 16:59, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-06 14:54:38)
On 31/03/2020 21:08, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-03-31 12:48:21)
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 58
Make all the internal necessary changes before we flip the switch.
v2: Use an unlimited number of intel contexts (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 587 +++--
drivers/gpu/drm/i915/i915_perf_types.h | 23 +-
2 files changed
XEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 176 ---
1 file changed, 116 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/dri
On 31/03/2020 21:08, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-03-31 12:48:21)
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
Hmm. The other thought is ctx->engine[] where one context may have more
t
On 01/04/2020 21:43, Umesh Nerlige Ramappa wrote:
On Tue, Mar 31, 2020 at 02:46:46PM +0300, Lionel Landwerlin wrote:
Gen12 brought an important redesign of the OA unit, splitting it in 2
with a per context part (OAR) and a global part (OAG).
OAR deals with per context counters and implements
On 01/04/2020 10:43, Dixit, Ashutosh wrote:
On Tue, 31 Mar 2020 23:57:57 -0700, Lionel Landwerlin wrote:
On 01/04/2020 02:14, Ashutosh Dixit wrote:
It is wrong to block the user thread in the next poll when OA data is
already available which could not fit in the user buffer provided
interrupt.
v2: Fix ret value for blocking reads (Umesh)
v3: Mistake during patch send (Ashutosh)
v4: Remove -EAGAIN from comment (Umesh)
v5: Improve condition for clearing pollin and return (Lionel)
v6: Improve blocking read loop and other cleanups (Lionel)
Cc: Umesh Nerlige Ramappa
Cc: Lionel
XEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 176 ---
1 file changed, 116 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/dri
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 58
Make all the internal necessary changes before we flip the switch.
v2: Use an unlimited number of intel contexts (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 584 +++--
drivers/gpu/drm/i915/i915_perf_types.h | 23 +-
2 files changed
.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 ++
drivers/gpu/drm/i915/i915_perf.c| 10 +++---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm
interrupt.
v2: Fix ret value for blocking reads (Umesh)
v3: Mistake during patch send (Ashutosh)
v4: Remove -EAGAIN from comment (Umesh)
v5: Improve condition for clearing pollin and return (Lionel)
Cc: Umesh Nerlige Ramappa
Cc: Lionel Landwerlin
Signed-off-by: Ashutosh Dixit
I forgot
is important for us so that we can efficiently schedule
the requests and reprioritise as required.
Reported-by: Lionel Landwerlin
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 154 -
drivers/gpu
On 27/03/2020 12:42, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-03-27 10:32:06)
Hi all,
i915/perf has currently support for single context filtering. This
allows mesa to read the content of the OA buffer and cut out any
unrelated context running in a middle of a query.
Iris currently
On 27/03/2020 12:40, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-03-27 10:32:07)
We want to enable performance monitoring on multiple contexts to cover
the Iris use case of using 2 GEM contexts (3D & compute).
So start by breaking the OA configuration BO which contains global &
Reading or writing those fields should only happen under
stream->oa_buffer.ptr_lock.
Signed-off-by: Lionel Landwerlin
Fixes: d1df41eb72ef ("drm/i915/perf: rework aging tail workaround")
---
drivers/gpu/drm/i915/i915_perf.c | 8 ++--
1 file changed, 6 insertions(+), 2 delet
interrupt.
v2: Fix ret value for blocking reads (Umesh)
v3: Mistake during patch send (Ashutosh)
v4: Remove -EAGAIN from comment (Umesh)
Cc: Umesh Nerlige Ramappa
Cc: Lionel Landwerlin
Signed-off-by: Ashutosh Dixit
Looks like you change makes more sense than what I suggested.
I have a few
Make all the internal necessary changes before we flip the switch.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 493 ++---
drivers/gpu/drm/i915/i915_perf_types.h | 25 +-
2 files changed, 293 insertions(+), 225 deletions(-)
diff --git
Add 2 new properties to the i915-perf open ioctl to specify an arry of
GEM context handles as well as the length of the array.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 51 ++--
include/uapi/drm/i915_drm.h | 21 +
2
ries on the compute context we need to be
able to also filter on the second GEM context used for compute
commands.
This series add support for filtering up to 4 GEM contexts in
i915/perf.
Lionel Landwerlin (3):
drm/i915/perf: break OA config buffer object in 2
drm/i915/perf: prepare driver to rec
XEU register
configurations are per context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 194 ++-
1 file changed, 137 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index
interrupt.
v2: Fix ret value for blocking reads (Umesh)
Cc: Umesh Nerlige Ramappa
Cc: Lionel Landwerlin
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 63 ++--
1 file changed, 12 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm
interrupt.
Looks like you found a pretty important issue.
Can you write an IGT test case so that we don't run into it again?
Thanks a lot,
-Lionel
Cc: Umesh Nerlige Ramappa
Cc: Lionel Landwerlin
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 62
On 16/03/2020 21:23, Dixit, Ashutosh wrote:
On Thu, 12 Mar 2020 16:04:59 -0700, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
We're about to introduce an options to open the perf stream, giving
the user ability to configure how often it wants the kernel to poll
the OA registers
The caller of i915_oa_init_reg_state() already sets this.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_perf.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
v2: Fix selftests by creating an empty config
v3: Fix unlocking on allocation error (Dan Carpenter)
v4: Fixup checkpatch warnings
v5: Fix incorrect unlock in error path (Umesh)
Signed-off-by: Lionel
)
Remove unrelated changes (Tvrtko)
v5: Some typos (Tvrtko)
Process sseu param in read_properties_unlocked() (Tvrtko)
v6: Actually commit the bits from v5...
Fixup some checkpath warnings
v7: Only compare engine uabi field (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
)
Remove unrelated changes (Tvrtko)
v5: Some typos (Tvrtko)
Process sseu param in read_properties_unlocked() (Tvrtko)
v6: Actually commit the bits from v5...
Fixup some checkpath warnings
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem
The caller of i915_oa_init_reg_state() already sets this.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_perf.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
v2: Fix selftests by creating an empty config
v3: Fix unlocking on allocation error (Dan Carpenter)
v4: Fixup checkpatch warnings
v5: Fix incorrect unlock in error path (Umesh)
Signed-off-by: Lionel
On 16/03/2020 20:46, Umesh Nerlige Ramappa wrote:
Looks good. Thanks for cleaning this up.
With s/mutex_lock/mutex_unlock/ below:
Reviewed-by: Umesh Nerlige Ramappa
Thanks,
Umesh
On Sat, Mar 14, 2020 at 12:33:29PM +0200, Lionel Landwerlin wrote:
A little bit of history :
Back when i915
On 17/03/2020 00:16, Dixit, Ashutosh wrote:
On Thu, 12 Mar 2020 16:05:01 -0700, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
The only bit of the status register we currently report in the
i915-perf stream is the "report loss" bit. Only report this when we
have some data
On 16/03/2020 11:16, Tvrtko Ursulin wrote:
On 13/03/2020 14:34, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly
On 15/03/2020 20:08, Francisco Jerez wrote:
Lionel Landwerlin writes:
On 15/03/2020 02:12, Francisco Jerez wrote:
srinivasa...@intel.com writes:
From: Srinivasan S
drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within
kernel
This patch sets improves GPU power
On 15/03/2020 02:12, Francisco Jerez wrote:
srinivasa...@intel.com writes:
From: Srinivasan S
drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within
kernel
This patch sets improves GPU power consumption on Linux kernel based OS such as
Chromium OS, Ubuntu, etc.
On 13/03/2020 17:26, Tvrtko Ursulin wrote:
On 13/03/2020 14:34, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
v2: Fix selftests by creating an empty config
v3: Fix unlocking on allocation error (Dan Carpenter)
v4: Fixup checkpatch warnings
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i91
)
Remove unrelated changes (Tvrtko)
v5: Some typos (Tvrtko)
Process sseu param in read_properties_unlocked() (Tvrtko)
v6: Actually commit the bits from v5...
Fixup some checkpath warnings
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +--
drivers/gpu
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