On Tue, Aug 15, 2023 at 09:53:44AM -0700, Jonathan Cavitt wrote:
> Align igt_spinner_create_request with the hang_create_request
> implementation in selftest_hangcheck.c.
>
> Signed-off-by: Jonathan Cavitt
Reviewed-by: Matt Roper
For the second patch in the series, the gener
check the GT stepping. Finally, the
now-unused IS_DG2_GRAPHICS_STEP macro can be dropped.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +---
drivers/gpu/drm/i915/gt/intel_mocs.c| 21 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 6 +-
drivers/gpu
All production DG2 cards have display stepping C0 or later. We can drop
Wa_14013215631 (only applies to pre-C0) and make Wa_14010547955
unconditional (applies to everything B0 and beyond). Also drop the
now-unused IS_DG2_DISPLAY_STEP macro.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915
The first production SoC steppings for DG2 were C0 (for G10), B1 (for
G11), and A1 (for G12). This corresponds to PCI revision IDs 0x8, 0x5,
and 0x1 respectively. Add this information to the driver's
pre-production detection.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_driver.c
tform first" convention. Code movement only; no
functional change.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 100 +---
1 file changed, 46 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/d
others.
Matt Roper (4):
drm/i915/dg2: Recognize pre-production hardware
drm/i915/dg2: Drop pre-production display workarounds
drm/i915/dg2: Drop pre-production GT workarounds
drm/i915: Tidy workaround definitions
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display
_spinner_create_request(struct igt_spinner *spin,
>
> *batch++ = arbitration_command;
>
> + memset32(batch, MI_NOOP, 128);
> + batch += 128;
> +
> if (GRAPHICS_VER(rq->i915) >= 8)
> *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
which IP is present based on PCI ID
anymore.
Signed-off-by: Matt Roper
Reviewed-by: Nemesa Garg
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_device_info.c | 14 --
drivers/gpu/drm/i915/intel_device_info.h |
two more conditions (one for pg_enable, one for MTL HuC
compatibility).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c
That's truly a
MTL-specific issue rather than being tied to any of the IP blocks, so
leaving the condition as IS_METEORLAKE is correct there.
v2:
- cdclk check should be >=, not >. (Gustavo)
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
.../drm/i915/display/skl_universal_plane.c| 5 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 ++--
drivers/gpu/drm/i915/gt/intel_gt.h| 17 ++
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 7 ++-
drivers/gpu/drm/i915/gt
The currently implemented Xe_LPM+ workarounds are specific to media
version 13.00. When new IP versions show up in the future, they'll need
their own workaround lists.
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2
The workaround bounds for Wa_22011802037 are somewhat complex and are
replicated in several places throughout the code. Pull the condition
out to a helper function to prevent mistakes if this condition needs to
change again in the future.
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
macros on top of existing range check and stepping
check building blocks. (Jani)
- Fix parameters in comment examples.
Cc: Tvrtko Ursulin
Cc: Dnyaneshwar Bhadane
Cc: Gustavo Sousa
Cc: Jani Nikula
Cc: Andi Shyti
Matt Roper (9):
drm/i915: Consolidate condition for Wa_22011802037
dr
Y_IP_RANGE /
IS_DISPLAY_STEP building blocks and make the parameters from/until
instead of begin/fixed. (Jani)
- Fix usage details in comment.
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_device.h | 22 +++
drivers/gpu/drm/i915/display/intel_fbc.c
of IS_MEDIA_GT_IP_RANGE and
IS_MEDIA_STEP building blocks and name the parameters from/until
rather than begin/fixed.. (Jani)
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.h | 30 +
drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +--
drivers/gpu
c: Gustavo Sousa
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Andi Shyti
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.h | 11 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++--
2 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/d
On Mon, Aug 14, 2023 at 08:32:15PM +0530, Shekhar Chauhan wrote:
> Since this Wa is specific to DirectX, this is not required on Linux.
>
> Signed-off-by: Shekhar Chauhan
Reviewed-by: Matt Roper
Too bad the hardware teams didn't do a better job of documenting this so
that we would h
On Fri, Aug 11, 2023 at 10:32:14AM +0300, Jani Nikula wrote:
> On Thu, 10 Aug 2023, Matt Roper wrote:
> > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> > of these workarounds are actually tied to MTL as a platform; they only
> > relate to t
ine_cs *engine,
>
> /* Wa_18019271663 */
> wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> +
> + /* Wa_15010599737 */
> + wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
> }
>
> static void fakewa_disable_nestedb
at the feature flag, and we can simplify the display
code similarly (which will also make it more self-contained for re-use
in the Xe driver).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu
on Xe_HP and beyond, legacy TileY on earlier platforms).
Signed-off-by: Matt Roper
---
.../i915/gem/selftests/i915_gem_client_blt.c | 39 +++
1 file changed, 15 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm
On Thu, Aug 10, 2023 at 03:34:35PM -0700, Matt Roper wrote:
> On Thu, Aug 10, 2023 at 01:36:20PM -0700, Jonathan Cavitt wrote:
> > Align igt_spinner_create_request with the hang_create_request
> > implementation in selftest_hangcheck.c.
> >
> > Signed-off-by: Jonathan C
ped your batch cursor forward 128 dwords (512 bytes).
Matt
> if (GRAPHICS_VER(rq->i915) >= 8)
> *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
> else if (IS_HASWELL(rq->i915))
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
two more conditions (one for pg_enable, one for MTL HuC
compatibility).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c
c: Gustavo Sousa
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Andi Shyti
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.h | 11 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++--
2 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/d
which IP is present based on PCI ID
anymore.
Signed-off-by: Matt Roper
Reviewed-by: Nemesa Garg
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_device_info.c | 14 --
drivers/gpu/drm/i915/intel_device_info.h |
IS_DISPLAY_IP_STEP() that only checks the
display IP version.
v2:
- Rename macro to IS_DISPLAY_IP_STEP for consistency with the
corresponding GT macro and handle steppings the same way.
v3:
- Drop the automatic "STEP_" pasting.
Signed-off-by: Matt Roper
---
.../gpu/drm/i9
The currently implemented Xe_LPM+ workarounds are specific to media
version 13.00. When new IP versions show up in the future, they'll need
their own workaround lists.
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2
That's truly a
MTL-specific issue rather than being tied to any of the IP blocks, so
leaving the condition as IS_METEORLAKE is correct there.
v2:
- cdclk check should be >=, not >. (Gustavo)
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/
The workaround bounds for Wa_22011802037 are somewhat complex and are
replicated in several places throughout the code. Pull the condition
out to a helper function to prevent mistakes if this condition needs to
change again in the future.
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
)
- Move macro to intel_gt.h. (Andi)
Cc: Gustavo Sousa
Cc: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
.../drm/i915/display/skl_universal_plane.c| 5 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 ++--
drivers/gpu/drm/i915/gt/intel_gt.h
of
IS_MEDIA_GT_IP_STEP, which checks the media IP version associated with a
specific IP and also ensures that we're operating on the media GT, not
the primary GT.
v2:
- Switch to the IS_GT_IP_STEP macro.
v3:
- Switch back to long-form IS_MEDIA_GT_IP_STEP. (Jani)
Cc: Jani Nikula
Signed-off-by: Matt Roper
in
Cc: Dnyaneshwar Bhadane
Cc: Gustavo Sousa
Cc: Jani Nikula
Cc: Andi Shyti
Matt Roper (9):
drm/i915: Consolidate condition for Wa_22011802037
drm/i915/xelpmp: Don't assume workarounds extend to future platforms
drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
drm/i915: Eli
ff92307c00(0000)
> knlGS:
> [5.477811] CS: 0010 DS: ES: 0000 CR0: 80050033
> [5.478499] CR2: CR3: 00010256e002 CR4:
> 001706f0
>
> Fixes: 69d439818fe5 ("drm/i915/display: Make display
On Fri, Jul 28, 2023 at 01:39:06PM +0100, Tvrtko Ursulin wrote:
>
> Forgot one part of your reply:
>
> On 28/07/2023 00:57, Matt Roper wrote:
> > On Thu, Jul 27, 2023 at 03:55:00PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > >
On Fri, Jul 28, 2023 at 09:18:36AM +0100, Tvrtko Ursulin wrote:
>
> On 27/07/2023 23:25, Matt Roper wrote:
> > On Thu, Jul 27, 2023 at 03:54:58PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > No need to run extra instruction
On Thu, Jul 27, 2023 at 04:57:53PM -0700, Matt Roper wrote:
> On Thu, Jul 27, 2023 at 03:55:00PM +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Commit 9275277d5324 ("drm/i915: use pat_index instead of cache_level") has
> > introduced PAT ind
ject cache
> mode check.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Fei Yang
> Cc: Matt Roper
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +
> 1 file changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ex
e_needs_clflush().
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Fei Yang
> Cc: Matt Roper
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_
rm.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Fei Yang
> Cc: Matt Roper
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 14 +++---
> 1 file changed, 3 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> b/dri
size. (Matt)
> * Boolean cache mode and flags query. (Matt)
> * Reduce number of cache macros with some macro magic.
> * One more checkpatch fix.
> * Tweak tables to show legacy and Gen12 WB is fully coherent.
>
> Signed-off-by: Tvrtko Ursulin
> References: 9275277d5324 ("
function every time.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Matt Roper
> Cc: Fei Yang
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 3 +--
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 7 ++---
> dr
HICS_VER(gt->i915) >= 12)
> ppgtt->vm.pte_encode = gen12_pte_encode;
I think you wanted 'else if' here. Otherwise you clobber the MTL
function pointer.
Matt
> else
> --
> 2.39.2
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
buffer to a non-coherent domain.
>
> Use the opportunity to documet the situation on discrete too.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Matt Roper
> Cc: Fei Yang
> Cc: Matthew Auld
> Cc: Thomas Hellström
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/
On Thu, Jul 27, 2023 at 03:38:46PM -0300, Lucas De Marchi wrote:
> On Mon, Jul 24, 2023 at 05:13:21PM -0700, Matt Roper wrote:
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>
> for the phy check
it in countertrend... why isn't this
>
> MEDIA_VER_FULL(engine->i915) == IP_VER(13, 0)
>
> Like all others?
Generally we always assume that future platforms will inherit the
behavior of the current platform. The exceptions are things like
workarounds (for which every platf
On Tue, Jul 25, 2023 at 04:52:07PM +0100, Tvrtko Ursulin wrote:
>
> On 25/07/2023 16:35, Matt Roper wrote:
> > On Tue, Jul 25, 2023 at 01:02:54PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 25/07/2023 01:13, Matt Roper wrote:
> > > > Although some of
On Tue, Jul 25, 2023 at 01:10:24PM +0100, Tvrtko Ursulin wrote:
>
> On 25/07/2023 01:13, Matt Roper wrote:
> > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> > of these workarounds are actually tied to MTL as a platform; they only
> > relate t
I would make this a wrapper around IS_GT_IP_STEP() with
> a compile error if we are outside the MTL range.
If we leave this, then someone might try to use it in future patches.
Every single place this macro gets used will always be a driver bug,
which is the motivation for killing it off.
In contast,
On Tue, Jul 25, 2023 at 01:02:54PM +0100, Tvrtko Ursulin wrote:
>
> On 25/07/2023 01:13, Matt Roper wrote:
> > Although some of our Xe_LPG workarounds were already being applied based
> > on IP version correctly, others were matching on MTL as a base platform,
> > which
(gt->i915) < 11)
> > + return false;
> > +
> > + if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
> > + return true;
> > +
> > + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
> > + return false;
> > +
> > + return true;
> > +}
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
That's truly a
MTL-specific issue rather than being tied to any of the IP blocks, so
leaving the condition as IS_METEORLAKE is correct there.
v2:
- cdclk check should be >=, not >. (Gustavo)
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/
The currently implemented Xe_LPM+ workarounds are specific to media
version 13.00. When new IP versions show up in the future, they'll need
their own workaround lists.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2 insertions(+), 2
comment to i915_coherent_map_type() noting that the current
implementation of the workaround is too broad. (Tvrtko)
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 8 ++--
drivers/gpu/drm/i915/gt/intel_engine_pm.c
The workaround bounds for Wa_22011802037 are somewhat complex and are
replicated in several places throughout the code. Pull the condition
out to a helper function to prevent mistakes if this condition needs to
change again in the future.
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
, which checks the media IP version associated with a
specific IP and also ensures that we're operating on the media GT, not
the primary GT.
v2:
- Switch to the IS_GT_IP_STEP macro.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +--
drivers/gpu/drm/i915/i915_drv.h | 4
y
checking for a MTL base platform; that will be remedied in a later
patch.
v2:
- Rework macro into a slightly more generic IS_GT_IP_RANGE() that can
be used for either GFX or MEDIA checks.
Cc: Gustavo Sousa
Cc: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_wor
graphics workarounds to the Xe_LPM+
media GT and vice-versa.
v2:
- Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
used for both graphics and media IP (and any other kind of GTs that
show up in the future).
Cc: Gustavo Sousa
Cc: Tvrtko Ursulin
Signed-off-by: Matt Roper
which IP is present based on PCI ID
anymore.
Signed-off-by: Matt Roper
Reviewed-by: Nemesa Garg
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_device_info.c | 14 --
drivers/gpu/drm/i915/intel_device_info.h |
IS_DISPLAY_IP_STEP() that only checks the
display IP version.
v2:
- Rename macro to IS_DISPLAY_IP_STEP for consistency with the
corresponding GT macro and handle steppings the same way.
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_display_device.h | 17
ustavo)
- Extra documentation comments
Cc: Tvrtko Ursulin
Cc: Dnyaneshwar Bhadane
Cc: Gustavo Sousa
Matt Roper (9):
drm/i915: Consolidate condition for Wa_22011802037
drm/i915/xelpmp: Don't assume workarounds extend to future platforms
drm/i915/xelpg: Call Xe_LPG workaround functions based
On Thu, Jul 20, 2023 at 03:10:21PM +0200, Andrzej Hajda wrote:
> On 20.07.2023 11:36, Tvrtko Ursulin wrote:
> >
> > On 19/07/2023 23:54, Matt Roper wrote:
> > > On Wed, Jul 19, 2023 at 08:28:12AM -0700, Matt Roper wrote:
> > > > On Wed, Jul 19, 2023 at 09
e for all
> engines")
> Signed-off-by: Andi Shyti
> Cc: Jonathan Cavitt
> Cc: Nirmoy Das
> Cc: # v5.8+
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> 2 files ch
ing a
> boolean gen12_needs_ccs_aux_inv() function that tells whether aux
> invalidation is needed or not.
>
> Currently PVC is the only exception to the above mentioned rule.
>
> Signed-off-by: Andi Shyti
> Cc: Matt Roper
> Cc: Jonathan Cavitt
> Cc: # v5.8+
Reviewed
_GTT_RELOC)
> >>>>> return false;
> >>>>>
> >>>>> -/*
> >>>>> - * For objects created by userspace through GEM_CREATE with
> >>>>> pat_index
> >>>>> - * set by set_pat extension, i915_gem_object_has_cache_level()
> >>>>> always
> >>>>> - * return true, otherwise the call would fall back to checking
> >>>>> whether
> >>>>> - * the object is un-cached.
> >>>>> - */
> >>>>> return (cache->has_llc ||
> >>>>> obj->cache_dirty ||
> >>>>> -!i915_gem_object_has_cache_level(obj, I915_CACHE_NONE));
> >>>>> +i915_gem_object_has_cache_mode(obj,
> >>>>> + I915_CACHE_MODE_UC) != 1);
> >>>>
> >>>> Platforms with relocations and platforms with user-specified PAT
> >>>> have no overlap, right? So a -1 return should be impossible here
> >>>> and this is one case where we could just treat the return value as
> >>>> a boolean, right?
> >>>
> >
> > Hm no, or maybe. My thinking behind tri-state is to allow a safe option
> > for "don't know". In case PAT index to cache mode table is not fully
> > populated on some future platform.
>
> That would be a problem in the cache mode table. At least max_pat_index
> should have guaranteed the PAT index is sane.
>
> -Fei
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
/i915/gt/intel_gpu_commands.h
> @@ -299,6 +299,7 @@
> #define PIPE_CONTROL_QW_WRITE (1<<14)
> #define PIPE_CONTROL_POST_SYNC_OP_MASK(3<<14)
> #define PIPE_CONTROL_DEPTH_STALL (1<<13)
> +#define PIPE_C
urn PTR_ERR(cs);
> -
> - cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1,
> - LRC_PPHWSP_SCRATCH_ADDR);
> - intel_ring_advance(rq, cs);
> + intel_emit_pipe_control_cs(rq, bit_group_0, bit_group_1,
> +LRC_PPHWSP_SCRATCH_ADDR);
> }
>
> if (mode & EMIT_INVALIDATE) {
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
want to stick with the flag it's
probably best to rename it slightly so that it more accurately reflects
what we're using it for.
Matt
>
> Signed-off-by: Andi Shyti
> Cc: Matt Roper
> Cc: Jonathan Cavitt
> Cc: # v5.8+
> ---
> drivers/gpu/drm/i915/gt/gen8_engine
f being removed.
These lines got replaced with a check for the specific PAT indices that
are problematic rather than just assuming any user-provided PAT might
cause problems. But I had some concerns about the specific logic there
in my review as well.
Matt
>
> >> /*
> >> * EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
> >> * possible for userspace to bypass the GTT caching bits set by the
> >> @@ -226,7 +242,21 @@ bool i915_gem_object_can_bypass_llc(struct
> >> drm_i915_gem_object *obj)
> >> * it, but since i915 takes the stance of always zeroing memory before
> >> * handing it to userspace, we need to prevent this.
> >> */
> >> -return IS_JSL_EHL(i915);
> >> +if (IS_JSL_EHL(i915))
> >> +return true;
> >> +
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
On Wed, Jul 19, 2023 at 08:28:12AM -0700, Matt Roper wrote:
> On Wed, Jul 19, 2023 at 09:01:58AM +0100, Tvrtko Ursulin wrote:
> >
> > On 18/07/2023 23:27, Matt Roper wrote:
> > > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> > > of th
ss_llc() (Matt)
>
> v3:
> * Checkpath issues.
> * Cache mode flags check fixed.
>
> Signed-off-by: Tvrtko Ursulin
> Fixes: 9275277d5324 ("drm/i915: use pat_index instead of cache_level")
> Cc: Chris Wilson
> Cc: Fei Yang
> Cc: Andi Shyti
On Wed, Jul 19, 2023 at 09:01:58AM +0100, Tvrtko Ursulin wrote:
>
> On 18/07/2023 23:27, Matt Roper wrote:
> > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> > of these workarounds are actually tied to MTL as a platform; they only
> > relate t
On Wed, Jul 19, 2023 at 08:57:15AM +0100, Tvrtko Ursulin wrote:
>
> On 18/07/2023 23:28, Matt Roper wrote:
> > Many of the IS_METEORLAKE conditions throughout the driver are supposed
> > to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
> > specifical
a MTL base platform; that will be remedied in a later
patch.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++--
drivers/gpu/drm/i915/i915_drv.h | 5 +++
2 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/d
IS_DISPLAY_IPVER_STEP() that only checks the
display IP version.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_device.h | 5 +
drivers/gpu/drm/i915/display/intel_fbc.c| 3 ++-
drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
drivers/gpu/drm
That's truly a
MTL-specific issue rather than being tied to any of the IP blocks, so
leaving the condition as IS_METEORLAKE is correct there.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
drivers/gpu/drm
which IP is present based on PCI ID
anymore.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_device_info.c | 14 --
drivers/gpu/drm/i915/intel_device_info.h | 4
include/drm/i915_pciids.h| 11 +++-
-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c| 4 ++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915
The workaround bounds for Wa_22011802037 are somewhat complex and are
replicated in several places throughout the code. Pull the condition
out to a helper function to prevent mistakes if this condition needs to
change again in the future.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt
graphics workarounds to the
Xe_LPM+ media GT.
Signed-off-by: Matt Roper
---
.../drm/i915/display/skl_universal_plane.c| 4 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 9 ++--
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4
ind a use for this macro on earlier platforms.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +--
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_perf.c| 15 ---
3 files changed, 11 insertions(+), 17 deletions(-)
diff --
: Dnyaneshwar Bhadane
Matt Roper (8):
drm/i915: Consolidate condition for Wa_22011802037
drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
drm/i915: Eliminate IS_MTL_MEDIA_STEP
drm/i915: Eliminate IS_MTL_DISPLAY_STEP
drm/i915/mtl
> > if (engine->class == COMPUTE_CLASS)
> > - if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > + if ((IS_METEORLAKE_M(engine->i915) &&
> > + IS_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0)) ||
>
> + if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> + struct intel_gt *gt;
> + int i;
> +
> + for_each_gt(gt, i915, i) {
> + if (gt->type == GT_MEDIA &&
> + intel_check_bios_c6_setup(>rc6))
> + return 6;
> + }
> + }
> +
> return 7;
> }
>
> --
> 2.36.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
>
> But isn't it the same the patch you linked is doing?
>
> return !xe->info.has_flat_ccs;
No, that's just the end of the function. The important
platform-specific checks come before that point (at the moment we only
have PVC, but we expect more platforms to be added there very soon too).
Matt
>
> And
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
On Mon, Jul 17, 2023 at 11:52:25PM +0200, Andi Shyti wrote:
> Hi Matt,
>
> On Mon, Jul 17, 2023 at 01:31:03PM -0700, Matt Roper wrote:
> > On Mon, Jul 17, 2023 at 10:54:37AM -0700, Matt Roper wrote:
> > > On Mon, Jul 17, 2023 at 07:30:55PM +0200, Andi Shyti wrote:
>
On Mon, Jul 17, 2023 at 10:54:37AM -0700, Matt Roper wrote:
> On Mon, Jul 17, 2023 at 07:30:55PM +0200, Andi Shyti wrote:
> > From: Jonathan Cavitt
> >
> > All memory traffic must be quiesced before requesting
> > an aux invalidation on platforms that use Aux CCS.
&
6014892111 */
> if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> @@ -1399,17 +1396,7 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context
> *ce, u32 *cs)
>
> PIPE_CONTROL_INSTRUCTION_CACHE_INVA
arlier patch, we should probably make this check that
the platform actually has AuxCCS.
Anyway, up to you whether you want to make that change or not. The
extra noops don't actually hurt anything.
Reviewed-by: Matt Roper
> - count = 8 + 4;
> - else
> -
ssion on pre-gen8 platforms.
Anyway, adding the extra condition shouldn't really hurt anything
either, so up to you whether you want to drop it or not.
Reviewed-by: Matt Roper
>
> if (mode & EMIT_FLUSH) {
> u32 bit_group_0 = 0;
> @@ -221,6 +221,14 @@ int g
On Mon, Jul 17, 2023 at 07:30:56PM +0200, Andi Shyti wrote:
> In preparation of the next patch allign with the datasheet (BSPEC
s/allign/align/
Otherwise,
Reviewed-by: Matt Roper
> 47112) with the naming of the pipe control set of flag values.
> The variable "flags" in g
op.org/patch/539304/?series=118334=1
Matt
> + mode |= EMIT_FLUSH;
> +
> if (mode & EMIT_FLUSH) {
> u32 flags = 0;
> int err;
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
en we probably should apply the blanket IS_METEORLAKE condition.
> > >
> > > Signed-off-by: Tvrtko Ursulin
> > > Fixes: 9275277d5324 ("drm/i915: use pat_index instead of cache_level")
> > > Cc: Chris Wilson
> > > Cc: Fei Yang
> > > Cc: An
ow ones. The
bottom 12 are guaranteed to be 0's (due to page alignment), so the
hardware doesn't need to know about them.
Also CTX_WA_PTR is a context register, but you're only programming it a
single time per engine in engine_init_workarounds. You need this to be
part of the golden context
that, move the programming of
> GEN12_FF_MODE2 to a single place so the value passed for "clear" can
> be all the bits. Otherwise the second workaround would be dropped as
> it'd be detected as overwriting a previously programmed workaround.
>
> Signed-off-by: Lucas De Mar
On Thu, Jun 22, 2023 at 04:24:49PM +0530, Kalvala, Haridhar wrote:
>
> On 6/17/2023 4:20 AM, Matt Roper wrote:
> > This workaround was already implemented for DG2, PVC, and some steppings
> > of MTL, but the workaround database has now been updated to extend this
> > wor
mming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With
> > > >> the GPU idle, that register could be read via intel_reg as 0x00e001ff,
> > > >> but during a 3D workload it would change to 0x007f. So the
> > > >> programming of that tuning was affecting more than the bits in
> > &
engine_cs
> > *engine)
> > /* Wa_14014475959:dg2 */
> > if (engine->class == COMPUTE_CLASS)
> > - if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > + if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> > STEP_B0) ||
> > IS_DG2(engine->i915))
> > engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index ef828e7de2ec..c6ad78381dd1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -688,15 +688,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> > (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> > -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> > +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
> > (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant)
> > && \
> > IS_GRAPHICS_STEP(__i915, since, until))
> > -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> > +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
> > (IS_METEORLAKE(__i915) && \
> > IS_DISPLAY_STEP(__i915, since, until))
> > -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
> > +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
> > (IS_METEORLAKE(__i915) && \
> > IS_MEDIA_STEP(__i915, since, until))
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c
> > b/drivers/gpu/drm/i915/i915_perf.c
> > index 0a111b281578..e943ffbaecbc 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf
> > *perf,
> > * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where
> > OAM
> > * does not work as expected.
> > */
> > - if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> > + if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> > props->engine->oa_group->type == TYPE_OAM &&
> > intel_check_bios_c6_setup(>engine->gt->rc6)) {
> > drm_dbg(>i915->drm,
> > @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private
> > *i915)
> > * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
> > * to indicate that OA media is not supported.
> > */
> > - if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> > + if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> > struct intel_gt *gt;
> > int i;
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
locks this register, preventing
the driver from making any modifications. We should still try to
apply the workaround, but if the register is locked and the value
doesn't stick, that's semi-expected and not something we want to flag
as a driver error on debug builds.
Signed-off-by: Matt
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