https://gitlab.freedesktop.org/drm/intel/issues/6230
> [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
> [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
> [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
> [i915#6252]: https://gitlab.freedeskto
/intel/issues/6367
> [i915#6712]: https://gitlab.freedesktop.org/drm/intel/issues/6712
> [i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
> [i915#7122]: https://gitlab.freedesktop.org/drm/intel/issues/7122
> [i915#7270]: https://gitlab.freedesktop.org/drm/intel/issues/7270
>
>
> Build changes
> -
>
> * Linux: CI_DRM_12261 -> Patchwork_109912v1
>
> CI-20190529: 20190529
> CI_DRM_12261: 41447224fdfbfbfd1e9ffa5fabc9d277f9c02f8a @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_7019: fdbafce2b74e84739bb1d81223ae6f01fb442980 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_109912v1: 41447224fdfbfbfd1e9ffa5fabc9d277f9c02f8a @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> 48b2a60b18d8 drm/i915/xelpg: Fix write to MTL_MCR_SELECTOR
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109912v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
A misplaced closing parenthesis caused the groupid/instanceid values to
be considered part of the ternary operator's condition instead of being
OR'd into the resulting value.
Fixes: f32898c94a10 ("drm/i915/xelpg: Add multicast steering")
Reported-by: kernel test robot
Signed-off-by:
he older TGL-ADL gfx IP name. MTL's media IP is called
Xe_LPM+ (which we should label as XELPMP in code, so it looks like the
final "P" is missing here).
Matt
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
59
> [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
> [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
> [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
> [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
> [i915#6344]: https://
On Mon, Oct 17, 2022 at 10:55:25AM +0200, Andrzej Hajda wrote:
> GEN7_DOP_CLOCK_GATE_ENABLE bit should be cleared, not inverse.
> The bug was introduced during conversion to intel_uncore_rmw helper.
>
> Suggested-by: Matt Roper
> Fixes: 8cee664d3eb6f8 ("drm/i915: use proper
On Mon, Oct 17, 2022 at 09:17:51AM -0700, Matt Roper wrote:
> On Sat, Oct 15, 2022 at 01:03:31AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: Explicit MCR handling and MTL steering (rev4)
> > URL : https://patchwork.freedesktop.org/series/
6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
> [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
> [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
> [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463
> [i915#6493]: https://gitlab.freedesktop.org/dr
, we keep the
> interrupts always enabled in HW and use a variable in the GuC structure
> to determine if we want to service the received interrupts or not.
>
> v2: use MTL_ prefix for reg definition (Matt)
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Matt Roper
> Cc: John Harri
The bspec was just updated with a correction to the forcewake domain
required when accessing registers in the CCS engine ranges (0x1a000 -
0x1 and 0x26000 - 0x27fff) on PVC; these ranges require a wake on
the RENDER domain, not the GT domain.
Bspec: 67609
Signed-off-by: Matt Roper
that handles this on MCR registers, similar to the
__intel_wait_for_register_fw() function we already have for regular
registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 55 ++
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 7
2 files changed, 62
us an alternate interface to do unicast per-instance
save/restore operations, so we should be very clear about which
registers on the list are MCR registers (and in the future which
save/restore behavior we want for them).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
to "XEHP_" to help clarify that we're using the
newer multicast form of the register.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +-
2 files changed, 9 insertions(+), 9 deletions(-)
for Xe_HP. (Bala)
Cc: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 58 ---
drivers/gpu/drm/i915/gt/intel_mocs.c | 13 ++---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 12 +++--
drivers/gpu/drm/i915/intel_pm.c
that in future patches.
Bspec: 66673, 66696, 66534, 67609
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 134
1 file changed, 68 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt
ion of HALF_SLICE_CHICKEN3 in GVT's gen9 engine MMIO
list. (Bala)
- Update to the gen8 version of MISCCPCTL in a couple new workarounds
that were recently added for DG2/PVC. (Bala)
Signed-off-by: Matt Roper
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/gt/intel_engine_c
Let's be more explicit about which of our workarounds are updating MCR
registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 433 +++---
.../gpu/drm/i915/gt/intel_workarounds_types.h | 4 +-
2 files changed, 263 insertions(+), 174 deletions
need only make changes to structures that have an
explicit i915_reg_t in them now.
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 16 --
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 51 ---
drivers/gpu/drm/i915/gt/inte
ally
steer to the primary GAM) is sufficient; we don't need to loop over each
instance of the MCR register.
v2:
- Update more instances of fault registers. (Bala)
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 52 +++
drivers/gpu/drm/i915/i915_gpu_er
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_ggtt.c| 4 ++--
drivers/gpu/drm/i915/gt/intel_gt.c | 18 --
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 26 +++--
drivers/gpu/drm/i915/gt/intel_gtt.c | 22
t writes just to be safe. (Bala)
Bspec: 67788, 67112
Cc: Radhakrishna Sripada
Cc: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 135 +---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/gt/inte
open-code this.
v2:
- Return a u32 to align with the recent change to intel_uncore_rmw.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 28 ++
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 3 +++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/d
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper
---
drivers
MTL's media IP (Xe_LPM+) only has a single type of steering ("OAADDRM")
which selects between media slice 0 and media slice 1. We'll always
steer to media slice 0 unless it is fused off (which is the case when
VD0, VE0, and SFC0 are all reported as unavailable).
Bspec: 67789
Signed-of
On Fri, Oct 14, 2022 at 09:32:55PM +0530, Balasubramani Vivekanandan wrote:
> On 30.09.2022 17:45, Matt Roper wrote:
> > MTL once again changes the multicast register types and steering
> > details. Key changes from past platforms:
> > * The number of instances of some M
cpt_init_clock_gating(dev_priv);
> diff --git a/drivers/gpu/drm/i915/vlv_suspend.c
> b/drivers/gpu/drm/i915/vlv_suspend.c
> index 664fde244f59b0..02e63ed77f608d 100644
> --- a/drivers/gpu/drm/i915/vlv_suspend.c
> +++ b/drivers/gpu/drm/i915/vlv_suspend.c
> @@ -194,7 +194,6 @@ static void vlv_restore_gunit_s0ix_state(struct
> drm_i915_private *i915)
> {
> struct vlv_s0ix_state *s = i915->vlv_s0ix_state;
> struct intel_uncore *uncore = >uncore;
> - u32 val;
> int i;
>
> if (!s)
> @@ -262,15 +261,11 @@ static void vlv_restore_gunit_s0ix_state(struct
> drm_i915_private *i915)
>* be restored, as they are used to control the s0ix suspend/resume
>* sequence by the caller.
>*/
> - val = intel_uncore_read(uncore, VLV_GTLC_WAKE_CTRL);
> - val &= VLV_GTLC_ALLOWWAKEREQ;
> - val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
> - intel_uncore_write(uncore, VLV_GTLC_WAKE_CTRL, val);
> + intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, ~VLV_GTLC_ALLOWWAKEREQ,
> + s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ);
>
> - val = intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG);
> - val &= VLV_GFX_CLK_FORCE_ON_BIT;
> - val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
> - intel_uncore_write(uncore, VLV_GTLC_SURVIVABILITY_REG, val);
> + intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG,
> ~VLV_GFX_CLK_FORCE_ON_BIT,
> + s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT);
>
> intel_uncore_write(uncore, VLV_PMWGICZ, s->pmwgicz);
>
> @@ -308,14 +303,10 @@ static int vlv_wait_for_pw_status(struct
> drm_i915_private *i915,
> static int vlv_force_gfx_clock(struct drm_i915_private *i915, bool force_on)
> {
> struct intel_uncore *uncore = >uncore;
> - u32 val;
> int err;
>
> - val = intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG);
> - val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
> - if (force_on)
> - val |= VLV_GFX_CLK_FORCE_ON_BIT;
> - intel_uncore_write(uncore, VLV_GTLC_SURVIVABILITY_REG, val);
> + intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG,
> VLV_GFX_CLK_FORCE_ON_BIT,
> + force_on ? VLV_GFX_CLK_FORCE_ON_BIT : 0);
>
> if (!force_on)
> return 0;
> @@ -340,11 +331,8 @@ static int vlv_allow_gt_wake(struct drm_i915_private
> *i915, bool allow)
> u32 val;
> int err;
>
> - val = intel_uncore_read(uncore, VLV_GTLC_WAKE_CTRL);
> - val &= ~VLV_GTLC_ALLOWWAKEREQ;
> - if (allow)
> - val |= VLV_GTLC_ALLOWWAKEREQ;
> - intel_uncore_write(uncore, VLV_GTLC_WAKE_CTRL, val);
> + intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ,
> + allow ? VLV_GTLC_ALLOWWAKEREQ : 0);
> intel_uncore_posting_read(uncore, VLV_GTLC_WAKE_CTRL);
>
> mask = VLV_GTLC_ALLOWWAKEACK;
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Tue, Oct 04, 2022 at 04:00:57PM +0300, Jani Nikula wrote:
> On Tue, 04 Oct 2022, Jani Nikula wrote:
> > On Fri, 30 Sep 2022, Matt Roper wrote:
> >> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> >> b/drivers/gpu/drm/i915/i915_reg_defs.h
> >> ind
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
> [i915#5235]: https://gitlab.fr
On Mon, Oct 03, 2022 at 09:56:18AM +0100, Tvrtko Ursulin wrote:
>
> Hi Matt,
>
> On 01/10/2022 01:45, Matt Roper wrote:
> > MTL's media GT only has a single type of steering ("OAADDRM") which
> > selects between media slice 0 and media slice 1. We'll always
that in future patches.
Bspec: 66673, 66696, 66534, 67609
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 134
1 file changed, 68 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt
us an alternate interface to do unicast per-instance
save/restore operations, so we should be very clear about which
registers on the list are MCR registers (and in the future which
save/restore behavior we want for them).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
nt to look for better ways to store mixed collections of i915_reg_t
and i915_mcr_reg_t in the future.
v2:
- Add TLB invalidation registers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 32 +++
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 53 --
open-code this.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 24
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 3 +++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index a2
r will be introduced in a future patch.
Bspec: 67788, 67112
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 85 ++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h| 8 +-
dri
Rather than relying on the implicit behavior of intel_uncore_*()
functions, let's always use the intel_gt_mcr_*() functions to operate on
multicast/replicated registers.
v2:
- Add TLB invalidation registers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 42
that handles this on MCR registers, similar to the
__intel_wait_for_register_fw() function we already have for regular
registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 55 ++
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 7
2 files changed, 62
ally
steer to the primary GAM) is sufficient; we don't need to loop over each
instance of the MCR register.
v2:
- Update more instances of fault registers. (Bala)
Cc: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 52 +++
drive
Let's be more explicit about which of our workarounds are updating MCR
registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 428 +++---
.../gpu/drm/i915/gt/intel_workarounds_types.h | 4 +-
2 files changed, 261 insertions(+), 171 deletions
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper
---
drivers
to "XEHP_" to help clarify that we're using the
newer multicast form of the register.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +-
2 files changed, 9 insertions(+), 9 deletions(-)
MTL's media GT only has a single type of steering ("OAADDRM") which
selects between media slice 0 and media slice 1. We'll always steer to
media slice 0 unless it is fused off (which is the case when VD0, VE0,
and SFC0 are all reported as unavailable).
Bspec: 67789
Signed-off-by:
ion of HALF_SLICE_CHICKEN3 in GVT's gen9 engine MMIO
list. (Bala)
- Update to the gen8 version of MISCCPCTL in a couple new workarounds
that were recently added for DG2/PVC. (Bala)
Cc: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
Reviewed-by: Balasubramani Vivekanandan
---
drivers/
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_ggtt.c| 4 ++--
drivers/gpu/drm/i915/gt/intel_gt.c | 18 --
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 26 +++--
drivers/gpu/drm/i915/gt/intel_gtt.c | 22
registers over to MCR handling where appropriate. (Bala)
Matt Roper (14):
drm/i915/gen8: Create separate reg definitions for new MCR registers
drm/i915/xehp: Create separate reg definitions for new MCR registers
drm/i915/gt: Drop a few unused register definitions
drm/i915/gt: Corr
On Wed, Sep 28, 2022 at 03:20:52PM +0530, Balasubramani Vivekanandan wrote:
> On 19.09.2022 15:32, Matt Roper wrote:
> > Starting in Xe_HP, several registers our driver works with have been
> > converted from singleton registers into replicated registers with
> > multicas
tlab.freedesktop.org/drm/intel/issues/3297
> [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
> [i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
> [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
> [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
> [i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
> [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
> [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
> [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
> [i915#6403]: https://gitlab.freedesktop.org/drm/intel/issues/6403
> [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#6987]: https://gitlab.freedesktop.org/drm/intel/issues/6987
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>
>
> Build changes
> -
>
> * Linux: CI_DRM_12199 -> Patchwork_109066v5
>
> CI-20190529: 20190529
> CI_DRM_12199: 6fa6bc62d3b91e5a70b8e4869436a0b03083abf5 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6669: 3d2df081c14c251e0269e3510ddc4e9d26ffe925 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_109066v5: 6fa6bc62d3b91e5a70b8e4869436a0b03083abf5 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109066v5/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Thu, Sep 29, 2022 at 10:09:03PM -0700, Lucas De Marchi wrote:
> Different handling for XeHP and later platforms should be using the
> xehp prefix, not gen125. Rename them.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/gen8_eng
On Thu, Sep 29, 2022 at 10:09:02PM -0700, Lucas De Marchi wrote:
> It's no obviously clear how the encode/decode of the per platform tables
This should probably say "...not obvious..." or "...not clear..."
Otherwise,
Reviewed-by: Matt Roper
> is done. Document
> ones there's a mismatch causing the jump to
> `wa_offset + DG2_PREDICATE_RESULT_BB` to be invalid since wa_offset is
> not correct.
>
> As in other places in the driver, check for graphics version "greater or
> equal" to future-proof the support for new platforms.
&g
2. replace the calculations with SZ_256M/SZ_8M
>
> v5: Include more details to commit message on how it is different from
> earlier platforms (Anshuman)
>
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: Jani Nikula
>
> Signed-off-by: CQ Tang
> Signed-off-by:
On Tue, Sep 27, 2022 at 05:22:41PM -0700, Ceraolo Spurio, Daniele wrote:
>
>
> On 9/27/2022 5:10 PM, Matt Roper wrote:
> > On Thu, Sep 22, 2022 at 03:11:17PM -0700, Daniele Ceraolo Spurio wrote:
> > > The render and media GuCs share the same interrupt enable register, s
red to the host for that specific GuC)?
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Matt Roper
> Cc: John Harrison
> Cc: Alan Previn
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 21 ++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> dr
valid_stolen_size check from Lucas
> (Jani, Lucas)
> 2. drop lmembar_is_igpu_stolen
> 3. revert to referring GFXMEM_BAR as GEN12_LMEM_BAR (Lucas)
>
> v3:(Jani)
> 1. rename get_mtl_gms_size to mtl_get_gms_size
> 2. define register for MMIO address
>
> Cc: Matt Roper
&g
ktop.org/drm/intel/issues/3689
> [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
> [i915#4338]: https://gitlab.freedesktop.org/drm/intel/issues/4338
> [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
> [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
> [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
> [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
> [i915#6375]: https://gitlab.freedesktop.org/drm/intel/issues/6375
> [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
> [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
> [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>
>
> Build changes
> -
>
> * Linux: CI_DRM_12169 -> Patchwork_108928v1
>
> CI-20190529: 20190529
> CI_DRM_12169: 5d9b8ac449d01e7d8c9253e1c939b5f3ca216f47 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6662: dcb1d7a8822e62935f4fe3f2e6a04caaee669369 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_108928v1: 5d9b8ac449d01e7d8c9253e1c939b5f3ca216f47 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108928v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Fri, Sep 23, 2022 at 03:48:51PM -0700, Lucas De Marchi wrote:
> On Thu, Sep 15, 2022 at 06:46:48PM -0700, Radhakrishna Sripada wrote:
> > From: Matt Roper
> >
> > The part of the media and blitter engine contexts that we care about for
> > setting up an initia
eedesktop.org/drm/intel/issues/6095
> [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
> [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
> [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
> [i915#6248]: https://gitlab.freed
nit function.
>
> bspec:54077
>
> Signed-off-by: Matt Atwood
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 ---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_wor
eedesktop.org/drm/intel/issues/6474
> [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
> [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
> [i915#6772]: https://gitlab.freedesktop.org/drm/intel/issues/6772
>
>
> Build changes
> -
>
> * Linux: CI_DRM_12144 -> Patchwork_108627v1
>
> CI-20190529: 20190529
> CI_DRM_12144: 55937d402fd885fe101cdd028dcc48df6d7f6b35 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_108627v1: 55937d402fd885fe101cdd028dcc48df6d7f6b35 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108627v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Wed, Sep 21, 2022 at 12:58:08PM -0400, Kumar Valsan, Prathap wrote:
> On Fri, Sep 16, 2022 at 07:53:40AM -0700, Matt Roper wrote:
> > On Fri, Sep 16, 2022 at 10:02:32AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 16/09/2022 02:43, Matt Roper wrote:
> > > >
el/issues/4386
> [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
> [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
> [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
> [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
> [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
> [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
> [i915#6864]: https://gitlab.freedesktop.org/drm/intel/issues/6864
>
>
> Build changes
> -
>
> * Linux: CI_DRM_12158 -> Patchwork_108755v1
>
> CI-20190529: 20190529
> CI_DRM_12158: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_108755v1: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
super common, but I think it
should be okay to use. I believe clang supports this language extension
as well and the coding style doc doesn't say anything one way or the
other.
Matt
>
> Andi
>
> > + return (gms - 0xf0 + 1) * 4;
> > + default:
> > + return -EIO;
> > + }
> > +}
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
ting towards the reason why
> the reset was hanging; and allow more marginal cases the extra headroom
> to complete the reset without further collateral damage.
>
> Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/6448
> Signed-off-by: Chris Wilson
Seems reasonable.
Reviewed-by: Mat
On Mon, Sep 19, 2022 at 03:46:47PM -0700, Matt Roper wrote:
> On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> > Updated the CAGF functions to get actual resolved frequency of
> > 3D and SAMedia
> >
> > Bspec: 66300
> >
> > Cc: Vinay Belgaum
f (GRAPHICS_VER(i915) >= 6) {
> + } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> + freq = intel_uncore_read(rps_to_gt(rps)->uncore,
> MTL_MIRROR_TARGET_WP1);
Same here.
Matt
> + else if (GRAPHICS_VER(i915) >= 6) {
> freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
> } else {
> freq = intel_uncore_read(uncore, MEMSTAT_ILK);
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Let's be more explicit about which of our workarounds are updating MCR
registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 424 +++---
.../gpu/drm/i915/gt/intel_workarounds_types.h | 4 +-
2 files changed, 259 insertions(+), 169 deletions
)
* SLICE_UNIT_LEVEL_CLKGATE (gslice replication)
* LNCFCMOCS (lncf replication)
Bspec: 66534
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 -
drivers/gpu/drm/i915/gt/intel_gtt.c | 29 ++---
drivers/gpu/drm/i915/gt/intel_mocs.c
Rather than relying on the implicit behavior of intel_uncore_*()
functions, let's always use the intel_gt_mcr_*() functions to operate on
multicast/replicated registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gtt.c
nt to look for better ways to store mixed collections of i915_reg_t
and i915_mcr_reg_t in the future.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 49 ---
drivers/gpu/drm/i915/gt/intel_gt_mcr.h| 14 +++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h
r will be introduced in a future patch.
Bspec: 67788, 67112
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 85 ++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h| 8 +-
dri
us an alternate interface to do unicast per-instance
save/restore operations, so we should be very clear about which
registers on the list are MCR registers (and in the future which
save/restore behavior we want for them).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
that in future patches.
Bspec: 66673, 66696, 66534, 67609
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 124
1 file changed, 63 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt
MTL's media GT only has a single type of steering ("OAADDRM") which
selects between media slice 0 and media slice 1. We'll always steer to
media slice 0 unless it is fused off (which is the case when VD0, VE0,
and SFC0 are all reported as unavailable).
Bspec: 67789
Signed-off-by:
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper
---
drivers
ally
steer to the primary GAM) is sufficient; we don't need to loop over each
instance of the MCR register.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 40 -
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
2 files changed, 42 insertions(+), 1 deletio
to "XEHP_" to help clarify that we're using the
newer multicast form of the register.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +-
2 files changed, 9 insertions(+), 9 deletions(-)
ate the register definitions for those registers in
preparation for upcoming patches that will handle MCR registers in a
special manner.
The registers adjusted are:
* MISCCPCTL
* SAMPLER_INSTDONE
* ROW_INSTDONE
* ROW_CHICKEN2
* HALF_SLICE_CHICKEN1
* HALF_SLICE_CHICKEN3
Signed-off-by: Matt Ro
/gitlab.freedesktop.org/drm/intel/issues/6248
> [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
> [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
> [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
> [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
> [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
> [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
> [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
>
>
> Build changes
> -
>
> * Linux: CI_DRM_12112 -> Patchwork_108394v1
>
> CI-20190529: 20190529
> CI_DRM_12112: ff8b32fbe64a79b380b1cca4232d30c0b29df069 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6650: f7aff600ab16d6405f0704b1743d2b7909715752 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_108394v1: ff8b32fbe64a79b380b1cca4232d30c0b29df069 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108394v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
b.freedesktop.org/drm/intel/issues/5325
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
> [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
> [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issue
On Fri, Sep 16, 2022 at 10:02:32AM +0100, Tvrtko Ursulin wrote:
>
> On 16/09/2022 02:43, Matt Roper wrote:
> > Although the bspec lists several MMIO ranges as "MSLICE," it turns out
> > that a subset of these are of a "GAM" subclass that has unique rules a
dware default should already be set to 1,0 properly, but it never
hurts to ensure that in the driver.
Bspec: 66534
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 24 +++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/inte
On Thu, Sep 15, 2022 at 03:25:15PM +0300, Jani Nikula wrote:
> On Wed, 14 Sep 2022, Matt Roper wrote:
> > Now that MTL is going to start providing two GTs, there are a few more
> > places in the driver that need to iterate over each GT instead of
> > operating directly on
lls around
but is otherwise pretty un-eventuful.
v2:
- Consolidate adjacent GT loops in a couple places. (Daniele)
Cc: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_driver.c | 3 ++-
drivers/gpu/drm/i915/i915_gem
Now that MTL is going to start providing two GTs, there are a few more
places in the driver that need to iterate over each GT instead of
operating directly on gt0. Also some more deliberate cleanup is needed,
in cases where we fail GT/engine initialization after the first GT has
been fully setup.
rop the destroy_pinned_context() helper for now. It's not really
worth it with just a single callsite at the moment. (Janusz)
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
d
From: Tvrtko Ursulin
Walk all GTs from i915_gem_resume when resuming engines.
Cc: Andi Shyti
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 22 --
1 file changed, 20 insertions(+), 2 deletions
From: Tvrtko Ursulin
Walk all GTs when suspending.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem
lls around
but is otherwise pretty un-eventuful.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_driver.c | 3 +-
drivers/gpu/drm/i915/i915_gem.c| 46 ++
2 files changed, 36 insertions(+), 13 deletions(-)
From: Tvrtko Ursulin
Walk all GTs from i915_gem_resume when resuming engines.
Cc: Andi Shyti
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers
From: Tvrtko Ursulin
Walk all GTs when suspending.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915
Cc: Janusz Krzysztofik
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1f7188129cd1..bff12b4ec
Now that MTL is going to start providing two GTs, there are a few more
places in the driver that need to iterate over each GT instead of
operating directly on gt0. Also some more deliberate cleanup is needed,
in cases where we fail GT/engine initialization after the first GT has
been fully setup.
Omit display version check in i915_reg.h(Jani)
> v3:
> - Remove extra whitespace introduced
> - Fix reg definitions for MTL_CHICKEN_TRANS(MattR)
>
> Bspec: 34387, 50054
> Cc: Jani Nikula
> Cc: Matt Roper
> Signed-off-by: Madhumitha Tolakanahalli Pradeep
>
> Signed
f bank check(MattR)
> - Skip modeset check to ahndle the case when a new pipe within
s/ahndle/handle/
Otherwise,
Reviewed-by: Matt Roper
>dbuf bank gets added/removed.(MattR)
>
> Bspec: 49213
>
> Cc: Jose Roberto de Souza
> Cc: Matt Roper
> Original Author: Caz
On Tue, Sep 13, 2022 at 11:33:39AM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper
>
> The part of the media and blitter engine contexts that we care about for
> setting up an initial state are the same on MTL as they were on DG2
> (and PVC), so we need to update the dr
media_table,
> +
> ARRAY_SIZE(gmd_media_table));
> + step.display_step = gmd_to_intel_step(i915,
> +
> _INFO(i915)->display.ip,
> +
On Mon, Sep 12, 2022 at 06:47:56PM +0200, Mauro Carvalho Chehab wrote:
> Hi Matt,
>
> Em Mon, 12 Sep 2022 08:09:57 -0700
> Matt Roper escreveu:
>
> > > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_c
/*
>* @timer: Timer for internal i915 PMU sampling.
>*/
> struct hrtimer timer;
> - /**
> + /*
>* @enable: Bitmask of specific enabled events.
>*
>* For some events we need to track their state and do some internal
> @@ -92,14 +92,14 @@ struct i915_pmu {
>*/
> u32 enable;
>
> - /**
> + /*
>* @timer_last:
>*
>* Timestmap of the previous timer invocation.
>*/
> ktime_t timer_last;
>
> - /**
> + /*
>* @enable_count: Reference counts for the enabled events.
>*
>* Array indices are mapped in the same way as bits in the @enable field
> @@ -107,11 +107,11 @@ struct i915_pmu {
>* are using the PMU API.
>*/
> unsigned int enable_count[I915_PMU_MASK_BITS];
> - /**
> + /*
>* @timer_enabled: Should the internal sampling timer be running.
>*/
> bool timer_enabled;
> - /**
> + /*
>* @sample: Current and previous (raw) counters for sampling events.
>*
>* These counters are updated from the i915 PMU sampling timer.
> @@ -120,11 +120,11 @@ struct i915_pmu {
>* struct intel_engine_cs.
>*/
> struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
> - /**
> + /*
>* @sleep_last: Last time GT parked for RC6 estimation.
>*/
> ktime_t sleep_last;
> - /**
> + /*
>* @irq_count: Number of interrupts
>*
>* Intentionally unsigned long to avoid atomics or heuristics on 32bit.
> @@ -132,15 +132,15 @@ struct i915_pmu {
>* occasional wraparound easily. It's 32bit after all.
>*/
> unsigned long irq_count;
> - /**
> + /*
>* @events_attr_group: Device events attribute group.
>*/
> struct attribute_group events_attr_group;
> - /**
> + /*
>* @i915_attr: Memory block holding device attributes.
>*/
> void *i915_attr;
> - /**
> + /*
>* @pmu_attr: Memory block holding device attributes.
>*/
> void *pmu_attr;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h
> b/drivers/gpu/drm/i915/intel_uncore.h
> index b1fa912a65e7..5f896fbf3064 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -39,7 +39,7 @@ struct intel_uncore;
> struct intel_gt;
>
> struct intel_uncore_mmio_debug {
> - spinlock_t lock; /** lock is also taken in irq contexts. */
> + spinlock_t lock; /* lock is also taken in irq contexts. */
> int unclaimed_mmio_check;
> int saved_mmio_check;
> u32 suspend_count;
> @@ -133,7 +133,7 @@ struct intel_uncore {
> struct intel_gt *gt;
> struct intel_runtime_pm *rpm;
>
> - spinlock_t lock; /** lock is also taken in irq contexts. */
> + spinlock_t lock; /* lock is also taken in irq contexts. */
>
> unsigned int flags;
> #define UNCORE_HAS_FORCEWAKE BIT(0)
> --
> 2.37.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/intel_uncore.c | 258 +-
drivers/gpu/drm/i915/intel_uncore.h | 2 +
drivers/gpu/drm/i915/selftests/intel_uncore.c | 4 +
4 files changed, 258 insertions(+), 11
1]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> [i915#5072]: https://gitlab.freedesktop.org/drm/intel/issues/5072
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5591]: https://gitlab.freedesktop.org/drm/i
tps://gitlab.freedesktop.org/drm/intel/issues/4991
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
> [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
> [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
> [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
> [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
> [i915#6375]: https://gitlab.freedesktop.org/drm/intel/issues/6375
> [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
> [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>
>
> Build changes
> -
>
> * Linux: CI_DRM_12098 -> Patchwork_108277v2
>
> CI-20190529: 20190529
> CI_DRM_12098: be32ae92a328265c2e49e459259eaae3b5f6b754 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_108277v2: be32ae92a328265c2e49e459259eaae3b5f6b754 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
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