Re: [Intel-gfx] [PATCH 13/20] drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11

6 +591,7 @@ static const struct intel_device_info intel_icelake_11_info = { .platform = INTEL_ICELAKE, .is_alpha_support = 1, .has_resource_streamer = 0, + .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING, }; /* -- 2.14.1 Reviewed-

Re: [Intel-gfx] [PATCH 01/20] drm/i915/icl: Add the ICL PCI IDs

, info), \ + INTEL_VGA_DEVICE(0x8A71, info), \ + INTEL_VGA_DEVICE(0x8A70, info) + #endif /* _I915_PCIIDS_H */ List is still correct and up-to-date. Reviewed-by: Michel Thierry <michel.thie...@intel.com> -- 2.14.1 ___ Intel-gfx ma

Re: [Intel-gfx] [PATCH v9 1/7] drm/i915/guc: Move GuC WOPCM related code into separate files

On 2/9/2018 11:38 AM, Yaodong Li wrote: On 02/09/2018 08:46 AM, Michal Wajdeczko wrote: --- /dev/null +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c @@ -0,0 +1,48 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2017-2018 Intel Corporation + * Do we really want to keep legacy license

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: Only allocate preempt context when required

diusz.hi...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Acked-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Only this one was missing a r-b, but all 3: Reviewed-by: Michel Thierry <mich

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Flush GTIIR on clearing CS interrupts during reset

. This hopefully reduces the frequency to 0... References: https://bugs.freedesktop.org/show_bug.cgi?id=104262 Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Tvrtko Ur

[Intel-gfx] [PATCH v11] drm/i915/icl: Gen11 forcewake support

s (Tvrtko) Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Paulo Zanoni <paulo.r.zan...@intel.com> Acked-by: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@i

Re: [Intel-gfx] [PATCH v10] drm/i915/icl: Gen11 forcewake support

On 2/1/2018 2:25 AM, Tvrtko Ursulin wrote: On 01/02/2018 00:52, Michel Thierry wrote: From: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> The main difference with previous GENs is that starting from Gen11 each VCS and VECS engine has its own power well, which only

[Intel-gfx] [PATCH v10] drm/i915/icl: Gen11 forcewake support

Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Paulo Zanoni <paulo.r.zan...@intel.com> Acked-by: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Signed-off

Re: [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Remove the ring advancement under preemption

said the preempt ctx could not be running at this point. Michal(s)/Tvrtko/Mika, any thoughts? Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <micha

Re: [Intel-gfx] [PATCH 1/2] drm/i915/lrc: Clear context restore/save inhibit flags for new contexts

this note: "This is not a true register bit This bit will always be in clear state on a context save of this bit". Maybe that's why didn't see any problems. But it doesn't hurt being paranoid. Reviewed-by: Michel Thierry <michel.thie...@intel.com> Fixes: 517aaffe0c1b ("drm/i915/

[Intel-gfx] [PATCH v2 12/27] drm/i915/icl: Add Indirect Context Offset for Gen11

v2: rebased to intel_lr_indirect_ctx_offset v3: rebase, move define to intel_lrc_reg.h BSpec: 11740 Signed-off-by: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Review

Re: [Intel-gfx] [PATCH v2] drm/i915/execlists: Inhibit context save/restore for the fake preempt context

On 1/24/2018 12:46 PM, Chris Wilson wrote: Quoting Chris Wilson (2018-01-24 09:44:45) Quoting Michel Thierry (2018-01-24 01:24:25) On 1/23/2018 1:04 PM, Chris Wilson wrote: We only use the preempt context to inject an idle point into execlists. We never need to reference its logical state, so

Re: [Intel-gfx] [PATCH v2] drm/i915/execlists: Inhibit context save/restore for the fake preempt context

moved into the submission process rather than the context image. Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@

[Intel-gfx] [PATCH 1/2] drm/i915/lrc: Update reg_state macros to pass checkpatch

that '+' (ctx:VxV) So fix these issues before they are moved to a new header file. Suggested-by: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 2/2] drm/i915: Move LRC register offsets to a header file

and intel_guc_reg.h (Chris) v3: License notice shenanigans. v4: Documentation/process/coding-style.rst is always right (Chris) v5: Rebase. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Lucas De Marchi <lucas.demar...@intel.com> Cc

[Intel-gfx] [PATCH v4] drm/i915: Move LRC register offsets to a header file

and intel_guc_reg.h (Chris) v3: License notice shenanigans. v4: Documentation/process/coding-style.rst is always right (Chris) Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Lucas De Marchi <lucas.demar...@intel.com> Cc: Chris W

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Inhibit context save/restore for the fake preempt context

ed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Kuoppala <mi

Re: [Intel-gfx] [PATCH v2] drm/i915: Move LRC register offsets to a header file

On 1/22/2018 4:31 PM, Lucas De Marchi wrote: So for this file what I understand is that it should be: // SPDX-License-Identifier: MIT // Copyright (C) 2014-2018 Intel Corporation So be it. ___ Intel-gfx mailing list

[Intel-gfx] [PATCH v3] drm/i915: Move LRC register offsets to a header file

and intel_guc_reg.h (Chris) v3: License notice shenanigans. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Lucas De Marchi <lucas.demar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i

Re: [Intel-gfx] [PATCH v2] drm/i915: Move LRC register offsets to a header file

On 22/01/18 13:28, Michal Wajdeczko wrote: On Mon, 22 Jan 2018 21:56:36 +0100, Lucas De Marchi <lucas.demar...@intel.com> wrote: On Mon, Jan 22, 2018 at 12:32:57PM -0800, Michel Thierry wrote: Newer platforms may have subtle offset changes, which will increase the number of defin

[Intel-gfx] [PATCH v2] drm/i915: Move LRC register offsets to a header file

and intel_guc_reg.h (Chris) Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Lucas De Marchi <lucas.demar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_lrc.c | 50 +---

Re: [Intel-gfx] [PATCH] drm/i915: Move LRC register offsets to a header file

On 1/22/2018 12:14 PM, Chris Wilson wrote: Quoting Michel Thierry (2018-01-22 20:06:32) Newer platforms may have subtle offset changes, which will increase the number of defines, so it is probably better to start moving them to its own header file. Also move the macros used while setting

[Intel-gfx] [PATCH] drm/i915: Move LRC register offsets to a header file

Newer platforms may have subtle offset changes, which will increase the number of defines, so it is probably better to start moving them to its own header file. Also move the macros used while setting the reg state. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Waj

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Downgrade incorrect engine constructor usage warnings to development

during development. Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 3 ++- drivers/gpu/drm/i915/intel_lrc.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/dr

Re: [Intel-gfx] [PATCH] intel: Future-proof ring names for aubinator_error_decode

state to use the new naming scheme. This of course means we need to teach aubinator_error_decode how to map both sets of ring names onto its register maps. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko &l

Re: [Intel-gfx] [PATCH v2] drm/i915: Use the engine name directly in the error_state file

On 17/01/18 07:15, Chris Wilson wrote: Quoting Michel Thierry (2018-01-16 18:33:32) On 1/15/2018 9:15 AM, Tvrtko Ursulin wrote: On 10/01/2018 01:21, Michel Thierry wrote: Instead of using local string names that we will have to keep maintaining, use the engine->name directly. v2: Bet

Re: [Intel-gfx] [PATCH i-g-t v3] tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation

iling. v2: - Add the commit that changed the behaviour in the Driver to the commit message. (Michel) v3: - Reuse get_reset_count instead of implementing a new function. (Michel) Cc: Michel Thierry <michel.thie...@intel.com> Cc: Arkadiusz Hiler <arkadi

Re: [Intel-gfx] [PATCH i-g-t v2] tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation

stats") and therefore the test was incorrectly failing. v2: - Add the commit that changed the behaviour in the Driver to the   commit message (Michel) Cc: Michel Thierry <michel.thie...@intel.com> Cc: Arkadiusz Hiler <arkadiusz.hi...@intel.com> Cc: Chris Wilson <ch...@chris

Re: [Intel-gfx] [PATCH v2] drm/i915: Use the engine name directly in the error_state file

On 1/15/2018 9:15 AM, Tvrtko Ursulin wrote: On 10/01/2018 01:21, Michel Thierry wrote: Instead of using local string names that we will have to keep maintaining, use the engine->name directly. v2: Better invalid engine_id handling, capture_bo will not be able know the engine_id and end

Re: [Intel-gfx] [PATCH v2] drm/i915: Use the engine name directly in the error_state file

On 1/9/2018 5:21 PM, Michel Thierry wrote: Instead of using local string names that we will have to keep maintaining, use the engine->name directly. v2: Better invalid engine_id handling, capture_bo will not be able know the engine_id and end up with -1 (Michal). Hi, Fi.CI.IGT didn't ca

Re: [Intel-gfx] [PATCH v3] drm/i915: Stop getting the fault address from RING_FAULT_REG

rmat) instead of PAGE_SIZE (Chris) - s/BITS_44_TO_47/HIGHBITS (Chris) - Right formatting, this time for real Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8 onwards") Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <miche

[Intel-gfx] [PATCH v2] drm/i915: Use the engine name directly in the error_state file

igned-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gpu_error.c | 33 - 1 file changed, 20 insertions(+), 13 deletions(-) d

Re: [Intel-gfx] [PATCH] drm/i915: Use the engine name directly in the error_state file

On 09/01/18 13:37, Michel Thierry wrote: On 09/01/18 12:46, Chris Wilson wrote: Quoting Michal Wajdeczko (2018-01-09 20:39:09) On Tue, 09 Jan 2018 20:33:55 +0100, Michel Thierry <michel.thie...@intel.com> wrote: Instead of using local string names that we will have to keep maintainin

Re: [Intel-gfx] [PATCH] drm/i915: Use the engine name directly in the error_state file

On 09/01/18 12:46, Chris Wilson wrote: Quoting Michal Wajdeczko (2018-01-09 20:39:09) On Tue, 09 Jan 2018 20:33:55 +0100, Michel Thierry <michel.thie...@intel.com> wrote: Instead of using local string names that we will have to keep maintaining, use the engine->name directly.

[Intel-gfx] [PATCH] drm/i915: Use the engine name directly in the error_state file

Instead of using local string names that we will have to keep maintaining, use the engine->name directly. Suggested-by: Michal Wajdeczko <michal.wajdec...@intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com>

Re: [Intel-gfx] [PATCH] drm/i915: Avoid context dereference inside execlists_submission_tasklet

engine->name, - rq->ctx->hw_id, count, + port->context_id, count, rq->global_seqno); GEM_BUG_ON(coun

Re: [Intel-gfx] [PATCH 3/3] drm/i915/selftests: Fix up igt_reset_engine

i915_reset_engine() by loading it with requests. Fixes: f6ba181ada55 ("drm/i915: Skip an engine reset if it recovered before our preparations") Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Mika Kuoppala <mika

Re: [Intel-gfx] [PATCH] drm/i915: Restore the kernel context after a GPU reset on an idle engine

if (!IS_ERR(rq)) + __i915_add_request(rq, false); + } } i915_gem_restore_fences(dev_priv); It shouldn't hurt and if it fixes something, Reviewed-by: Michel Thierry <michel.thie...@intel.com> _

Re: [Intel-gfx] [PATCH v2] drm/i915: Skip an engine reset if it recovered before our preparations

before we could issue a reset, so let the engine continue on without a reset. If the engine is truly stuck, we will back soon enough with the next reset attempt. v2: Remove the stale debug message. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@inte

Re: [Intel-gfx] [PATCH] drm/i915: Skip an engine reset if it recovered before our preparations

On 12/15/2017 4:16 PM, Chris Wilson wrote: Quoting Michel Thierry (2017-12-16 00:02:47) Hi, On 12/15/2017 3:52 PM, Chris Wilson wrote: At the beginning of a reset, we disable the submission method and find the stuck request. We expect to find a stuck request for we have declared the engine

Re: [Intel-gfx] [PATCH] drm/i915: Skip an engine reset if it recovered before our preparations

stall before we could issue a reset, so let the engine continue on without a reset. If the engine is truly stuck, we will back soon enough with the next reset attempt. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Mika Kuoppala

Re: [Intel-gfx] [PATCH 7/8] drm/i915/guc: Extract doorbell verification into a function

Reviewed-by: Michal Wajdeczko <michal.wajdec...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 6/8] drm/i915/guc: Extract clients allocation to submission_init

son.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> --- Reviewed-by: Michel Thierry <michel.thie...@intel.com> drivers/gpu/drm/i915/intel_guc_submission.c | 33 ++--- 1 file changed,

Re: [Intel-gfx] [PATCH 5/8] drm/i915/guc: Extract doorbell creation from client allocation

intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_guc_submission.c | 151 ---

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation

that changed the behaviour, ...when not root. This is no longer true in the driver since commit 4c9c0d09741d ("drm/i915: Fix retrieval of hangcheck stats") and therefore... the test was incorrectly failing. Cc: Michel Thierry <michel.thie...@intel.com> Cc: Arkadiusz Hil

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Cache ELSP register offset

ine_cs *engine) desc = 0; } - elsp_write(desc, elsp); + elsp_write(desc, engine->execlists.elsp); } execlists_clear_active(>execlists, EXECLISTS_ACTIVE_HWACK); } --- Anyway, Reviewed-by: Michel Th

Re: [Intel-gfx] [PATCH] drm/i915: Fix compilation (panel orientation x enum plane rename).

this race the second patch got merged first so the first one broke i915 compilation. Thanks to Michel this was found quickly. Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniel Vetter <daniel.vet...@ffwll.ch> Cc: Hans de Goede <hdego...@redhat.com> Suggested-by:

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Declare we allocated the guc clients

C doorbells selftest") Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Anyway, thanks for fixing it

Re: [Intel-gfx] [PATCH] drm/i915/selftest: Make guc clients static

On 11/20/2017 5:26 AM, Chris Wilson wrote: Make the private array used for stashing test clients static, to silence sparse. References: 55bd6bd75717 ("drm/i915/selftests: Add a GuC doorbells selftest") Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thie

Re: [Intel-gfx] [PATCH 4/4] drm/i915/execlists: Delay writing to ELSP until HW has processed the previous write

tps://bugs.freedesktop.org/show_bug.cgi?id=102035 Suggested-by: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Isn't it nice to come back after the weekend and see everything is o

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

gt; Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index be6c39adebd

[Intel-gfx] [PATCH] drm/i915/lrc: Stop writing to ELSP until HW has processed the previous write

tatus_reg = 0x7_8308 Note that having to wait for this ack does not disable lite-restores, although it may reduce their numbers. And take this as a RFC, since there are probably better ways to still respect this HW requirement. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102035 Sig

[Intel-gfx] [PATCH v5 2/2] HAX enable GuC submission for CI

From: Michal Wajdeczko Also revert ("drm/i915/guc: Assert that we switch between known ggtt->invalidate functions") Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++-- drivers/gpu/drm/i915/i915_params.h

[Intel-gfx] [PATCH v5 1/2] drm/i915/selftests: Add a GuC doorbells selftest

btest. v5: Remove redundant pr_info at the beginning of each subtest (Chris); rebase (s/i915_guc_client/intel_guc_client/). Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.

Re: [Intel-gfx] [PATCH v4 1/3] drm/i915/selftests: Add a GuC doorbells selftest

On 11/16/2017 7:10 AM, Chris Wilson wrote: Quoting Michel Thierry (2017-11-15 18:30:27) The first test aims to check guc_init_doorbell_hw, changing the existing guc clients and doorbells state before calling it. The second test tries to create as many clients as it is currently possible

[Intel-gfx] [PATCH 3/3] HAX enable GuC submission for CI

From: Michal Wajdeczko Also revert ("drm/i915/guc: Assert that we switch between known ggtt->invalidate functions") Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++-- drivers/gpu/drm/i915/i915_params.h

[Intel-gfx] [PATCH v4 1/3] drm/i915/selftests: Add a GuC doorbells selftest

t. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_guc_submission.c |

[Intel-gfx] [RFC 2/3] drm/i915/guc: Omit guc_init_doorbell_hw during driver load

guc_init_doorbell_hw is no longer the right name, but I'll leave that to someone else. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...

[Intel-gfx] [PATCH v3] drm/i915: There is only one fault register from GEN8 onwards

check for engine presence before posting_read (Chris). References: IHD-OS-BDW-Vol 2c-11.15, page 75. References: IHD-OS-SKL-Vol 2c-05.16, page 350. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem_

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible

On 11/10/2017 5:15 PM, Chris Wilson wrote: Quoting Patchwork (2017-11-11 01:03:20) == Series Details == Series: series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible URL : https://patchwork.freedesktop.org/series/33649/ State : success BAT results

[Intel-gfx] [PATCH 2/2 v2] drm/i915: There is only one fault register from GEN8 onwards

: IHD-OS-SKL-Vol 2c-05.16, page 350. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 52 +++ drivers/gpu/drm/i915/i915_gpu_error.c | 8 -- drivers/

[Intel-gfx] [PATCH 1/2] drm/i915: Clear per-engine fault register as early as possible

this is inside intel_engines_init_mmio(). Suggested-by: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++ drivers/gpu/drm/i915/intel_uncore.c

Re: [Intel-gfx] [PATCH] drm/i915: There is only one fault register from GEN8 onwards

On 11/10/2017 3:50 PM, Chris Wilson wrote: Quoting Michel Thierry (2017-11-10 23:42:31) On 11/10/2017 12:51 PM, Chris Wilson wrote: Quoting Michel Thierry (2017-11-10 19:01:16) Until Haswell/Baytrail, the hardware used to have a per engine fault register (e.g. 0x4094 - render fault register

Re: [Intel-gfx] [PATCH] drm/i915: There is only one fault register from GEN8 onwards

On 11/10/2017 12:51 PM, Chris Wilson wrote: Quoting Michel Thierry (2017-11-10 19:01:16) Until Haswell/Baytrail, the hardware used to have a per engine fault register (e.g. 0x4094 - render fault register, 0x4194 - media fault register and so on). But since Broadwell, all these registers were

[Intel-gfx] [PATCH v3] drm/i915/selftests: Add a GuC doorbells selftest

of clients; check for client allocation failure when number of doorbells is exceeded; validate client properties; reuse guc_init_doorbell_hw (Chris). v3: guc_init_doorbell_hw test added per Chris suggestion. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczk

[Intel-gfx] [PATCH] drm/i915: There is only one fault register from GEN8 onwards

-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 38 ++- drivers/gpu/drm/i915/i915_gpu_error.c | 8 +--- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 3 files changed, 40 insertions(+), 8 deletions(-) diff --git a/drive

Re: [Intel-gfx] [PATCH] drm/i915/guc: Clear terminated attribute bit on GuC preemption context

data[1] = client->stage_id; data[2] = INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q | -- 2.14.2 Since Michał is not around, Reviewed-by: Michel Thierry <michel.thie...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v6] drm/i915/guc: Add support for reset engine using GuC commands

off-by: Michel Thierry <michel.thie...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_drv.c | 15 +-- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_guc.c | 24 drive

Re: [Intel-gfx] ✗ Fi.CI.IGT: warning for GuC based reset engine

On 10/31/2017 3:20 AM, Chris Wilson wrote: Quoting Patchwork (2017-10-30 23:20:13) For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6267/shards.html https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6267/shard-kbl1/igt@prime_b...@wait-hang-render.html is suspicious.

Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Add support for reset engine using GuC commands

On 30/10/17 14:09, Chris Wilson wrote: Quoting Michel Thierry (2017-10-30 18:56:15) This patch adds per engine reset and recovery (TDR) support when GuC is used to submit workloads to GPU. In the case of i915 directly submission to ELSP, driver manages hang detection, recovery and resubmission

Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Add support for reset engine using GuC commands

On 30/10/17 13:58, Chris Wilson wrote: Quoting Michel Thierry (2017-10-30 18:56:15) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index af745749509c..02fb35744f66 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1984,10

[Intel-gfx] [PATCH 1/3] drm/i915/guc: Rename the function that resets the GuC

rsu...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_uc.c | 4 ++-- drivers/gpu/drm/i915/intel_uncore.c | 2 +- 3 files cha

[Intel-gfx] [PATCH 2/3] drm/i915/guc: Add support for reset engine using GuC commands

it regardless of submission mode. (Chris) v4: Rebase. v5: Do not pass unnecessary reporting flags to the fw (Jeff); tasklet_schedule(>irq_tasklet) handles the resubmit; rebase. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drive

[Intel-gfx] [PATCH 0/3] GuC based reset engine

rtko.ursu...@linux.intel.com> Michal Wajdeczko (1): HAX enable GuC submission for CI Michel Thierry (2): drm/i915/guc: Rename the function that resets the GuC drm/i915/guc: Add support for reset engine using GuC commands drivers/gpu/drm/i915/i915_drv.c | 9 +++-- drivers/

[Intel-gfx] [PATCH 3/3] HAX enable GuC submission for CI

From: Michal Wajdeczko Also revert ("drm/i915/guc: Assert that we switch between known ggtt->invalidate functions") Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++-- drivers/gpu/drm/i915/i915_params.h

[Intel-gfx] [PATCH] drm/i915/cnl: Remove unnecessary check in cnl_setup_private_ppat

lable to submit work." Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 6 -- 1 file changed, 6 deletions(-)

Re: [Intel-gfx] [PATCH v6] drm/i915/guc: Add a second client, to be used for preemption

On 10/26/2017 1:02 PM, Chris Wilson wrote: Quoting Michel Thierry (2017-10-26 19:49:06) On 26/10/17 07:17, Michał Winiarski wrote: @@ -763,14 +770,14 @@ static int guc_init_doorbell_hw(struct intel_guc *guc) /* Now for every client (and not only execbuf_client) make sure

Re: [Intel-gfx] [PATCH v2] drm/i915/selftests: Add a GuC doorbells selftest

On 26/10/17 11:51, Michel Thierry wrote: Try to create as many clients as it is currently possible (currently limited to max number of doorbells) and exercise the doorbell alloc/dealloc code. Since our usage mode require very few clients/doorbells, this code has been exercised very lightly

[Intel-gfx] [PATCH v2] drm/i915/selftests: Add a GuC doorbells selftest

_hw (Chris). Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wi

Re: [Intel-gfx] [PATCH v6] drm/i915/guc: Add a second client, to be used for preemption

On 26/10/17 07:17, Michał Winiarski wrote: @@ -763,14 +770,14 @@ static int guc_init_doorbell_hw(struct intel_guc *guc) /* Now for every client (and not only execbuf_client) make sure their * doorbells are known by the GuC */ - //for (client = client_list; client !=

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Add a GuC doorbells selftest

On 25/10/17 14:19, Michel Thierry wrote: On 25/10/17 14:08, Chris Wilson wrote: Quoting Michel Thierry (2017-10-25 21:53:44) Try to create multiple clients (one of each kind) and exercise the doorbell alloc/dealloc code. Since our usage mode require very few clients/doorbells, this code has

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Add a GuC doorbells selftest

On 25/10/17 14:08, Chris Wilson wrote: Quoting Michel Thierry (2017-10-25 21:53:44) Try to create multiple clients (one of each kind) and exercise the doorbell alloc/dealloc code. Since our usage mode require very few clients/doorbells, this code has been exercised very lightly and it's good

Re: [Intel-gfx] [PATCH v2 03/12] drm/i915/guc: Allocate separate shared data object for GuC communication

confusing (why are we using this particular page?). Let's allocate a separate object instead. v2: Drop kernel_context from GuC suspend/resume action handlers (Michel) v2 Reviewed-by: Michel Thierry <michel.thie...@intel.com> Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@

[Intel-gfx] [PATCH] drm/i915/selftests: Add a GuC doorbells selftest

fixed by commit 7f1ea2ac3017 ("drm/i915/guc: Fix doorbell id selection"). Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Michal Winiarski

Re: [Intel-gfx] [PATCH v3 01/22] drm/i915: Use a mask when applying WaProgramL3SqcReg1Default

@linux.intel.com> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Cc: Imre Deak <imre.d...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> If this gets lost in the series, please send separately to bring attention to the bugfix. Hopefully r-b's will be prompt... This is w

Re: [Intel-gfx] [PATCH 02/12] drm/i915/guc: Allocate separate shared data object for GuC communication

On 12/10/17 13:35, Michel Thierry wrote: On 09/10/17 15:35, Michel Thierry wrote: On 10/9/2017 11:41 AM, Daniele Ceraolo Spurio wrote: On 09/10/17 07:52, Michał Winiarski wrote: We were using first page of kernel context render state for sharing data with GuC. While it's justified

Re: [Intel-gfx] [PATCH 03/12] drm/i915/guc: Initialize GuC before restarting engines

already in user requested submission mode. Signed-off-by: Michał Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Mika Kuoppala <mika.ku

Re: [Intel-gfx] [PATCH 02/12] drm/i915/guc: Allocate separate shared data object for GuC communication

On 09/10/17 15:35, Michel Thierry wrote: On 10/9/2017 11:41 AM, Daniele Ceraolo Spurio wrote: On 09/10/17 07:52, Michał Winiarski wrote: We were using first page of kernel context render state for sharing data with GuC. While it's justified by the fact that those pages are not used (note

Re: [Intel-gfx] [PATCH 02/12] drm/i915/guc: Allocate separate shared data object for GuC communication

On 10/9/2017 11:41 AM, Daniele Ceraolo Spurio wrote: On 09/10/17 07:52, Michał Winiarski wrote: We were using first page of kernel context render state for sharing data with GuC. While it's justified by the fact that those pages are not used (note, GuC still enforces this layout and refuses

Re: [Intel-gfx] [RFC PATCH 01/11] drm/i915: No need for RING_MAX_NONPRIV_SLOTS space

uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Is it worth mention the commit that changed this? E.g.: Now that we write RING_FORCE_TO_NONPRIV registers directly to hardware [commit 32ced39c1b12 ("drm/i915: Transform whitelisting WAs into a simple reg write")]... Anywa

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Add a comment for the extra MI_ARB_ENABLE

On 10/5/2017 12:10 PM, Chris Wilson wrote: Michel Thierry noticed that we were applying WaDisableCtxRestoreArbitration even to gen9, which does not require the w/a. The rationale is that we need to enable MI arbitration for execlists to work, and to be safe we do that before every batch

Re: [Intel-gfx] [PATCH] drm/i915/execlists: WaDisableCtxRestoreArbitration is only needed in gen8

On 10/5/2017 11:28 AM, Chris Wilson wrote: Quoting Michel Thierry (2017-10-05 19:19:27) WaDisableCtxRestoreArbitration was only applied for bdw and chv, but this changed after the code got moved to gen8_emit_bb_start (and, at least in my tree, there is no gen9_emit_bb_start). But I need

[Intel-gfx] [PATCH] drm/i915/execlists: WaDisableCtxRestoreArbitration is only needed in gen8

WaDisableCtxRestoreArbitration was only applied for bdw and chv, but this changed after the code got moved to gen8_emit_bb_start (and, at least in my tree, there is no gen9_emit_bb_start). Fixes: 3ad7b52d962e ("drm/i915/execlists: Move bdw GPGPU w/a to emit_bb") Signed-off-by: Mich

Re: [Intel-gfx] [PATCH] drm/i915: Transform whitelisting WAs into a simple reg write

On 9/29/2017 3:25 AM, Joonas Lahtinen wrote: On Thu, 2017-09-28 at 16:47 -0700, Michel Thierry wrote: On 28/09/17 15:40, Oscar Mateo wrote: RING_FORCE_TO_NONPRIV registers do not live in the logical context. They are simply global privileged MMIO registers that happen to be powercontext saved

Re: [Intel-gfx] [PATCH] drm/i915: Transform whitelisting WAs into a simple reg write

engine->mmio_base, index), + i915_mmio_reg_offset(reg)); wa->hw_whitelist_count[engine->id]++; return 0; -- 1.9.1 I see RCS_FORCE_TO_NONPRIV in "Render Engine *Power* Context" and not in the "Register State Context", so

Re: [Intel-gfx] [PATCH] drm/i915: Re-enable per-engine reset for Broxton

On 05/09/17 06:57, Chris Wilson wrote: Quoting Chris Wilson (2017-08-21 15:55:34) Quoting Michel Thierry (2017-08-18 18:23:42) The corruption in CSB mmio reads we were seeing has been tracked down to incorrectly touching forcewake of all domains, following an engine reset. It is still

[Intel-gfx] [PATCH v2] drm/i915: Add a default case in gen7 hwsp switch-case

(Chris). Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/

Re: [Intel-gfx] [PATCH] drm/i915: Add a default case in gen7 hwsp switch-case

On 29/08/17 12:18, Chris Wilson wrote: Quoting Michel Thierry (2017-08-29 19:55:45) Gen7 won't get any new engines, and we already added VCS2 there to just silence gcc's not-handled-in-switch warnings. Use a default case instead, otherwise we will need to keep adding extra cases if changes

[Intel-gfx] [PATCH] drm/i915: Add a default case in gen7 hwsp switch-case

Gen7 won't get any new engines, and we already added VCS2 there to just silence gcc's not-handled-in-switch warnings. Use a default case instead, otherwise we will need to keep adding extra cases if changes happen in the future. Signed-off-by: Michel Thierry <michel.thie...@intel.

Re: [Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

engine_mask &= ~intel_engine_flag(engine); Reviewed-by: Michel Thierry <michel.thie...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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