On 7/29/2015 5:23 PM, Michel Thierry wrote:
Michel Thierry (19):
drm/i915: Remove unnecessary gen8_clamp_pd
drm/i915/gen8: Make pdp allocation more dynamic
drm/i915/gen8: Abstract PDP usage
drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT
drm/i915/gen8: Add dynamic page trace
ingen8_ppgtt_insert_pte_entries until this
commit (Akash).
Reviewed-by: Akash Goel akash.g...@intel.com (v9)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 52 +
1 file changed, 36 insertions(+), 16
akash.g...@intel.com (v3)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers
goto free_scratch in temp 48-bit mode init code (Akash).
v4: kfree the pdp until the 4lvl alloc/free patch (Akash).
v5: Postpone 48-bit code in sanitize_enable_ppgtt (Akash).
v6: Keep _insert_pte_entries changes outside this patch (Akash).
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Michel
Goel akash.g...@intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++-
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++-
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7a526f9..31d20c6
On 7/30/2015 12:26 PM, Chris Wilson wrote:
On Wed, Jul 29, 2015 at 05:23:44PM +0100, Michel Thierry wrote:
This clean-up version delays the 48-bit work to later patches and includes
more review comments from Akash and Chris. The first 5 patches prepare the
dynamic page allocation code to handle
(Akash).
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 84 +++--
1 file changed, 44 insertions(+), 40 deletions(-)
diff --git
akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 53 -
1 file changed, 41 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915
goto free_scratch in temp 48-bit mode init code (Akash).
v4: kfree the pdp until the 4lvl alloc/free patch (Akash).
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 36
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c| 60 ++---
3 files
gen8_ppgtt_alloc_page_dirpointers
funtion, as we do for pds and pts; move pd and pdp setup functions to
this patch (Akash).
v15: Added kfree(pdp) from previous patch to this (Akash).
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie
Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
Note, aliasing PPGTT remains 32b only.
v2: s/full_64b/full_48b/. (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 -
drivers/gpu/drm
On 7/30/2015 5:46 AM, Goel, Akash wrote:
On 7/29/2015 9:53 PM, Michel Thierry wrote:
The insert_entries function was the function used to write PTEs. For the
PPGTT it was hardcoded to only understand two level page tables, which
was the case for GEN7. We can reuse this for 4 level page tables
On 7/30/2015 5:01 AM, Goel, Akash wrote:
On 7/29/2015 9:53 PM, Michel Thierry wrote:
Introduces the Page Map Level 4 (PML4), ie. the new top level structure
of the page tables.
To facilitate testing, 48b mode will be available on Broadwell and
GEN9+, when i915.enable_ppgtt = 3.
v2: Remove
On 7/30/2015 5:14 AM, Goel, Akash wrote:
On 7/29/2015 9:53 PM, Michel Thierry wrote:
@@ -1512,12 +1522,15 @@ static int gen8_emit_bb_start(struct
drm_i915_gem_request *req,
* Ideally, we should set Force PD Restore in ctx descriptor,
* but we can't. Force Restore would be a second
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases it is important that size is a 64b variable.
v2: Drop the warning about bind with size 0, it shouldn't happen anyway.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 5
correctly (Akash)
Fix check for entries currently using +4GB addresses, use min_t and
other polish in object_bind_to_vm (Chris)
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Akash Goel akash.g...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk (v4)
Signed-off-by: Michel
value in
execlists_update_context. (Akash)
v8: Move pd and pdp setup functions to a previous patch, they do not
belong here. (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm
and here is no exception.
v2: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
v3: Rebase after final merged version of Mika's ppgtt/scratch patches.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2)
---
drivers/gpu/drm/i915
Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
Note, aliasing PPGTT remains 32b only.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++---
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 3 insertions(+), 4 deletions
),
the used_ptes bitmap may not get updated correctly, but none of the
code-checks rely on this.
Suggested-by: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 49 +++--
1 file changed, 36 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7c024e98..7070d42 100644
patches
(and removed commit message part related to v3).
v5: Update commit message to also mention PML4 table initialization and
the new scratch pdp (Akash).
Suggested-by: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c
are already allocated (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 86 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 17
: Just kill the limit, it was only there for early detection of an
error when used for execbuffer (Chris).
Cc: Akash Goel akash.g...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 4
indentation in _alloc_pagetabs/page_directories (Chris)
v9: Defer gen8_alloc_va_range_4lvl definition until 4lvl is implemented,
clean-up gen8_ppgtt_cleanup [pun intended] (Akash).
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie
gen8_map_pagetable_range removal.
v7: Use generic page name (px) in DECLARE_EVENT_CLASS (Akash)
v8: Defer define of i915_page_directory_pointer_entry_alloc (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v3
gen8_ppgtt_alloc_page_dirpointers
function, as we do for pds and pts; move pd and pdp setup functions to
this patch (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c
goto free_scratch in temp 48-bit mode init code (Akash).
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 38 -
drivers/gpu/drm/i915
Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_debugfs.c | 18
drivers/gpu/drm/i915/i915_gem_gtt.c | 84 +
2 files changed, 94 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm
...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c6c8af7..7c024e98 100644
Otherwise it can overflow in 48-bit mode, and cause an incorrect
exec_start.
Before commit 5f19e2bffa63a91cd4ac1adcec648e14a44277ce (drm/i915: Merged
the many do_execbuf() parameters into a structure), it was already an u64.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu
been changes on them, but they require a rebase. I will also expand the
ppgtt igt test per Chris suggestions.
Michel Thierry (19):
drm/i915: Remove unnecessary gen8_clamp_pd
drm/i915/gen8: Make pdp allocation more dynamic
drm/i915/gen8: Abstract PDP usage
drm/i915/gen8: Generalize PTE writing
-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 24 ++--
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
.
Suggested-by: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ---
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915
On 7/28/2015 3:43 PM, Chris Wilson wrote:
On Tue, Jul 28, 2015 at 12:12:11PM +0100, Michel Thierry wrote:
On 7/27/2015 10:11 PM, Chris Wilson wrote:
On Thu, Jul 16, 2015 at 10:33:29AM +0100, Michel Thierry wrote:
+ if (!(entry-flags EXEC_OBJECT_SUPPORTS_48B_ADDRESS)
+ (vma
On 7/16/2015 10:33 AM, Michel Thierry wrote:
In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains
the base address to PML4, while the other PDP registers are ignored.
In LRC, the addressing mode must be specified in every context
descriptor, and the base address to PML4
On 7/16/2015 10:33 AM, Michel Thierry wrote:
PML4 has no special attributes, and there will always be a PML4.
So simply initialize it at creation, and destroy it at the end.
The code for 4lvl is able to call into the existing 3lvl page table code
to handle all of the lower levels.
v2: Return
On 7/16/2015 10:33 AM, Michel Thierry wrote:
The insert_entries function was the function used to write PTEs. For the
PPGTT it was hardcoded to only understand two level page tables, which
was the case for GEN7. We can reuse this for 4 level page tables, and
remove the concept of insert_entries
On 7/16/2015 10:33 AM, Michel Thierry wrote:
Similar to PDs, while setting up a page directory pointer, make all entries
of the pdp point to the scratch pd before mapping (and make all its entries
point to the scratch page); this is to be safe in case of out of bound
access or proactive prefetch
On 7/27/2015 10:11 PM, Chris Wilson wrote:
On Thu, Jul 16, 2015 at 10:33:29AM +0100, Michel Thierry wrote:
+ if (!(entry-flags EXEC_OBJECT_SUPPORTS_48B_ADDRESS)
+ (vma-node.start + vma-node.size) = (1ULL 32))
+ return true;
gcc completely screwed this up here
On 7/27/2015 3:46 PM, Chris Wilson wrote:
On Mon, Jul 27, 2015 at 08:04:50PM +0530, Goel, Akash wrote:
On 7/16/2015 3:03 PM, Michel Thierry wrote:
There are some allocations that must be only referenced by 32-bit
offsets. To limit the chances of having the first 4GB already full,
objects
).
Suggested-by: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 38 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915
.
Suggested-by: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ---
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915
and here is no exception.
v2: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
v3: Rebase after final merged version of Mika's ppgtt/scratch patches.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2)
---
drivers/gpu/drm/i915
-by: Chris Wilson ch...@chris-wilson.co.uk (v4)
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 2 ++
drivers/gpu/drm/i915/i915_gem.c| 14 --
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 13 +
include/uapi
: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 49 +++--
1 file changed, 36 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915
-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 24 ++--
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
Note, aliasing PPGTT remains 32b only.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++---
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 3 insertions(+), 4 deletions
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases it is important that size is a 64b variable.
v2: Drop the warning about bind with size 0, it shouldn't happen anyway.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 5
Otherwise it can overflow in 48-bit mode, and cause an incorrect
exec_start.
Before commit 5f19e2bffa63a91cd4ac1adcec648e14a44277ce (drm/i915: Merged
the many do_execbuf() parameters into a structure), it was already an u64.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu
indentation in _alloc_pagetabs/page_directories (Chris)
v9: Defer gen8_alloc_va_range_4lvl definition until 4lvl is implemented,
clean-up gen8_ppgtt_cleanup [pun intended] (Akash).
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie
-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 163
drivers/gpu/drm/i915/i915_gem_gtt.h | 13 ++-
drivers/gpu/drm/i915/i915_trace.h | 8 ++
3 files changed, 167
goto free_scratch in temp 48-bit mode init code (Akash).
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 38 -
drivers/gpu/drm/i915
),
the used_ptes bitmap may not get updated correctly, but none of the
code-checks rely on this.
Suggested-by: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
: Just kill the limit, it was only there for early detection of an
error when used for execbuffer (Chris).
Cc: Akash Goel akash.g...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 4
gen8_map_pagetable_range removal.
v7: Use generic page name (px) in DECLARE_EVENT_CLASS (Akash)
v8: Defer define of i915_page_directory_pointer_entry_alloc (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v3
value in
execlists_update_context (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 54 +
drivers/gpu/drm/i915
are already allocated (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 86 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 17
.
Michel Thierry (19):
drm/i915: Remove unnecessary gen8_clamp_pd
drm/i915/gen8: Make pdp allocation more dynamic
drm/i915/gen8: Abstract PDP usage
drm/i915/gen8: Add dynamic page trace events
drm/i915/gen8: Add PML4 structure
drm/i915/gen8: implement alloc/free for 4lvl
drm/i915/gen8
Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_debugfs.c | 18
drivers/gpu/drm/i915/i915_gem_gtt.c | 83 +
2 files changed, 93 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm
...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ba41b01..ee19473 100644
limited to 4GB, this change is not required
in i915_gem_obj_ggtt_offset.
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++---
drivers/gpu/drm/i915/i915_gem.c | 12 ++--
drivers/gpu/drm/i915
On 7/8/2015 6:03 PM, Chris Wilson wrote:
On Wed, Jul 08, 2015 at 05:42:17PM +0100, Michel Thierry wrote:
WARN_ON(vma-node.size != obj-base.size) ? Feel free to get the casting
right - I suck at implicit C integer conversion rules ...
-Daniel
Thanks, if there's no objections, I'll change
On 7/11/2015 9:02 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:48PM +0100, Michel Thierry wrote:
Introduces the Page Map Level 4 (PML4), ie. the new top level structure
of the page tables.
To facilitate testing, 48b mode will be available on Broadwell and
GEN9+, when i915.enable_ppgtt
On 7/10/2015 10:39 AM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:45PM +0100, Michel Thierry wrote:
These are the rebased patches, after Mika's final ppgtt clean-up series landed
(it relies in the macros added) and Akash review comments.
In order expand the GPU address space, a 4th
On 7/7/2015 4:15 PM, Michel Thierry wrote:
There are some allocations that must be only referenced by 32-bit
offsets. To limit the chances of having the first 4GB already full,
objects not requiring this workaround use DRM_MM_SEARCH_BELOW/
DRM_MM_CREATE_TOP flags
In specific, any resource used
On 7/7/2015 9:08 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:44:30PM +0100, Michel Thierry wrote:
On 7/7/2015 4:27 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:59PM +0100, Michel Thierry wrote:
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases
On 7/8/2015 4:22 PM, Daniel Vetter wrote:
On Wed, Jul 08, 2015 at 12:22:58PM +0100, Michel Thierry wrote:
On 7/7/2015 9:08 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:44:30PM +0100, Michel Thierry wrote:
On 7/7/2015 4:27 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:59PM +0100
On 7/7/2015 4:27 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:59PM +0100, Michel Thierry wrote:
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases it is important that size is a 64b variable.
Also added a warning for illegal bind with size = 0.
Signed
register.
v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
PDP update in bb_start is only for legacy 32b mode.
v6: Rebase after final merged version of Mika's ppgtt/scratch
patches.
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel
v2: For semaphore errors, object is mapped to GGTT and offset will not
be 4GB, print only lower 32-bits (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 4
.
Suggested-by: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ---
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915
in insert_pte_entries.
v8: Change gen8_ppgtt_clear_pte_range to stop at PDP boundary, instead of
adding and extra clamp function; remove unnecessary pdp_start/pdp_len
variables (Akash).
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c
).
Suggested-by: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 41 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers
Harrison john.c.harri...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91e195a..4a30a73 100644
: Just kill the limit, it was only there for early detection of an
error when used for execbuffer (Chris).
Cc: Akash Goel akash.g...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 4
gen8_map_pagetable_range removal.
v7: Use generic page name (px) in DECLARE_EVENT_CLASS (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v3+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++
drivers/gpu
(v4)
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 2 ++
drivers/gpu/drm/i915/i915_gem.c| 14 --
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 13 +
include/uapi/drm/i915_drm.h| 3 ++-
4
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases it is important that size is a 64b variable.
Also added a warning for illegal bind with size = 0.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 5 +++--
drivers
Introduces the Page Map Level 4 (PML4), ie. the new top level structure
of the page tables.
To facilitate testing, 48b mode will be available on Broadwell and
GEN9+, when i915.enable_ppgtt = 3.
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7a1d6f8..030f688 100644
/scratch
patches.
v12: Fix pdpe start value in trace (Akash)
Cc: Akash Goel akash.g...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 161 ++--
drivers/gpu/drm
and here is no exception.
v2: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
v3: Rebase after final merged version of Mika's ppgtt/scratch patches.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2)
---
drivers/gpu/drm/i915
Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_debugfs.c | 18
drivers/gpu/drm/i915/i915_gem_gtt.c | 83 +
2 files changed, 93 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm
-by: Michel Thierry michel.thie...@intel.com (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 107 +++-
1 file changed, 68 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fa66dfa..c3c2703
Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
Note, aliasing PPGTT remains 32b only.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions
On 7/7/2015 9:33 AM, Chris Wilson wrote:
On Sat, Apr 11, 2015 at 09:41:37AM +0100, Chris Wilson wrote:
Bug reports are still coming in for late 4.0-rcX that indicate that
execlists causes GPU hangs following resume.
Fixes regression from
commit d7f621e50704306c348ccb192f17047f1499f9bc
Author:
On 7/7/2015 1:56 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
v2: Clean up patch after rebases.
v3: gen8_dump_ppgtt for 32b and 48b PPGTT.
v4: Use used_pml4es/pdpes (Akash).
v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
Signed-off-by: Ben Widawsky b
On 7/7/2015 1:36 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
This transitional patch doesn't do much for the existing code. However,
it should make upcoming patches to use the full 48b address space a bit
easier. The patch also introduces the PML4, ie. the new top level
On 7/7/2015 1:51 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
static void
@@ -781,9 +793,9 @@ gen8_ppgtt_insert_pte_entries(struct
i915_address_space *vm,
struct i915_hw_ppgtt *ppgtt =
container_of(vm, struct i915_hw_ppgtt, base);
gen8_pte_t
On 7/7/2015 1:43 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
@@ -795,13 +821,15 @@ static void gen8_ppgtt_cleanup(struct
i915_address_space *vm)
*
* Return: 0 if success; negative error code otherwise.
*/
-static int gen8_ppgtt_alloc_pagetabs(struct
On 7/7/2015 1:48 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
@@ -1087,8 +1137,62 @@ static int gen8_alloc_va_range_4lvl(struct
i915_address_space *vm,
uint64_t start,
uint64_t length)
{
-WARN_ON(1); /* to be implemented
On 7/1/2015 6:06 PM, Emil Velikov wrote:
Hi Michel,
Although I cannot comment on the exact implementation I can give you
general some tips which you might find useful.
Hi Emil,
On 1 July 2015 at 16:28, Michel Thierry michel.thie...@intel.com wrote:
Gen8+ supports 48-bit virtual addresses
On 7/2/2015 8:21 AM, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 04:28:10PM +0100, Michel Thierry wrote:
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.
OUT_BATCH(0);
OUT_BATCH(mocs_wb 16);
/* Surface state
allocate per ppgtt scratch page.
Maybe also say that it moved scratch page/pt/pd operations together
(genx_init/free_scratch functions).
Daniel, since you requested this, should it get yours r-b?
It looks ok to me.
-Michel
Cc: Michel Thierry michel.thie...@intel.com
Cc: Daniel Vetter daniel.vet
On 7/1/2015 3:26 PM, Daniel Vetter wrote:
On Wed, Jul 01, 2015 at 03:05:44PM +0100, Michel Thierry wrote:
On 6/30/2015 4:16 PM, Mika Kuoppala wrote:
Previously we have pointed the page where the individual ppgtt
scratch structures refer to, to be the instance which GGTT setup have
allocated
On 6/30/2015 4:16 PM, Mika Kuoppala wrote:
Every other alloc_* function return the pointer to the page
they alloc. Follow the convention with scratch page also.
Reviewed-by: Michel Thierry michel.thie...@intel.com
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm
On 7/1/2015 4:43 PM, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 04:27:32PM +0100, Michel Thierry wrote:
+ flags |= PIN_ZONE_4G;
+ if (entry-flags EXEC_OBJECT_SUPPORTS_48B_ADDRESS)
+ flags = ~PIN_ZONE_4G;
+
if (!drm_mm_node_allocated(vma-node
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