Re: [Intel-gfx] [PATCH 6/6] drm/i915: Bpp/timeslot calculation fixes for DP MST DSC

Thanks Stan for the explanation, With that Reviewed-by: Manasi Navare Manasi -Original Message- From: Lisovskiy, Stanislav Sent: Tuesday, November 22, 2022 2:40 AM To: Navare, Manasi D Cc: intel-gfx@lists.freedesktop.org; Saarinen, Jani ; Nikula, Jani ; dri-de

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)

, Manasi D Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4) Patch Details Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4) URL: https://patchwork.freedesktop.org/series/98801

Re: [Intel-gfx] [PATCH v2] drm/amd/display: Only define DP 2.0 symbols if not already defined

PM To: Wentland, Harry ; Deucher, Alexander ; amd-...@lists.freedesktop.org Cc: Nikula, Jani ; Li, Sun peng (Leo) ; nat...@kernel.org; intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; ville.syrj...@linux.intel.com; Navare, Manasi D ; Koenig, Christian ; Pan, Xinhui ; s

Re: [Intel-gfx] [v3] drm/i915/dsc: Fix bigjoiner check in dsc_disable

This change takes care of resetting the dss_ctl registers in case of dsc_disable, bigjoiner disable and also uncompressed joiner disable. v2: Fix formatting v3: Fix the typo (Mansi) Suggested-by: Jani Nikula Fixes: d961eb20adb6 (drm/i915/bigjoiner: atomic commit changes for uncompressed

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes

I don’t see how these failures are related to the patch series Manasi From: Patchwork Sent: Wednesday, October 28, 2020 4:31 PM To: Navare, Manasi D Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for series starting with [v3,1/6] drm/i915/dp: Some reshuffling in mode_valid

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: Modeset only the tiled connectors with CRTC

5:47 PM To: Navare, Manasi D Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for drm/i915/dp: Modeset only the tiled connectors with CRTC == Series Details == Series: drm/i915/dp: Modeset only the tiled connectors with CRTC URL : https://patchwork.freedesktop.org/series

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: Disable Port sync mode correctly on teardown

this by itself. Manasi -Original Message- From: Jani Nikula [mailto:jani.nik...@linux.intel.com] Sent: Thursday, December 19, 2019 10:23 PM To: Navare, Manasi D ; intel-gfx@lists.freedesktop.org Cc: Sarvela, Tomi P ; Saarinen, Jani ; Chris Wilson Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: Disable Port sync mode correctly on teardown

This is a gem test failing on BYT for which Port Sync feature in this feature is not even enabled. Looks like a false positive. Manasi -Original Message- From: Patchwork [mailto:patchw...@emeril.freedesktop.org] Sent: Thursday, December 19, 2019 7:13 PM To: Navare, Manasi D Cc: intel

Re: [Intel-gfx] [PATCH] drm/i915/vbt: Assume port A is connected to eDP when there's no VBT

We currently assume port A is connected to a DP sink when VBT is absent, instead assume it is connected to an eDP sink, which seems like a more common configuration. Although I don't have data to back this up, it is still just as valid as asumming port A is not eDP. This reverts to the behavior

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence

Thanks for the review ! Manasi Em Seg, 2017-07-17 às 15:05 -0700, Manasi Navare escreveu: > The condition for setting the Loadgen Select bit of > PORT_TX_DW4 register during DDI Vswing Sequence should be Bit rate <=6 > GHz whereas the existing code checks only Bit Rate < 6GHz. This patch >

Re: [Intel-gfx] [PATCH v4] drm/i915/edp: Add a T12 panel delay quirk to fix DP AUX CH timeouts

On Fri, Jun 30, 2017 at 09:33:48AM -0700, Manasi Navare wrote: > This patch fixes the DP AUX CH timeouts observed during CI IGT tests > thus fixing the CI failures. This is done by adding a quirk for a > particular PCI device that requires the panel power cycle delay (T12) > to be set to 800ms

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add information to missing case.

On Sat, 2017-06-17 at 01:31 -0700, Dhinakaran Pandiyan wrote: > On Friday, June 16, 2017 10:18:28 PM PDT Vivi, Rodrigo wrote: > > On Fri, 2017-06-16 at 21:54 +0000, Navare, Manasi D wrote: > > > > > On Fri, 2017-06-16 at 21:26 +, Vivi, Rodrigo wrote: > > >

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add information to missing case.

On Fri, 2017-06-16 at 21:26 +, Vivi, Rodrigo wrote: > On Fri, 2017-06-16 at 21:21 +, Pandiyan, Dhinakaran wrote: > > On Fri, 2017-06-16 at 14:12 -0700, Manasi Navare wrote: > > > On Fri, Jun 16, 2017 at 08:58:25PM +, Pandiyan, Dhinakaran wrote: > > > > On Fri, 2017-06-16 at 13:20

Re: [Intel-gfx] Power management test in DP compliance suite

On Thu, Jun 08, 2017 at 12:59:23AM +, Navare, Manasi D wrote: > Hi, > > I am executing the DP compliance test suite and the only test > currently failing with the drm-tip + my patch > (https://patchwork.freedesktop.org/series/25191/) > Is the power management test (4.4.3

[Intel-gfx] Power management test in DP compliance suite

Hi, I am executing the DP compliance test suite and the only test currently failing with the drm-tip + my patch (https://patchwork.freedesktop.org/series/25191/) Is the power management test (4.4.3) where it expects the source DUT to go into Power state D3 by setting DPCD register 0x600 to 2

Re: [Intel-gfx] [PATCH v6] drm/i915/dp: Validate cached link rate and lane count before retraining

Thanks Ville for the review and thanks Jani for pushing this patch. Now we are down to 1 patch to get merged! Regards Manasi On Wed, 12 Apr 2017, Ville Syrjälä wrote: > On Thu, Apr 06, 2017 at 02:00:12PM -0700, Manasi Navare wrote: >> Currently

Re: [Intel-gfx] [PATCH v4 09/11] drm/i915/dp: read sink count to a temporary variable first

Thanks Jani for pushing patches 1-9. Now we just need review on Patch 10 (Validate cached link rate and lane count), may Be Ville can review that. I have submitted new revision based on his comments already. And Patch 11 already has your R-b. Regards Manasi On Thu, 06 Apr 2017, Ville Syrjälä

Re: [Intel-gfx] [PATCH v2] drm: Add DPCD definitions for DP 1.4 DSC feature

On Fri, 17 Feb 2017, Manasi Navare wrote: > Display stream compression is supported on DP 1.4 DP devices. This > patch adds the corersponding DPCD register definitions for DSC. > > v2: > * Rebased on drm-tip > > Signed-off-by: Manasi Navare

Re: [Intel-gfx] [i915] monitor is not detected unless it was active during boot

Hi Maarten, Is this the Debug message when you are connected to the external DP Port or the HDMI port? I want to know if the problem is with the native DP connector or LSPCON? Also could you send the log that has the Video Bios Table information (VBT) information? Manasi From: Intel-gfx

Re: [Intel-gfx] [PATCH i-g-t] tools: Add intel_dp_compliance for DisplayPort 1.2 compliance automation

On Fri, Apr 29, 2016 at 06:13:33PM -0700, Manasi Navare wrote: > This is the userspace component of the Displayport Compliance testing > software required for compliance testing of the I915 Display Port > driver. This must be running in order to successfully complete Display > Port compliance

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate

The automated test request for link training needs to start the link training with the requested link rate and lane count. So after reading the TEST LANE COUNT and TEST LINK RATE values, it needs to call intel_dp_start_link_train() also. How is the automated link train being tested currently?