[Intel-gfx] [PATCH] drm/i915/guc: Cancel GuC engine busyness worker synchronously

2022-07-26 Thread Nerlige Ramappa, Umesh
The worker is canceled in gt_park path, but earlier it was assumed that gt_park path cannot sleep and the cancel is asynchronous. This caused a race with suspend flow where the worker runs after suspend and causes an unclaimed register access warning. Cancel the worker synchronously since the

[Intel-gfx] [PATCH 1/2] i915/perf: Replace DRM_DEBUG with driver specific drm_dbg call

2022-07-07 Thread Nerlige Ramappa, Umesh
DRM_DEBUG is not the right debug call to use in i915 OA, replace it with driver specific drm_dbg() call (Matt). Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_perf.c | 151 --- 1 file changed, 100 insertions(+), 51 deletions(-) diff --git

[Intel-gfx] [PATCH 2/2] i915/perf: Disable OA sseu config param for gfx12.50+

2022-07-07 Thread Nerlige Ramappa, Umesh
The global sseu config is applicable only to gen11 platforms where concurrent media, render and OA use cases may cause some subslices to be turned off and hence lose NOA configuration. Ideally we want to return ENODEV for non-gen11 platforms, however, this has shipped with gfx12, so disable only

[Intel-gfx] [PATCH 1/2] i915/perf: Replace DRM_DEBUG with driver specific drm_dbg call

2022-07-07 Thread Nerlige Ramappa, Umesh
DRM_DEBUG is not the right debug call to use in i915 OA, replace it with driver specific drm_dbg() call (Matt). Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_perf.c | 151 --- 1 file changed, 100 insertions(+), 51 deletions(-) diff --git

[Intel-gfx] [PATCH 2/2] i915/perf: Disable OA sseu config param for gfx12.50+

2022-07-07 Thread Nerlige Ramappa, Umesh
The global sseu config is applicable only to gen11 platforms where concurrent media, render and OA use cases may cause some subslices to be turned off and hence lose NOA configuration. Ideally we want to return ENODEV for non-gen11 platforms, however, this has shipped with gfx12, so disable only

[Intel-gfx] [PATCH] i915/perf: Disable OA sseu config param for gfx12.5+

2022-07-07 Thread Nerlige Ramappa, Umesh
The global sseu config is applicable only to gen11 platforms where concurrent media, render and OA use cases may cause some subslices to be turned off and hence lose NOA configuration. Ideally we want to return ENODEV for non-gen11 platforms, however, this has shipped with gfx12, so disable only

[Intel-gfx] [PATCH] i915/perf: Disable OA sseu config param for non-gen11 platforms

2022-07-07 Thread Nerlige Ramappa, Umesh
The global sseu config is applicable only to gen11 platforms where concurrent media, render and OA use cases may cause some subslices to be turned off and hence lose NOA configuration. Return ENODEV for non-gen11 platforms. v2: gfx12 is already shipped with this, disable for gfx12.5+ (Lionel)

[Intel-gfx] [PATCH] i915/perf: Disable OA sseu config param for non-gen11 platforms

2022-07-06 Thread Nerlige Ramappa, Umesh
The global sseu config is applicable only to gen11 platforms where concurrent media, render and OA use cases may cause some subslices to be turned off and hence lose NOA configuration. Return ENODEV for non-gen11 platforms. Signed-off-by: Umesh Nerlige Ramappa ---

[Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend

2022-06-21 Thread Nerlige Ramappa, Umesh
From: Umesh Nerlige Ramappa For execlists backend, current implementation of Wa_22011802037 is to stop the CS before doing a reset of the engine. This WA was further extended to wait for any pending MI FORCE WAKEUPs before issuing a reset. Add the extended steps in the execlist path of reset.

[Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness

2022-06-16 Thread Nerlige Ramappa, Umesh
From: John Harrison GuC provides engine_id and last_switch_in ticks for an active context in the pphwsp. The context image provides a 32 bit total ticks which is the accumulated by the context (a.k.a. context[CTX_TIMESTAMP]). This information is used to calculate the context busyness as follows:

[Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness

2022-06-16 Thread Nerlige Ramappa, Umesh
From: John Harrison GuC provides engine_id and last_switch_in ticks for an active context in the pphwsp. The context image provides a 32 bit total ticks which is the accumulated by the context (a.k.a. context[CTX_TIMESTAMP]). This information is used to calculate the context busyness as follows:

[Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness

2022-06-13 Thread Nerlige Ramappa, Umesh
From: John Harrison GuC provides engine_id and last_switch_in ticks for an active context in the pphwsp. The context image provides a 32 bit total ticks which is the accumulated by the context (a.k.a. context[CTX_TIMESTAMP]). This information is used to calculate the context busyness as follows:

[Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend

2022-06-09 Thread Nerlige Ramappa, Umesh
From: Umesh Nerlige Ramappa For execlists backend, current implementation of Wa_22011802037 is to stop the CS before doing a reset of the engine. This WA was further extended to wait for any pending MI FORCE WAKEUPs before issuing a reset. Add the extended steps in the execlist path of reset.

[Intel-gfx] [PATCH] For execlists backend, current implementation of Wa_22011802037 is to stop the CS before doing a reset of the engine. This WA was further extended to wait for any pending MI FORCE

2022-06-09 Thread Nerlige Ramappa, Umesh
From: Umesh Nerlige Ramappa In addition, extend the WA to gen11. v2: (Tvrtko) - Clarify comments, commit message, fix typos - Use IS_GRAPHICS_VER for gen 11/12 checks v3: (Daneile) - Drop changes to intel_ring_submission since WA does not apply to it - Log an error if MSG IDLE is not defined

[Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend

2022-05-10 Thread Nerlige Ramappa, Umesh
From: Umesh Nerlige Ramappa For execlists backend, current implementation of Wa_22011802037 is to stop the CS before doing a reset of the engine. This WA was further extended to wait for any pending MI FORCE WAKEUPs before issuing a reset. Add the extended steps in the execlist path of reset.