From: Ville Syrjälä
Fix up the SEL_FETCH_{SIZE,OFFSET} registers. A classic
copy-paste fail on my part.
I even had a small test to confirm that the old and new register
offsets match, but somehow I must have screwed things up when
running it, and likely just ended up comparing the old defines
From: Ville Syrjälä
The c8_planes_changed() check in the high level atomic code is
a bit of an eyesore. Push it inside intel_color_check() so the
high level code doesn't have to care about this stuff.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 11
From: Ville Syrjälä
Move the intel_crtc_needs_color_update() into intel_color_check()
so that the caller doesn't have to care about this. This will
also enable us to hide the c8_planes_changed() thing better.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 5
From: Ville Syrjälä
Bunch of stuff in intel_color_check() needs to look at both the
old and new crtc states. Currently we do that by digging the
full atomic state via the crtc_state->state pointer. That thing
is a total footgun if I ever saw one, as it's only valid during
specific parts of the
From: Ville Syrjälä
Eliminate the crtc_state->state footgun from intel_color_check(),
and hide some mundane C8 plane details inside it.
Ville Syrjälä (3):
drm/i915: Plumb the entire atomic state into intel_color_check()
drm/i915: Hide the intel_crtc_needs_color_update() inside
From: Ville Syrjälä
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
v2: Pass the correct register offset fpr pipe B (Jani)
From: Ville Syrjälä
Bspec lists the mas TMDS bitrate as 6 Gbps on ADL-S/ADL-P/DG2.
Bump our limit to match.
v2: Bump for ADL-S as well (Jani)
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
From: Ville Syrjälä
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.
v2: Don't break
From: Ville Syrjälä
Disable eDP DSC usage when instructed to do so by the VBT.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 4
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c| 4
3
From: Ville Syrjälä
No idea what this MST checks is doing in intel_dp_has_audio().
Looks completely pointless, so get rid of it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
From: Ville Syrjälä
intel_dp_supports_dsc() now works for MST as well, reuse it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 20
From: Ville Syrjälä
Reuse intel_dp_has_dsc() during .compute_config() instead of
repeating some of the checks again by hand. We'll be adding
more checks to intel_dp_has_dsc() and this will make sure
we cover both .mode_valid() and .compute_config() with them.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Extract a helper to check whether the source+sink combo
supports DSC. That basic check is needed both during mode
validation and compute config. We'll also need to add extra
checks to both places, so having a single place for it is nicer.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Utilize intel_dp_has_dsc() for MST as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 -
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +--
3 files changed, 6 insertions(+), 3
From: Ville Syrjälä
If we have no dsc_decompression_aux (only possible on MST)
then we won't have the dsc_dpcd caps either. So checking
both is not needed.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 1 -
1 file changed, 1 deletion(-)
diff --git
From: Ville Syrjälä
Respect the VBT's edp_disable_dsc bit, and do a bunch
of refactoring around checking for DSC support.
Also threw in a bonus cleanup to intel_dp_has_audio()
that caught my eye.
Ville Syrjälä (7):
drm/i915: Drop redundant dsc_decompression_aux check
drm/i915: Extract
From: Ville Syrjälä
Bspec lists the mas TMDS bitrate as 6 Gbps on ADL/DG2.
Bump our limit to match.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
From: Ville Syrjälä
Make life easier for drivers by filtering out unwanted YCbCr 4:2:0
only modes prior to calling the connector->mode_valid() hook.
Currently drivers will still see YCbCr 4:2:0 only modes in said
hook, which will likely come as a suprise when the driver has
declared no support
From: Ville Syrjälä
Group the sprite plane register definitions such that everything
to do wiht the same register is in one place.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_sprite_regs.h | 231 ++
1 file changed, 134 insertions(+), 97 deletions(-)
diff
From: Ville Syrjälä
Note which sprite registers are valid for which platforms.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_sprite_regs.h | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
From: Ville Syrjälä
Relocate all pre-skl primary plane register definitions
into their own declutter i915_reg.h.
Cc: Zhenyu Wang
Cc: Zhi Wang
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 1 +
.../gpu/drm/i915/display/i9xx_plane_regs.h| 98
From: Ville Syrjälä
Add some notes indicatign which plane registers/bits are
valid for which platforms.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/i9xx_plane_regs.h| 22 +--
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git
From: Ville Syrjälä
Group the pre-skl primary plane register definitions
sensible, and toss in a few comments to indicate which
platforms have what.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/i9xx_plane_regs.h| 46 ---
1 file changed, 29 insertions(+), 17
From: Ville Syrjälä
PIPEGCMAX was left behind when all other gamma registers moved
into intel_color_regs.h.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color_regs.h | 5 +
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 5 insertions(+), 4
From: Ville Syrjälä
Make a more thorough split between universal planes vs. cursors
by defining the contents of the cursor WM/DDB registers separately.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 34 +++
From: Ville Syrjälä
Instead of that huge _PICK() let's use PICK_EVEN_2RANGES()
for the SEL_FETCH_PLANE registers. A bit more tedious to have
to define 8 raw register offsets for everything, but perhaps
a bit easier to understand since we use a standard mechanism
now instead of hand rolling the
From: Ville Syrjälä
Rename the selective fetch plane registers to match the spec.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 +-
drivers/gpu/drm/i915/display/skl_universal_plane.c | 12 ++--
2 files changed, 11 insertions(+), 11
From: Ville Syrjälä
PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x7 range.
so using _MMIO_TRANS2() for it is not really correct. Also since this
is a pipe register, and not present on CHV, the registers will be
equally spaced out, so we can use the simpler _MMIO_PIPE() instead
From: Ville Syrjälä
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Group the cursor register defines such that everything to
do with one register is in one place.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_cursor_regs.h | 52 +--
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git
From: Ville Syrjälä
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.
Signed-off-by:
From: Ville Syrjälä
Bunch of cleanup mostly around plane registers.
Ville Syrjälä (13):
drm/i915: Add skl+ plane name aliases to enum plane_id
drm/i915: Clean up the cursor register defines
drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
drm/i915: Simplify PIPESRC_ERLY_TPT
From: Ville Syrjälä
I don't think the display hardware really has such chroma
plane tile row alignment requirements as outlined in
commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar
UV plane is tile row size aligned")
Bspec had the same exact thing to say about earlier hardware
as well,
From: Ville Syrjälä
Currently we still use the SKL+ PLANE_SURF alignment even
for TGL+ even though the hardware no longer needs it.
Introduce a separate tgl_plane_min_alignment() and update
it to more accurately reflect the hardware requirements.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Now that all pre-skl platforms have their own .min_alignment()
functions the remainder of intel_surf_alignment() can be hoisted
into skl_univerals_plane.c (and renamed appropriately).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb.c | 77
From: Ville Syrjälä
Extract the necessary chunks from intel_surf_alignment()
into per-platform variants for all pre-skl primary/sprite
planes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 69 -
drivers/gpu/drm/i915/display/intel_fb.c |
From: Ville Syrjälä
Split intel_cursor_alignment() into per-platform variants.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 40 +++--
drivers/gpu/drm/i915/display/intel_fb.c | 16 -
drivers/gpu/drm/i915/display/intel_fb.h | 3
From: Ville Syrjälä
Different planes could have different alignment requirements
even for the same format/modifier. Collect the alignment
requirements across all planes capable of scanning out the
fb such that the alignment used when pinning the normal ggtt
view is satisfactory to all those
From: Ville Syrjälä
Different hardware generations have different scanout alignment
requirements. Introduce a new vfunc that will allow us to
make that distinction without horrible if-ladders.
For now we directly plug in the existing intel_surf_alignment()
and intel_cursor_alignment()
From: Ville Syrjälä
Rename drm_plane_check_pixel_format() to drm_plane_has_format()
and change the return type accordingly. Allows one to write
more natural code.
Also matches drm_any_plane_has_format() better.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c| 7 ++-
From: Ville Syrjälä
Export drm_plane_has_format() so that drivers can use it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_crtc_internal.h | 2 --
drivers/gpu/drm/drm_plane.c | 1 +
include/drm/drm_plane.h | 2 ++
3 files changed, 3 insertions(+), 2 deletions(-)
From: Ville Syrjälä
intel_surf_alignment() in particular has devolved into
a complete mess. Redesign the code so that we can handle
alignment restrictions in a nicer. Also adjust alignment
for TGL+ to actually match the hardware requirements.
Ville Syrjälä (9):
drm: Rename
From: Ville Syrjälä
Currentluy every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and
From: Ville Syrjälä
A few extra tabs have snuck into the skl+ plane register bit
definitions. Remove them.
v2: Rebase
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
From: Ville Syrjälä
A couple of PLANE_WM bits were still using the hand
rolled (1<
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit
v2: Define register contents after all offsets (Jani)
Cc: Jani Nikula
Signed-off-by:
From: Ville Syrjälä
We only need register defines for the first two planes
on the first two pipes. Nuke everything else.
v2: Drop a few more that snuck through
Reviewed-by: Jani Nikula #v1
Signed-off-by: Ville Syrjälä
---
.../i915/display/skl_universal_plane_regs.h | 19
From: Ville Syrjälä
Having the plane WM/DDB regitster write functions in skl_watermarks.c
is rather annoying when trying to implement DSB based plane updates.
Move them into the respective files that handle all other plane
register writes. Less places where I need to worry about the DSB
vs. MMIO
From: Ville Syrjälä
Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
just call intel_de_write_fw() directly.
This is prep work towards DSB based plane updates where these
wrappers are more of a hinderance.
Done with cocci mostly:
@@
expression D, R, L;
@@
- skl_write_wm_level(D,
From: Ville Syrjälä
Extract helpers to calculate the final wm/ddb register
values for skl+. Will allow me to more cleanly remove the
register write wrappers for these registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 29 +---
1 file
From: Ville Syrjälä
Currentluy every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and
From: Ville Syrjälä
A few extra tabs have snuck into the skl+ plane register bit
definitions. Remove them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Ville Syrjälä
A couple of PLANE_WM bits were still using the hand
rolled (1<
---
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
From: Ville Syrjälä
Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit
Signed-off-by: Ville Syrjälä
---
.../i915/display/skl_universal_plane_regs.h | 502
From: Ville Syrjälä
We only need register defines for the first two planes
on the first two pipes. Nuke everything else.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/skl_universal_plane_regs.h | 12
1 file changed, 12 deletions(-)
diff --git
From: Ville Syrjälä
Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane
and just use the real thing.
Cc: Zhenyu Wang
CC: Zhi Wang
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff
From: Ville Syrjälä
Stop hand rolling PLANE_KEY*() register defines and just
use the real thing.
Cc: Zhenyu Wang
CC: Zhi Wang
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git
From: Ville Syrjälä
Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing.
Cc: Zhenyu Wang
CC: Zhi Wang
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gvt/handlers.c | 24 ++---
drivers/gpu/drm/i915/gvt/reg.h | 2 --
From: Ville Syrjälä
Stop hand rolling PLANE_AUX_DIST() and just use the real thing.
Cc: Zhenyu Wang
CC: Zhi Wang
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gvt/handlers.c | 24 ++---
drivers/gpu/drm/i915/gvt/reg.h | 1 -
From: Ville Syrjälä
On SKL+ the watermark/DDB registers are proper per-plane
registers. Move the definitons to their respective files.
Cc: Zhenyu Wang
CC: Zhi Wang
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_cursor_regs.h | 20 +
From: Ville Syrjälä
Move most cursor register definitions into their own file.
Declutters i915_reg.h a bit more.
Cc: Zhenyu Wang
CC: Zhi Wang
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 1 +
.../gpu/drm/i915/display/intel_cursor_regs.h | 78
From: Ville Syrjälä
Move most of the SKL+ universal plane register definitions
into their own file. Declutters i915_reg.h a bit more.
Cc: Zhenyu Wang
CC: Zhi Wang
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
From: Ville Syrjälä
_MMIO_PLANE_GAMC() is some leftover macro that is never used.
Get rid of it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
From: Ville Syrjälä
Bunch of refactoring around skl+ plane registers.
Ville Syrjälä (16):
drm/i915: Nuke _MMIO_PLANE_GAMC()
drm/i915: Extract skl_universal_plane_regs.h
drm/i915: Extract intel_cursor_regs.h
drm/i915: Move skl+ wm/ddb registers to proper headers
drm/i915/gvt: Use the
From: Ville Syrjälä
We use a mix of 'intel_fb' vs. 'ifbdev->fb' in the same function.
Both should be pointing at the same thing. Make things less
confusing by just getting existing fb from 'ifbdev->fb' at the
start and then sticking with the local 'fb' (renamed from the
'intel_fb') until the
From: Ville Syrjälä
Change intel_fbdev_fb_alloc() to return struct intel_fb instead
of struct drm_framebuffer. Let's us eliminate some annoying
aliasing variables in the fbdev setup code.
v2: Assing the results to the correct variable (Jani)
Fix xe's copy
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
For some reason xe and i915 each have an identical (fortunately)
copy of intel_fbdev_fb.h. The xe copy actually only gets included
by xe's intel_fbdev_fb.c, and the i915 copy by everyone else,
include intel_fbdev.c which is the actual caller of the
functions declared in the
From: Ville Syrjälä
Rename the fb pinning functions such that their name directly
informs us what gets pinned into which address space.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpt.c | 6 +--
drivers/gpu/drm/i915/display/intel_dpt.h | 6 +--
From: Ville Syrjälä
We use a mix of 'fb' vs. 'ifbdev->fb' in the same function.
Both should be pointing at the same thing. Make things less
confusing by just getting existing fb from 'ifbdev->fb' at the
start and then sticking with the local 'fb' until the very end.
And we'll also change
From: Ville Syrjälä
Change intel_fbdev_fb_alloc() to return struct intel_fb instead
of struct drm_framebuffer. Let's us eliminate some annoying
aliasing variables in the fbdev setup code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbdev.c| 10 +-
From: Ville Syrjälä
Make the 'fb' pointers const in the pinning code. We never
want to mutate these. Also nuke a few aliasing fb vs. intel_fb
cases by just using the more specific type everywhere in the
same function.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Be a bit more consistent in our use of integer types in
the fb related calculatiosn. u32 we generally only use
for ggtt offsets and such, and everything else can be regular
(unsigned) ints.
There's also an overabundance of consts for local variables
in
From: Ville Syrjälä
Pull the "does this plane need a physical address?" check into
a small helper.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8
drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 +
From: Ville Syrjälä
Fence regions are only relevant for GGTT, not DPT. Drop the
pointless 'uses_fence' argument from intel_pin_fb_obj_dpt().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
From: Ville Syrjälä
skl_plane_max_stride() is pretty messy. Streamline it and
split it into clear skl+ vs. adl+ variants.
TODO: Deal with icl and tgl strude limits properly
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/skl_universal_plane.c| 65 +++
1 file
From: Ville Syrjälä
Plane .max_stride() is alreayd a vfunc so having one made
up of two branches based on the display version is silly.
Split i9xx_plane_max_stride() into gen2 vs. gen3 variants
so that we get rid of said check.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
A bit of cleanup/refactoring around plane fb stuff.
This is mainly prep work for a slightly bigger rework
of alignment handling.
Ville Syrjälä (9):
drm/i915: Split gen2 vs. gen3 .max_stride()
drm/i915: Clean up skl+ plane stride limits
drm/i915: Drop 'uses_fence'
From: Ville Syrjälä
Define the contents of VBT block 253 (PRD Table).
Unfortunately the block has two definitions, with the cutoff
supposedly happening on ICL vs. TGL. Also according to some
notes it might be that the VBIOS (if that's still a thing)
still uses the old definition even on TGL+.
From: Ville Syrjälä
Declare that VBT block 252 is the "int15 hook". This is some
VBIOS only juju so don't bother with a full definition.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Ville Syrjälä
Define the contents of the obsolete VBT block 55 (Compression
Parameters).
This was some early attempt at defining the compression
parameters. However the spec says:
"This block is obsolete and should not be consumed for any
compression programming."
Block 56 is the
From: Ville Syrjälä
Define the contents of VBT block 50 (MIPI).
This was some easly attempt at a MIPI DSI stuff. I'm not sure
this was ever actually used (I certainly don't have any VBTs
with this block), but here's some kind of definition for it
anyway.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Define the contents of VBT block 57 (Vswing PreEmphasis Table).
The contents is highly platform specific. The columns of the
table corresponding to some set of PHY/etc registers. The rows
corresponding to all legal vswing+pre-emphasis combinations
(ie. should be 10 rows in
From: Ville Syrjälä
Define the contents of VBT block 55 (RGB Palette Table).
Note that I've not actually seen any real world VBTs with this
block.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12
1 file changed, 12 insertions(+)
diff --git
From: Ville Syrjälä
Define the contents of VBT block 51 (Fixed Set Mode Table).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
From: Ville Syrjälä
Define the contents of VBT block 46 (Chromaticity For Narrow Gamut
Panel). One entry per panel.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 26 +++
1 file changed, 26 insertions(+)
diff --git
From: Ville Syrjälä
Define the contents of VBT block 45 (eDP BFI).
Note that I've not actually seen any real world VBTs with this
block.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 17 +
1 file changed, 17 insertions(+)
diff --git
From: Ville Syrjälä
Define the contents of VBT block 28 (EFP DTD).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
From: Ville Syrjälä
Define the contents of VBT block 26 (TV Options).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
From: Ville Syrjälä
Define the contents of VBT block 25 (SDVO LVDS PPS).
Not 100% sure about the order of the fields as this is not
documented in the VBT spec anymore, but this order matches
what is included as part of the power sequencing SDVO commands
(struct sdvo_panel_power_sequencing).
From: Ville Syrjälä
Define the contents of VBT block 24 (SDVO LVDS PnP ID).
The descriotion is not part of the VBT spec anymore, but the layout
is rather obsvious.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8
1 file changed, 8 insertions(+)
From: Ville Syrjälä
Define the contents of VBT block 21 (EFP List). Specs are nowhere
to be found, but real world data suggests that each entry is just
the first four bytes of the EDID PnP ID structure.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 15
From: Ville Syrjälä
Define the contents of VBT block 20 (OEM Customizable Modes).
Each entry is either 26 or 28 bytes, depending on the BDB version.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 24 +++
1 file changed, 24 insertions(+)
diff
From: Ville Syrjälä
Define the contenst is VBT blocks 19,30,32 (Display Configuration
Removal Table) contents. There are three variants of this block:
pre-IVB, IVB, HSW+, with each having slightly different entries.
Curiously many HSW/BDW machines seem to have both the IVB and HSW+
variants in
From: Ville Syrjälä
Define the contenst is VBT blocks 16,19,31 (Toggle List).
There are three variants of this block: pre-IVB, IVB, HSW+,
with each having slightly different entries.
Curiously many HSW/BDW machines seem to have both the IVB and
HSW+ variants in their VBTs simultanously. No idea
From: Ville Syrjälä
For some reason ALM VBT has two dot clock override tables.
One as the normal block 15 and a second one as block 9.
The table in block 9 has no row_size/num_rows information.
On my Fujitsu Lifebook S6010 only the block 9 table has actual
data in it. Block 15 is present but
From: Ville Syrjälä
Define the contents of block 18 (Driver Rotation).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
From: Ville Syrjälä
Define the contents of VBT block 17 (SV Test Functions).
Nothing real here for us, but might as well define it for
completeness.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 9 +
1 file changed, 9 insertions(+)
diff --git
From: Ville Syrjälä
Define the contents of VBT block 15 (Dot Clock Override Table)
The contents were reverse engineered by intuition. The gen2 stuff
seems solid as I can verify that against real world VBT data. The
gen3 stuff less so as all the gen3+ VBTs I have just filla the
entire block with
From: Ville Syrjälä
Define the contents of VBT block 12 (Driver Persistent Algorithm).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
From: Ville Syrjälä
Define the contents of VBT block 10 (Mode Removal Table).
There seem to be two variants:
- 8 byte entries for desktop systems
- 10 byte entries for mobile systems, with the extra
panel_flags being a bitmask of LFPs
It seems starting from HSW only the mobile variant is
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