From: Ville Syrjälä
Move skl_get_pfit_config() next to the other skl+ scaler code
and rename it to skl_scaler_get_config() so that it has a consistnet
namespace.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 49 ++--
From: Ville Syrjälä
Pimp the skl+ scaler register bits with REG_BIT()/etc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 98 ++---
1 file changed, 53 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
To avoid annoying spec lookups let's define more PS_CTRL
bits in the header.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Define and use the bitmasks for the x/y components
of the ilk+ panel filter window pos/size registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 12
drivers/gpu/drm/i915/i915_reg.h | 8
2 files
From: Ville Syrjälä
Fix a typo in the PS_COEF_INDEX_AUTO_INC define.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Rename the scaler binding bits to match the spec more closely.
Also call the parameters 'plane_id' to make it a bit more clear
what to pass in.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 12 ++--
drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Define and use the bitmasks for the x/y components
of the skl+ scaler window pos/size registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 14 --
drivers/gpu/drm/i915/i915_reg.h | 8
2 files changed, 16
From: Ville Syrjälä
ilk_pfit_enable() is defined before the first use. No need
for a forwared declaration.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
Polish the ilk+ pfit registers with REG_BIT() & co., and
also take the opportunity to unify the ivb/hsw vs. not checks
in ilk_pfit_enable() and ilk_get_pfit_config().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
From: Ville Syrjälä
We have some duplicated scaler register defines that are
never used. Remove them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Move intel_atomic_setup_scalers() next to the other scaler
code in skl_scaler.c.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 256 ---
drivers/gpu/drm/i915/display/intel_atomic.h | 4 -
From: Ville Syrjälä
Modernize the gmch pfit register definitions using REG_BIT/etc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++---
drivers/gpu/drm/i915/display/intel_overlay.c | 16 +++---
drivers/gpu/drm/i915/display/intel_panel.c | 8 +--
From: Ville Syrjälä
Give the PFIT_CONTROL bits a consistent namespace.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_lvds.c| 2 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_panel.c | 25 ++--
From: Ville Syrjälä
The skl+ scalers only sample 12 bits of PIPESRC so we can't
do any plane scaling at all when the pipe source size is >4k.
Make sure the pipe source size is also below the scaler's src
size limits. Might not be 100% accurate, but should at least be
safe. We can refine the
From: Ville Syrjälä
Move the VBLANK_EVASION_TIME_US definition to a slightly
better place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.h| 10 ++
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
From: Ville Syrjälä
One scaler bugfix, and a bunch of scaler/pfit cleanups/etc.
Ville Syrjälä (15):
drm/i915: Check pipe source size when using skl+ scalers
drm/i915: Relocate VBLANK_EVASION_TIME_US
drm/i915: Relocate intel_atomic_setup_scalers()
drm/i915: Relocate skl_get_pfit_config()
From: Ville Syrjälä
Replace the hardcoded masks with just a loop over all hpd
pins using the _hotplug_mask() functions.
v2: Deal with mtp
Reviewed-by: Vinod Govindapillai a #v1
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 65 -
1 file
From: Ville Syrjälä
We need to untangle the mess where some SKL machines (at least)
declare both DDI A and DDI E to be present in their VBT, and
both using AUX A. DDI A is a ghost eDP, wheres DDI E may be a
real DP->VGA converter.
Currently that is handled by checking the VBT child devices
for
From: Ville Syrjälä
Add a mechanism by which we can enable the HPD sense for
individual encoders.
This will be used during eDP probing to figure out if
anything is actually connected. The normal intel_hpd_irq_setup()
thing doesn't work since we only do that after probing the
outputs, and we
From: Ville Syrjälä
Pair each _hotplug_enables() function with
a corresponding _hotplug_mask() function so that
we can determine right bits to clear on a per hpd_pin basis.
We'll need this for turning on HPD sense for a specific
encoder rather than just all of them.
v2: Drop the unused 'i915'
From: Ville Syrjälä
Remainder of the eDP HPD check series, now rebased on top
of MTL HPD stuff.
Ville Syrjälä (4):
drm/i915: Introduce _hotplug_mask()
drm/i915: Introduce intel_hpd_enable_detection()
drm/i915: Check HPD live state during eDP probe
drm/i915: Reuse _hotplug_mask() in
From: Ville Syrjälä
intel_{mpllb,c10pll}_state_verify() blows up if you call them
for a non-modeset/fastset commit on account of the relevant
connector not being part of the overall atomic state.
Currently the state checker only runs for modeset/fastset
commits, but for testing purposes it is
From: Ville Syrjälä
The point of the WARN was to print something, not oops
straight up. Currently that is precisely what happens
if we can't find the connector for the crtc in the atomic
state. Get the dev pointer from the atomic state instead
of the potentially NULL encoder to avoid that.
From: Ville Syrjälä
intel_mpllb_state_verify() blows up if you call it for a
non-modeset/fastset commit on account of the relevant
connector not being part of the overall atomic state.
Currently the state checker only runs for modeset/fastset
commits, but for testing purposes it is sometimes
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening.
From: Ville Syrjälä
VLV has a so called "wide gamut color correction" unit (WGC).
What it is is a 3x3 matrix similar to the later CHV CGM
CSC, which less precisions/range. In fact CHV also has the WGC
but using it there doesn't reall make sense when you have the
superior CGM CSC around.
Hook up
From: Ville Syrjälä
The CHV CGM CSC coefficients are in s4.12 two's complement
format. Fix the CTM->CGM conversion to handle that correctly
instead of pretending that the hw coefficients are also
in some sign-magnitude format.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
On CHV toggling the CGM CSC on/off while the pipe is running leads
to underruns. Looks like we'd have to do the toggling strictly inside
the start_of_vblank-frame_start window to avoid this, but that window
is less than a scanline so there's no way we can guarantee hitting
From: Ville Syrjälä
Apparently desktop gen3 parts don't support the
10bit gamma mode at all. Stop claiming otherwise.
As is the case with pipe A on gen3 mobile parts, the
PIPECONF gamma mode bit can be set but it has no
effect on the output.
PNV seems to be the only slight exception, but
From: Ville Syrjälä
Document in which order the CTM matrix elements are stored.
Signed-off-by: Ville Syrjälä
---
include/uapi/drm/drm_mode.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 46becedf5b2f..43691058d28f
From: Ville Syrjälä
The ilk/snb code is internally fully capable of handling the
CTM property, so expose it.
Note that we still choose not to expose DEGAMMA_LUT though.
The hardware is capable if degamma or gamma, but not both
similtanously due to lack of the split gamma mode. Exposing
both
From: Ville Syrjälä
Mostly some CTM stuff:
- document the uapi better
- fix CHV CSC negative coefficients
- expose CTM on ilk/snb/vlv
- a bonus gamma patch for gen3
- cure CGM CSC underruns on CHV (new in v2)
Test-with: 20230411161555.10001-1-ville.syrj...@linux.intel.com
Ville Syrjälä (7):
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening.
From: Ville Syrjälä
The CHV CGM CSC coefficients are in s4.12 two's complement
format. Fix the CTM->CGM conversion to handle that correctly
instead of pretending that the hw coefficients are also
in some sign-magnitude format.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Apparently desktop gen3 parts don't support the
10bit gamma mode at all. Stop claiming otherwise.
As is the case with pipe A on gen3 mobile parts, the
PIPECONF gamma mode bit can be set but it has no
effect on the output.
PNV seems to be the only slight exception, but
From: Ville Syrjälä
VLV has a so called "wide gamut color correction" unit (WGC).
What it is is a 3x3 matrix similar to the later CHV CGM
CSC, which less precisions/range. In fact CHV also has the WGC
but using it there doesn't reall make sense when you have the
superior CGM CSC around.
Hook up
From: Ville Syrjälä
The ilk/snb code is internally fully capable of handling the
CTM property, so expose it.
Note that we still choose not to expose DEGAMMA_LUT though.
The hardware is capable if degamma or gamma, but not both
similtanously due to lack of the split gamma mode. Exposing
both
From: Ville Syrjälä
Document in which order the CTM matrix elements are stored.
Signed-off-by: Ville Syrjälä
---
include/uapi/drm/drm_mode.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 46becedf5b2f..43691058d28f
From: Ville Syrjälä
Mostly some CTM stuff:
- document the uapi better
- fix CHV CSC negative coefficients
- expose CTM on ilk/snb/vlv
- a bonus gamma patch for gen3
Test-with: 20230411161555.10001-1-ville.syrj...@linux.intel.com
Ville Syrjälä (6):
drm/uapi: Document CTM matrix better
From: Ville Syrjälä
Reduce the 'intel_dp' stuff a bit by introducing local
cpu_transcoder variables.
Ideally I'd like the whole PSR code to stop using intel_dp
except during a full modeset, but dunno yet if that's
possible. But the less 'intel_dp' we have sprad around
the easier that should be
From: Ville Syrjälä
The fact that DC states reset the PSR perofrmance counter
is no reason not to include it in the debug output.
But let's keep the comment there to remind people about
that caveat.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 10 --
1
From: Ville Syrjälä
Modernize a bunch of display chicken registers by using
REG_BIT() & co.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 114 +---
1 file changed, 59 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
We need to disable PSR when we are doing AUX by hand, otherwise
it's possible that the PSR hardware could be using the AUX CH
while we try to do our manual stuff. Add a FIXME for now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 5 +
1
From: Ville Syrjälä
Replace some hand rolled RMW stuff with intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 32 ++--
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
From: Ville Syrjälä
Define more of the PSR mask bits, and describe in detail
what some of them do. Even if we don't set them all from
the driver they can be very useful during PSR debugging.
Having to trawl through bspec every time to find them is
not fun, and re-reverse engineering the
From: Ville Syrjälä
Use REG_BIT() & co. to make the PSR register definitions
nicer.
v2: Rebase due to intel_psr_regs.h
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 34 ++-
drivers/gpu/drm/i915/display/intel_psr_regs.h | 197 +-
2 files
From: Ville Syrjälä
Fix a bunch of whitespace issues in some display register
definitons. Only touching the bits alerayd using REG_BIT() &
co. here. The rest will come later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 70 -
1 file
From: Ville Syrjälä
Some cleanups around mostly PSR/related registers.
v2: Improve the mask bit docs and rebase due to
intel_psr_regs.h
Ville Syrjälä (8):
drm/i915: Fix up whitespace in some display chicken registers
drm/i915: Clean up various display chicken registers
drm/i915/psr:
From: Ville Syrjälä
Most places in the vblank code use min() to clamp scanline
counters below vtotal. But we missed one in the gen3/4
pixel counter based codepath.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 3 +--
1 file changed, 1 insertion(+), 2
From: Ville Syrjälä
The transcoder M/N values are double buffered on the transcoder's
undelayed vblank. So when doing seamless M/N fastsets we need to
evade also that.
Not that currently the pipe's delayed vblank == transcoder's
undelayed vblank, so this is still a nop change. But in the
future
From: Ville Syrjälä
If the panel supports VRR it must be capable of accepting
timings with arbitrary vblank length, within the valid VRR
range. Use that fact to allow the user to request any refresh
rate they like. We simply pick the next highest fixed mode
from our list, and adjust the vblank
From: Ville Syrjälä
Include the device and connector information in the SCDC
debugs. Makes it easier to figure out who did what.
v2: Rely on connector->ddc (Maxime)
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Robert Foss
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Thierry
From: Ville Syrjälä
Define CUR_CHICKEN so we don't have to remember the offset.
Looks like it's getting introduced in mtl.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Add tgl+ comments to the PLANE_CHICKEN registers which
I apparently forgot to add when defining the registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Cursor is not a universal plane and thus doesn't have the
PLANE_CHICKEN register. Skip it.
Fixes: c5de248484af ("drm/i915/dpt: Add a modparam to disable DPT via the
chicken bit")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpt.c | 6 +-
1 file
From: Ville Syrjälä
Replace the hardcoded final numbers in the AUX SYNC/precharge
setup, and derive those from numbers from the (e)DP specs.
The new functions can serve as the single point of truth for
the number of SYNC pulses we use.
Cc: Jouni Högander
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Fast wake should use 8 SYNC pulses for the preamble
and 10-16 SYNC pulses for the precharge. Recuce our
fast wake SYNC count to match the maximum value.
We also use the maximum precharge length for normal
AUX transactions.
Cc: Jouni Högander
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä
Include the device and connector information in the SCDC
debugs. Makes it easier to figure out who did what.
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Robert Foss
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Thierry Reding
Cc: Emma Anholt
Cc: Maxime
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening.
From: Ville Syrjälä
Include the csc matrices in the state dump. The format being
hardware specific we just dump as hex for now. Might have
to think of some way to get a bit more human readable
output...
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_crtc_state_dump.c | 43
From: Ville Syrjälä
Read out the csc matrix on chv, and stash the result into the
correct spot in the crtc state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 36 ++
1 file changed, 36 insertions(+)
diff --git
From: Ville Syrjälä
Have the state checker validate that the csc matrices
look correct when read back from the hardware.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 21
1 file changed, 21 insertions(+)
diff --git
From: Ville Syrjälä
Make sure the csc enable bit(s) match the way we're about to
fill the csc matrices.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 22 ++
1 file changed, 22 insertions(+)
diff --git
From: Ville Syrjälä
Read out the pipe/output csc matrices on ilk+ and stash the results
(in the hardware specific format) into the appropriate place
in the crtc state.
Note that on skl/glk/icl the pipe csc unit suffers from an issue
where *reads* of the coefficient/offset registers also disarm
From: Ville Syrjälä
Store the chv cgm csc matrix in the crtc state as well. We
shall store it in the same place where we store the ilk+
pipe csc matrix (as opposed to the output csc matrix).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 35
From: Ville Syrjälä
Embed a pair of intel_csc_matrix structs in the crtc state,
and fill them out appropriately during atomic_check().
Since pre-ivb platforms don't have programmable post offsets
we shall leave those zeroed, mainly in preparation for
state readout+check.
Signed-off-by: Ville
From: Ville Syrjälä
Convert chv_cgm_csc_convert_ctm() over to using the nee
intel_csc_matrix structure. No pre/post offsets on this
hardware so only the coefficients get filled out.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 24 +++---
1 file
From: Ville Syrjälä
Introduce a structure that can hold our CSC matrices. In there
we shall have the preoffsets, postoffsets, and coefficients,
all in platform specific format (at least for now).
We shall start by converting the ilk+ code to make use of
the new structure. chv will come later.
From: Ville Syrjälä
Split chv_cgm_csc_convert_ctm() out from chv_load_cgm_csc() so
that we have functions with clear jobs. This is also how the ilk+
code is already structured.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 19 +--
1 file
From: Ville Syrjälä
Our current limited range matrix is a bit off. I think it
was originally calculated with rounding, as if we wanted
the normal pixel replication type of behaviour.
That is, since the 8bpc max value is 0xeb we assumed the
16bpc max value should be 0xebeb, but what the HDMI spec
From: Ville Syrjälä
Implement state readout/check for the various CSC units
we utilize.
Ville Syrjälä (12):
drm/i915: Fix limited range csc matrix
drm/i915: Introduce intel_csc_matrix struct
drm/i915: Split chv_load_cgm_csc() into pieces
drm/i915: Start using struct intel_csc_matrix for
From: Ville Syrjälä
Only the PWM output mode of the utility pin is incompatible
with DC6/LCPLL disable. Check for that specifically.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/6609
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6
From: Ville Syrjälä
If we have to force the hardware to go through a full modeset
due to eg. cdclk reprogramming, we need to preserve
crtc_state->inherited for all crtcs that have not otherwise
gone through the whole compute_config() stuff after connectors
have been detected.
Otherwise eg.
From: Ville Syrjälä
The fact that DC states reset the PSR perofrmance counter
is no reason not to include it in the debug output.
But let's keep the comment there to remind people about
that caveat.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 10 --
1
From: Ville Syrjälä
Reduce the 'intel_dp' stuff a bit by introducing local
cpu_transcoder variables.
Ideally I'd like the whole PSR code to stop using intel_dp
except during a full modeset, but dunno yet if that's
possible. But the less 'intel_dp' we have sprad around
the easier that should be
From: Ville Syrjälä
We need to disable PSR when we are doing AUX by hand, otherwise
it's possible that the PSR hardware could be using the AUX CH
while we try to do our manual stuff. Add a FIXME for now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 5 +
1
From: Ville Syrjälä
Define more of the PSR mask bits, and describe in detail
what some of them do. Even if we don't set them all from
the driver they can be very useful during PSR debugging.
Having to trawl through bspec every time to find them is
not fun, and re-reverse engineering the
From: Ville Syrjälä
Use REG_BIT() & co. to make the PSR register definitions
nicer.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 34 ++--
drivers/gpu/drm/i915/i915_reg.h | 197 ---
2 files changed, 116 insertions(+), 115
From: Ville Syrjälä
Replace some hand rolled RMW stuff with intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 32 ++--
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
From: Ville Syrjälä
Modernize a bunch of display chicken registers by using
REG_BIT() & co.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 106 +---
1 file changed, 55 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Fix a binch of whitespace issues in some display register
definitons. Only touching the bits alerayd using REG_BIT() &
co. here. The rest will come later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 70 -
1 file
From: Ville Syrjälä
Some cleanups around mostly PSR/related registers.
Ville Syrjälä (8):
drm/i915: Fix up whitespace in some display chicken registers
drm/i915: Clean up various display chicken registers
drm/i915/psr: Clean up PSR register defininitions
drm/i915/psr: Use intel_de_rmw()
From: Ville Syrjälä
Similar to FBC let's expose an debugfs file to control
IPS false color. Enabling this provides an immediate visual
feedback on whether IPS is working or not.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/hsw_ips.c| 58 ++-
From: Ville Syrjälä
IPS is a per-pipe feature, so let's move the debugfs stuff
under the crtc directory, and only register it when IPS
is actually available.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/hsw_ips.c| 15 +++
From: Ville Syrjälä
Currently we have no sane way to forcibly disable SAGV, which
makes debugging things a PITA. Manually poking at the pcode
mailbox with it's various SAGV/QGV/PSF formats is no fun,
and likely to be clobbered by the driver anyway.
Let's add a modparam for this.
Signed-off-by:
From: Ville Syrjälä
Advertize more suitable cursor sizes via the new SIZE_HINTS
plane property.
Here are some examples on various platforms:
ivb+:
31 SIZE_HINTS:
flags: immutable blob
blobs:
value:
From: Ville Syrjälä
Add a new immutable plane property by which a plane can advertise
a handful of recommended plane sizes. This would be mostly exposed
by cursor planes as a slightly more capable replacement for
the DRM_CAP_CURSOR_WIDTH/HEIGHT caps, which can only declare
a one size fits all
From: Ville Syrjälä
Tweak the parameters we pass to the cursor size_ok() functions
in preparation for using them to populate the SIZE_HINT property.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 63 +++--
1 file changed, 32 insertions(+), 31
From: Ville Syrjälä
I was pondering how I'd be able to do non-square cursor
sizes without have a massive list of them in the SIZE_HINTS
blob.
So I came up with this idea of having a 2D bitmap in
there to indicate support for (mostly) POT non-square
sizes..
What does everyone think? Is this
From: Ville Syrjälä
Move VRR enabling/disabling into a place where it also works
for fastsets.
With this we always start the transcoder up in non-VRR mode.
Granted we already did that but for a very short period of
time. But now that we might end up doing a bit more with the
transcoder in
From: Ville Syrjälä
Now that VRR enable/disable are called from convenient places
it is trivial to allow it to change state during fastsets.
Make it so.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7542
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
Move VRR enabling/disabling into a place where it also works
for fastsets.
With this we always start the transcoder up in non-VRR mode.
Granted we already did that but for a very short period of
time. But now that we might end up doing a bit more with the
transcoder in
From: Ville Syrjälä
In order to move VRR enable/disable to a place where it's also
applicable to fastsets we need to be prepared to configure
the pipe into non-VRR mode initially, and then later switch
to VRR mode. To that end allow the active timings to be configured
in non-VRR mode temporarily
From: Ville Syrjälä
On adl/dg2 a chicken bit needs to be set for TRANS_SET_CONTENXT_LATENCY
to take effect in VRR mode. Can't really think of a reason why we'd
ever disable that chicken bit, so let's just always set it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vrr.c
From: Ville Syrjälä
I want to use the same logic that planes_{enabling,disabling}()
are using for other features as well. Generlize the thing
into a pair of macros.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 16
1 file changed, 12
From: Ville Syrjälä
Some of the VRR functions take redundant arguments. Get rid
of them to make life simpler.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_vrr.c
From: Ville Syrjälä
People would prefer to be able to enable/disable VRR without
a full modeset. Make it so.
Ville Syrjälä (6):
drm/i915: Generalize planes_{enabling,disabling}()
drm/i915/vrr: Eliminate redundant function arguments
drm/i915/vrr: Make delayed vblank operational in VRR mode
From: Ville Syrjälä
Keeping DC states enabled is incompatible with the _noarm()/_arm()
split we use for writing pipe/plane registers. When DC5 and PSR
are enabled, all pipe/plane registers effectively become self-arming
on account of DC5 exit arming the update, and PSR exit latching it.
What
From: Ville Syrjälä
Define more of the PSR mask bits. Even if we don't set them
from the driver they can be very useful during PSR debugging.
Having to trawl through bspec every time to find them is
not fun.
The particularly interesting bits are:
-
From: Ville Syrjälä
Keeping DC states enabled is incompatible with the _noarm()/_arm()
split we use for writing pipe/plane registers. When DC5 and PSR
are enabled, all pipe/plane registers effectively become self-arming
on account of DC5 exit arming the update, and PSR exit latching it.
What
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