[Intel-gfx] [PATCH v3 0/8] i915 pvmmio to improve GVTg performance

conflict with recnet i915 change and take time to rework. Xiaolin Zhang (8): drm/i915: introduced pv capability for vgpu drm/i915: get ready of memory for pvmmio drm/i915: context submission pvmmio optimization drm/i915: ppgtt update pvmmio optimization drm/i915/gvt: GVTg handle pvmmio_caps

[Intel-gfx] [PATCH v3 3/8] drm/i915: context submission pvmmio optimization

c: Zhenyu Wang Cc: Zhi Wang Cc: Chris Wilson Cc: Joonas Lahtinen Cc: He Min Cc: Jiang Fei Cc: Gong Zhipeng Cc: Yuan Hang Cc: Zhiyuan Lv Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_pvinfo.h | 1 + drivers/gpu/drm/i915/i915_vgpu.c| 2 ++ drivers/gpu/drm/

[Intel-gfx] [PATCH v3 6/8] drm/i915/gvt: GVTg handle shared_page setup

zero memory and handle VGT_G2V_SHARED_PAGE_SETUP g2v notification Cc: Zhenyu Wang Cc: Zhi Wang Cc: Min He Cc: Fei Jiang Cc: Zhipeng Gong Cc: Hang Yuan Cc: Zhiyuan Lv Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/gvt.h | 5 - drivers/gpu/drm/i915/gvt/handlers.c | 39

[Intel-gfx] [PATCH v3 4/8] drm/i915: ppgtt update pvmmio optimization

Cc: Joonas Lahtinen Cc: He Min Cc: Jiang Fei Cc: Gong Zhipeng Cc: Yuan Hang Cc: Zhiyuan Lv Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_gem.c | 3 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 67 + drivers/gpu/drm/i915/i915_pvinfo.h | 3

[Intel-gfx] [PATCH v2 3/5] drm/i915: context submission pvmmio optimization

orts and preempt_context implemented. Cc: Zhenyu Wang Cc: Zhi Wang Cc: Chris Wilson Cc: Joonas Lahtinen Cc: He, Min Cc: Jiang, Fei Cc: Gong, Zhipeng Cc: Yuan, Hang Cc: Zhiyuan Lv Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_vgpu.c| 2 + drivers/gpu/drm/i915/intel_lrc.c

[Intel-gfx] [PATCH v2 0/5] i915 pvmmio to improve GVTg performance

: RFC patch set v1: addressed RFC review comments v2: addressed v1 review comments, added pv callbacks for pv operations Xiaolin Zhang (5): drm/i915: introduced pv capability for vgpu drm/i915: get ready of memory for pvmmio drm/i915: context submission pvmmio optimization drm/i915: master irq

[Intel-gfx] [PATCH v2 4/5] drm/i915: master irq pvmmio optimization

: Jiang, Fei Cc: Gong, Zhipeng Cc: Yuan, Hang Cc: Zhiyuan Lv Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_irq.c| 82 -- drivers/gpu/drm/i915/i915_pvinfo.h | 3 +- drivers/gpu/drm/i915/i915_vgpu.c | 2 +- 3 files changed, 81 insertions

[Intel-gfx] [PATCH v2 2/5] drm/i915: get ready of memory for pvmmio

Wilson Cc: Joonas Lahtinen Cc: He, Min Cc: Jiang, Fei Cc: Gong, Zhipeng Cc: Yuan, Hang Cc: Zhiyuan Lv Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_drv.c| 2 ++ drivers/gpu/drm/i915/i915_drv.h| 4 +++- drivers/gpu/drm/i915/i915_pvinfo.h | 24

[Intel-gfx] [PATCH v2 1/5] drm/i915: introduced pv capability for vgpu

module parameter. v1: addressed RFC comment to remove enable_pvmmio module parameter by pv capability check. v2: rebase Cc: Zhenyu Wang Cc: Zhi Wang Cc: Chris Wilson Cc: Joonas Lahtinen Cc: He, Min Cc: Jiang, Fei Cc: Gong, Zhipeng Cc: Yuan, Hang Cc: Zhiyuan Lv Signed-off-by: Xiaolin Zhang

[Intel-gfx] [PATCH v2 5/5] drm/i915: ppgtt update pvmmio optimization

-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_gem_gtt.c | 67 + drivers/gpu/drm/i915/i915_pvinfo.h | 3 ++ drivers/gpu/drm/i915/i915_vgpu.c| 3 +- 3 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b

[Intel-gfx] [v1 02/10] drm/i915: get ready of memory for pvmmio

this shared page without hypeviser trap cost for shared data exchagne via hyperviser read_gpa functionality. v1: addressed RFC comment to move both shared_page_lock and shared_page to i915_virtual_gpu structure v0: RFC Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_drv.c| 8

[Intel-gfx] [v1 10/10] drm/i915/gvt: GVTg support ppgtt pvmmio optimization

and removes the cost of write protection from the original shadow page mechansim. v1: rebase v0: RFC Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/gtt.c | 318 drivers/gpu/drm/i915/gvt/gtt.h | 9 + drivers/gpu/drm/i915/gvt/handlers.c | 13

[Intel-gfx] [v1 05/10] drm/i915: ppgtt update pvmmio optimization

of pvmmio optimization. v1: rebase v0: RFC Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_gem_gtt.c | 36 drivers/gpu/drm/i915/i915_pvinfo.h | 3 +++ drivers/gpu/drm/i915/i915_vgpu.c| 3 ++- 3 files changed, 41 insertions(+), 1 deletion

[Intel-gfx] [v1 07/10] drm/i915/gvt: GVTg read_shared_page implementation

GVTg implemented the read_shared_page functionality based on hypervisor_read_gpa(). the shared_page_gpa was passed from guest driver through PVINFO shared_page_gpa register. v1: rebase v0: RFC Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/gvt.h | 4 +++- drivers/gpu/drm/i915

[Intel-gfx] [v1 04/10] drm/i915: master irq pvmmio optimization

one trap when we disable master irq. Use PVMMIO_MASTER_IRQ to control this level of pvmmio optimization. v1: rebase v0: RFC Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_irq.c| 29 +++-- drivers/gpu/drm/i915/i915_pvinfo.h | 3 ++- drivers/gpu/drm/i915

[Intel-gfx] [v1 06/10] drm/i915/gvt: GVTg handle enable_pvmmio PVINFO register

implement enable_pvmmio PVINFO register handler in GVTg to control different level pvmmio optimization within guest. report VGT_CAPS_PVMMIO capability in pvinfo page for guest. v1: rebase v0: RFC Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/handlers.c | 10 ++ drivers/gpu

[Intel-gfx] [v1 09/10] drm/i915/gvt: GVTg support master irq pvmmio optimization

GVTg to check master irq status in the shared_page instead of register. v1: rebase v0: RFC Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/handlers.c | 4 drivers/gpu/drm/i915/gvt/interrupt.c | 17 + 2 files changed, 17 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] [v1 03/10] drm/i915: context submission pvmmio optimization

PVMMIO_ELSP_SUBMIT to control this level of pvmmio optimization. v1: rebase v0: RFC Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_vgpu.c | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 37 - 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers

[Intel-gfx] [v1 02/10] drm/i915: get ready of memory for pvmmio

this shared page without hypeviser trap cost for shared data exchagne via hyperviser read_gpa functionality. v1: addressed RFC comment to move both shared_page_lock and shared_page to i915_virtual_gpu structure v0: RFC Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_drv.c| 4

[Intel-gfx] [v1 08/10] drm/i915/gvt: GVTg support context submission pvmmio optimization

implemented context submission pvmmio optimizaiton with GVTg. GVTg to read context submission data (elsp_data) from the shared_page directly without trap cost to improve guest GPU peformrnace. v1: rebase v0: RFC Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/handlers.c | 12

[Intel-gfx] [v1 01/10] drm/i915: introduced pv capability for vgpu

enable_pvmmio module parameter by pv capability check. v0: RFC, introudced enable_pvmmio module parameter. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_drv.h| 11 +++ drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/i915_pvinfo.h | 17

[Intel-gfx] [v1 00/10] i915 pvmmio to improve GVTg performance

: addressed RFC review comments v0: RFC patch set Xiaolin Zhang (10): drm/i915: introduced pv capability for vgpu drm/i915: get ready of memory for pvmmio drm/i915: context submission pvmmio optimization drm/i915: master irq pvmmio optimization drm/i915: ppgtt update pvmmio optimization drm

[Intel-gfx] [RFC 09/10] drm/i915/gvt: GVTg support master irq pvmmio optimization

GVTg to check master irq status in the shared_page instead of register. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/handlers.c | 4 drivers/gpu/drm/i915/gvt/interrupt.c | 17 + 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [RFC 10/10] drm/i915/gvt: GVTg support ppgtt pvmmio optimization

and removes the cost of write protection from the original shadow page mechansim. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/gtt.c | 318 drivers/gpu/drm/i915/gvt/gtt.h | 9 + drivers/gpu/drm/i915/gvt/handlers.c | 13 +- 3 files changed

[Intel-gfx] [RFC 08/10] drm/i915/gvt: GVTg support context submission pvmmio optimization

implemented context submission pvmmio optimizaiton with GVTg. GVTg to read context submission data (elsp_data) from the shared_page directly without trap cost to improve guest GPU peformrnace. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/handlers.c | 12 1 file

[Intel-gfx] [RFC 03/10] drm/i915/gvt: context submission pvmmio optimization

PVMMIO_ELSP_SUBMIT to control this level of pvmmio optimization. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 37 - 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [RFC 06/10] drm/i915/gvt: GVTg handle enable_pvmmio PVINFO register

implement enable_pvmmio PVINFO register handler in GVTg to control different level pvmmio optimization within guest. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/handlers.c | 10 ++ drivers/gpu/drm/i915/gvt/vgpu.c | 6 ++ 2 files changed, 16 insertions(+) diff

[Intel-gfx] [RFC 04/10] drm/i915/gvt: master irq pvmmio optimization

one trap when we disable master irq. Use PVMMIO_MASTER_IRQ to control this level of pvmmio optimization. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_irq.c| 29 +++-- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/i915_pvinfo.h | 3

[Intel-gfx] [RFC 07/10] drm/i915/gvt: GVTg read_shared_page implementation

GVTg implemented the read_shared_page functionality based on hypervisor_read_gpa(). the shared_page_gpa was passed from guest driver through PVINFO shared_page_gpa register. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/gvt.h | 4 +++- drivers/gpu/drm/i915/gvt/handlers.c | 5

[Intel-gfx] [RFC 05/10] drm/i915/gvt: ppgtt update pvmmio optimization

of pvmmio optimization. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_gem_gtt.c | 36 drivers/gpu/drm/i915/i915_params.h | 3 ++- drivers/gpu/drm/i915/i915_pvinfo.h | 3 +++ 3 files changed, 41 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [RFC 02/10] drm/i915/gvt: get ready of memory for pvmmio

this shared page without hypeviser trap cost for shared data exchagne via hyperviser read_gpa functionality. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_drv.c| 5 + drivers/gpu/drm/i915/i915_drv.h| 3 +++ drivers/gpu/drm/i915/i915_pvinfo.h | 25

[Intel-gfx] [RFC 01/10] drm/i915/gvt: add module parameter enable_pvmmio

modification during runtime which would break the pvmmio internal logic. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_drv.h| 3 +++ drivers/gpu/drm/i915/i915_params.c | 4 drivers/gpu/drm/i915/i915_params.h | 3 ++- drivers/gpu/drm/i915/i915_pvinfo.h | 16

[Intel-gfx] [RFC 00/10] i915 pvmmio to improve GVTg performance

. Xiaolin Zhang (10): drm/i915/gvt: add module parameter enable_pvmmio drm/i915/gvt: get ready of memory for pvmmio drm/i915/gvt: context submission pvmmio optimization drm/i915/gvt: master irq pvmmio optimization drm/i915/gvt: ppgtt update pvmmio optimization drm/i915/gvt: GVTg handle

[Intel-gfx] [PATCH] drm/i915: Disable display crc feature for vgpu

for vgpu, it doesn't support display crc feature. this patch is to skip pipe crc create and report ENODEV during set_crc_source. igt display crc relatated cases will be failed instead of dead sleep. Signed-off-by: Xiaolin Zhang <xiaolin.zh...@intel.com> --- drivers/gpu/drm/i915/intel_pipe

[Intel-gfx] [PATCH v1] drm/i915: Enhanced for initialize partially filled pagetables

, var 0x6, len 1” when create linux guest. Signed-off-by: Xiaolin Zhang <xiaolin.zh...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 731ce2

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