Re: [Intel-gfx] [PATCH] drm/i915: Use ktime on wait_for

On 4/20/2018 4:09 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2018-04-20 11:23:50) On 4/20/2018 3:24 PM, Mika Kuoppala wrote: We use jiffies to determine when wait expires. However Imre did find out that jiffies can and will do a >1 increments on certain situations [1]. W

Re: [Intel-gfx] [PATCH] drm/i915: Use ktime on wait_for

On 4/20/2018 3:24 PM, Mika Kuoppala wrote: We use jiffies to determine when wait expires. However Imre did find out that jiffies can and will do a >1 increments on certain situations [1]. When this happens in a wait_for loop, we return timeout errorneously much earlier than what the real

Re: [Intel-gfx] [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

on top of the WA refactoring Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Praveen Paneri <praveen.pan...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam..

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

On 4/9/2018 9:02 PM, Michal Wajdeczko wrote: On Mon, 09 Apr 2018 17:09:18 +0200, Patchwork wrote: == Series Details == Series: series starting with [v8,01/12] drm/i915: Park before resetting the submission backend URL   :

Re: [Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote: As we always call intel_uc_sanitize after every call to intel_uc_fini_hw we may drop redundant call and sanitize uC from the fini_hw function. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sa

Re: [Intel-gfx] [PATCH v8 05/12] drm/i915: Add i915_gem_fini_hw to i915_gem_suspend

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote: By calling i915_gem_init_hw in i915_gem_resume and not calling i915_gem_fini_hw in i915_gem_suspend we introduced asymmetry in init_hw/fini_hw calls. Let's fix that. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun

Re: [Intel-gfx] [PATCH v8 04/12] drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw

. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/

Re: [Intel-gfx] [PATCH v8 03/12] drm/i915: Move i915_gem_fini to i915_gem.c

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote: We should keep i915_gem_init/fini functions together for easier tracking of their symmetry. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chr

Re: [Intel-gfx] [PATCH] drm/i915: Park before resetting the submission backend

l.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c| 15 ++

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Park before resetting the submission backend

Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 11 +++ drivers/gpu/drm/i9

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v6,01/12] drm/i915: Correctly handle error path in i915_gem_init_hw

On 4/5/2018 6:03 AM, Patchwork wrote: == Series Details == Series: series starting with [v6,01/12] drm/i915: Correctly handle error path in i915_gem_init_hw URL : https://patchwork.freedesktop.org/series/41159/ State : failure == Summary == Possible new issues: Test gem_eio:

Re: [Intel-gfx] [PATCH v12 05/17] drm/i915/guc/slpc: Add SLPC communication interfaces

On 3/30/2018 7:07 PM, Michal Wajdeczko wrote: On Fri, 30 Mar 2018 10:31:50 +0200, Sagar Arun Kamble <sagar.a.kam...@intel.com> wrote: diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h index 66c76fe..81250c0 100644 --- a/drivers/gpu/dr

Re: [Intel-gfx] [PATCH v12 01/17] drm/i915/guc/slpc: Add SLPC control to enable_guc modparam

Thanks for the review. Will update with all suggestions in the next rev. On 3/30/2018 6:07 PM, Michal Wajdeczko wrote: On Fri, 30 Mar 2018 10:31:46 +0200, Sagar Arun Kamble <sagar.a.kam...@intel.com> wrote: From: Tom O'Rourke <Tom.O'rou...@intel.com> GuC is currentl

[Intel-gfx] [PATCH v12 16/17] drm/i915/guc/slpc: Add SLPC banner to RPS debugfs interfaces

Sagar) v4: idle_freq, boost_freq are also not used with SLPC. v5: Added SLPC banner to i915_rps_boost_info and keep printing driver internal values. (Chris) v6: Commit message update. v7: Rebase. v8: Rebase. Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: S

[Intel-gfx] [PATCH v12 12/17] drm/i915/guc/slpc: Add enable/disable controls for SLPC tasks

. Moved functions to intel_slpc.c. RPM Get/Put added before setting parameters and sending RESET event explicitly. (Sagar) v7: Rebase. Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris

[Intel-gfx] [PATCH v12 14/17] drm/i915/guc/slpc: Add debugfs support to read/write/revert the parameters

l_guc_slpc_enabled instead of accessing status variable. Optimized token parsing. (Michal Wajdeczko) s/i915_slpc_paramlist/i915_guc_slpc_params and s/i915_slpc_param_ctl/i915_guc_slpc_param_ctl v3: Rebase. Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson &

[Intel-gfx] [PATCH v12 11/17] drm/i915/guc/slpc: Add support for sysfs min/max frequency control

->pm.rps structure. v8: Updated returns from gt_min_freq_mhz_store and gt_max_freq_mhz_store and i915_min_freq_set and i915_max_freq_set. v9: Rebase. Debugfs interfaces will be removed hence only updated sysfs. Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <

[Intel-gfx] [PATCH v12 15/17] drm/i915/guc/slpc: Add i915_guc_slpc_info to debugfs

intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: Michal Wajdeczko <michal.wajdec

[Intel-gfx] [PATCH v12 17/17] HAX: drm/i915/guc: Enable GuC

Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 2484925..dd2de06 100644 --- a/drivers/gpu/dr

[Intel-gfx] [PATCH v12 13/17] drm/i915/debugfs: Create generic string tokenize function and update CRC control parsing

parsing that was misplaced at tokenize function. v2: Moved buffer_tokenize to i915_debugfs.c (Michal Wajdeczko) Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Tomeu Vizoso <tomeu.viz...@collabora.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com>

[Intel-gfx] [PATCH v12 09/17] drm/i915/guc/slpc: Reset SLPC on engine reset with flag TDR_OCCURRED

. Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.co

[Intel-gfx] [PATCH v12 07/17] drm/i915/guc/slpc: Send RESET event to restart/enable SLPC tasks

-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sujaritha

[Intel-gfx] [PATCH v12 10/17] drm/i915/guc/slpc: Add parameter set/unset/get, task control/status functions

-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: M

[Intel-gfx] [PATCH v12 05/17] drm/i915/guc/slpc: Add SLPC communication interfaces

they are used. v10: Rebase. Prepared separate header for SLPC firmware interface. Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti..

[Intel-gfx] [PATCH v12 08/17] drm/i915/guc/slpc: Send SHUTDOWN event to stop SLPC tasks

k post disabling to wait for 20us. (Sagar) v9: Updated the status check wait time to 5ms for safe margin as it is handled similar to reset by SLPC. s/slpc_disabled/slpc_stopped v10: Rebase. Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.k

[Intel-gfx] [PATCH v12 01/17] drm/i915/guc/slpc: Add SLPC control to enable_guc modparam

ulo.r.zan...@intel.com> Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <rados

[Intel-gfx] [PATCH v12 03/17] drm/i915/guc/slpc: Lay out SLPC init/enable/disable/fini helpers

c_initialized and guc_slpc_enabled to track state of SLPC initialization and enabling. v12: s/guc_slpc_cleanup/guc_slpc_fini. Updated SLPC flows w.r.t uC flows. Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson

[Intel-gfx] [PATCH v12 02/17] drm/i915/guc/slpc: Disable host RPS

min/max frequency limits. Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: Michal Wajdeczko <

[Intel-gfx] [PATCH v12 06/17] drm/i915/guc/slpc: Allocate/initialize/release SLPC shared data

: Enabling Balancer task in SLPC. v10: Rebase. v11: Rebase. Added lock specific to SLPC. Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti..

[Intel-gfx] [PATCH v12 04/17] drm/i915/guc/slpc: Enable SLPC in GuC load control params

m> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: Michal Wajdeczko <michal.wajdec

[Intel-gfx] [PATCH v12 00/17] Add support for GuC-based SLPC

car.ma...@intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com> Cc: Jeff McGee <jeff.mc...@intel.com> Tested-by: Radoslaw Szwichtenberg <radoslaw.szwich

Re: [Intel-gfx] [PATCH v5 8/8] HAX: Enable GuC for CI

On 3/28/2018 2:05 AM, Michal Wajdeczko wrote: v2: except running with HYPERVISOR Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_uc.c| 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff

Re: [Intel-gfx] [PATCH v5 5/8] drm/i915/uc: Use correct error code for GuC initialization failure

;ch...@chris-wilson.co.uk> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> void intel_uc_fini_hw(struct drm_i915_private *i915) { + struct intel_guc *

Re: [Intel-gfx] [PATCH v5 4/8] drm/i915/uc: Fully sanitize uC in uc_fini_hw

-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/intel_uc.c | 14 ++ 1 fi

Re: [Intel-gfx] [PATCH v5 3/8] drm/i915/guc: Restore symmetric doorbell cleanup

paths, we can restore symmetry in doorbell cleanup, as GuC should be still active by now. Suggested-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Winiarski <

Re: [Intel-gfx] [PATCH v5 2/8] drm/i915/uc: Disable GuC submission during sanitize

On 3/28/2018 2:05 AM, Michal Wajdeczko wrote: We should not leave GuC submission enabled after sanitize, as we are going to reset all GuC/HuC hardware. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson

Re: [Intel-gfx] [PATCH v5 01/12] drm/i915/guc: Add documentation for MMIO based communication

eraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Kelvin Gardiner <kelvin.gardi...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> #1 --- } diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers

Re: [Intel-gfx] [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw

-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> We should drop call to uc_fini_hw from gem_fini as part of this patch as GuC won't be available then. --- drivers/gpu/drm/i9

Re: [Intel-gfx] [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize

On 3/23/2018 8:44 PM, Michal Wajdeczko wrote: We should not leave GuC submission enabled after sanitize, as we are going to reset all GuC/HuC hardware. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson

Re: [Intel-gfx] [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw

On 3/23/2018 8:44 PM, Michal Wajdeczko wrote: In function gem_init_hw() we are calling uc_init_hw() but in case of error later in function, we missed to call matching uc_fini_hw() Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@inte

Re: [Intel-gfx] [CI 1/2] drm/i915/guc: Fix null pointer dereference when GuC FW is not available

g <radoslaw.szwichtenb...@intel.com> Cc: Michał Winiarski <michal.winiar...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Jackie Li <yaodong...@int

Re: [Intel-gfx] [PATCH v3] drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams

: - Updated GuC Address Space kernel-doc based on Michal's suggestion Signed-off-by: Jackie Li <yaodong...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --

Re: [Intel-gfx] [PATCH] drm/i915/guc: Unify parameters of public CT functions

On 3/20/2018 6:30 PM, Michal Wajdeczko wrote: On Tue, 20 Mar 2018 08:24:14 +0100, Sagar Arun Kamble <sagar.a.kam...@intel.com> wrote: On 3/19/2018 8:58 PM, Michal Wajdeczko wrote: There is no need to mix parameter types in public CT functions as we can always accept intel_guc_ct.

Re: [Intel-gfx] [PATCH] drm/i915/guc: Unify parameters of public CT functions

On 3/19/2018 8:58 PM, Michal Wajdeczko wrote: There is no need to mix parameter types in public CT functions as we can always accept intel_guc_ct. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson

Re: [Intel-gfx] [PATCH 1/8] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

to ICL+ (Sagar) Cc: Paulo Zanoni <paulo.r.zan...@intel.com> Cc: Vinay Belgaumkar <vinay.belgaum...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo

Re: [Intel-gfx] [PATCH v3 10/13] drm/i915/guc: Allow user to control default GuC logging

iele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> (v2) --- drivers/gpu/drm/i915/intel_guc.c | 24 +++- driver

Re: [Intel-gfx] [PATCH v3 01/13] drm/i915/guc: Keep GuC interrupts enabled when using GuC

iele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> (v2) Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> ---

Re: [Intel-gfx] [PATCH 36/36] drm/i915: Support per-context user requests for GPU frequency control

intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Praveen Paneri <praveen.pan...@intel.com> Cc: Sagar A Kamble <sagar.a.kam...@intel.com> Change looks good to me. I have one query below. diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/d

Re: [Intel-gfx] [PATCH 35/36] drm/i915: Remove unwarranted clamping for hsw/bdw

On 3/14/2018 3:07 PM, Chris Wilson wrote: We always start off at an "efficient frequency" and can let the system autotune from there, eliminating the need to clamp the available range. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kam

Re: [Intel-gfx] [PATCH 33/36] drm/i915: Pull IPS into RPS

". It seems IPS and RPS merge is happening in next patch. Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h| 37 - drivers/gpu/drm/i915/i915_irq.c| 21 +- drivers/gpu/drm/i

Re: [Intel-gfx] [PATCH 32/36] drm/i915: Rename rps min/max frequencies

On 3/14/2018 3:07 PM, Chris Wilson wrote: In preparation for more layers of limits, rename the existing limits to hw and user. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/i915_deb

Re: [Intel-gfx] [PATCH 31/36] drm/i915: Don't fiddle with rps/rc6 across GPU reset

On 3/14/2018 3:07 PM, Chris Wilson wrote: Resetting the GPU doesn't affect the RPS/RC6 state, so we can stop forcibly reloading the registers. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Changes look good to me. Review

Re: [Intel-gfx] [PATCH] drm/i915/guc: Handle GuC log flush event in dedicated function

iarski <michal.winiar...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Ordering of the declarations is an issue but not c

Re: [Intel-gfx] [PATCH 30/36] drm/i915: Refactor frequency bounds computation

On 3/14/2018 3:07 PM, Chris Wilson wrote: When choosing the initial frequency in intel_gt_pm_busy() we also need to calculate the current min/max bounds. As this calculation is going to become more complex with the intersection of several different limits, refactor it to a common function. The

Re: [Intel-gfx] [PATCH 29/36] drm/i915: Simplify rc6/rps enabling

On 3/14/2018 3:07 PM, Chris Wilson wrote: As we know that whenever the GT is awake, rc6 and rps are enabled (if available), then we can remove the individual tracking and enabling to the gen6_rps_busy/gen6_rps_idle() (now called intel_gt_pm_busy and intel_gt_pm_idle) entry points.

Re: [Intel-gfx] [PATCH 28/36] drm/i915: Enabling rc6 and rps have different requirements, so separate them

On 3/14/2018 3:07 PM, Chris Wilson wrote: On Ironlake, we are required to not enable rc6 until the GPU is loaded with a valid context; after that point it can start to use a powersaving context for rc6. This seems a reasonable requirement to impose on all generations as we are already priming

Re: [Intel-gfx] [PATCH 27/36] drm/i915: Split control of rps and rc6

On 3/16/2018 2:22 PM, Sagar Arun Kamble wrote: On 3/14/2018 3:07 PM, Chris Wilson wrote: Allow ourselves to individually toggle rps or rc6. This will be used later when we want to enable rps/rc6 at different phases during the device bring up. Whilst here, convert the intel_

Re: [Intel-gfx] [PATCH 27/36] drm/i915: Split control of rps and rc6

On 3/14/2018 3:07 PM, Chris Wilson wrote: Allow ourselves to individually toggle rps or rc6. This will be used later when we want to enable rps/rc6 at different phases during the device bring up. Whilst here, convert the intel_$verb_gt_powersave over to intel_gt_pm_$verb scheme.

Re: [Intel-gfx] [PATCH 26/36] drm/i915: Reorder GT interface code

On 3/14/2018 3:07 PM, Chris Wilson wrote: Try to order the intel_gt_pm code to match the order it is used: init enable disable cleanup Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@

Re: [Intel-gfx] [PATCH 25/36] drm/i915: Remove defunct intel_suspend_gt_powersave()

on idling), remove the defunct function. References: b7137e0cf1e5 ("drm/i915: Defer enabling rc6 til after we submit the first batch/context") Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers

Re: [Intel-gfx] [PATCH 24/36] drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info

viewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 6 ++ drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_gt_pm.c | 20 4 files

Re: [Intel-gfx] [PATCH 23/36] drm/i915: Move all the RPS irq handlers to intel_gt_pm

As per discussion with Michal w.r.t moving GuC interrupt handling functions to intel_guc|_interrupt.c, I agreed that since most functions (gen9_*_guc_interrupts) are touching dev_priv level interrupt registers we should keep them  in i915_irq.c Handler for rps can be created and be in gt_pm.c

Re: [Intel-gfx] [PATCH 22/36] drm/i915: Move rps worker to intel_gt_pm.c

are coordinated. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h| 1 - drivers/gpu/drm/i915/i915_irq.c| 141 drivers/gpu/drm/i915/i915_sy

Re: [Intel-gfx] [PATCH 21/36] drm/i915: Split GT powermanagement functions to intel_gt_pm.c

OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + Need SPDX License identifier here. Thanks for many checkpatch/comment fixes. Few more are still flagged. Otherwise change looks good to me. Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> +#ifndef __INTEL_GT_PM_H__ +#define __INTEL_GT

Re: [Intel-gfx] [PATCH 15/36] drm/i915: Mark up Ironlake ips with rpm wakerefs

i915_mch_val() called from i915_emon_status debugfs is not protected under rpm_get and mchdev_lock. Can that also be updated as part of this patch. Thanks, Sagar On 3/14/2018 3:07 PM, Chris Wilson wrote: Currently Ironlake operates under the assumption that rpm awake (and its error checking

Re: [Intel-gfx] [PATCH 15/36] drm/i915: Mark up Ironlake ips with rpm wakerefs

On 3/14/2018 3:07 PM, Chris Wilson wrote: Currently Ironlake operates under the assumption that rpm awake (and its error checking is disabled). As such, we have missed a few places where we access registers without taking the rpm wakeref and thus trigger warnings. intel_ips being one culprit.

Re: [Intel-gfx] [PATCH 12/36] drm/i915: Merge sbi read/write into a single accessor

On 3/14/2018 3:07 PM, Chris Wilson wrote: Since intel_sideband_read and intel_sideband_write differ by only a couple of lines (depending on whether we feed the value in or out), merge the two into a single common accessor. Signed-off-by: Chris Wilson -u32

Re: [Intel-gfx] [PATCH 10/36] drm/i915: Replace pcu_lock with sb_lock

out_us, int slow_timeout_ms) +static int __sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, +u32 mbox, u32 val, +int fast_timeout_us, + int sl

Re: [Intel-gfx] [PATCH 08/36] drm/i915: Reduce RPS update frequency on Valleyview/Cherryview

On 3/14/2018 3:07 PM, Chris Wilson wrote: Valleyview and Cherryview update the GPU frequency via the punit, which is very expensive as we have to ensure the cores do not sleep during the comms. But the patch 5 applies this workaround to only VLV. If we perform frequent RPS evaluations, the

Re: [Intel-gfx] [PATCH v2] drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams

l.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/intel_guc.c | 52 -- drivers/gpu/drm/i915/intel_wopcm.c | 44 +--- 2 files chang

Re: [Intel-gfx] [PATCH 20/36] drm/i915: Remove obsolete min/max freq setters from debugfs

On 3/14/2018 3:07 PM, Chris Wilson wrote: A more complete, and more importantly stable, interface for controlling the RPS frequency range is available in sysfs, obsoleting the unstable debugfs. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sa

Re: [Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

On 3/14/2018 2:33 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2018-03-14 08:15:15) On 3/13/2018 7:28 PM, Chris Wilson wrote: Exercise some new API that allows applications to request that individual contexts are executed within a desired frequency range. v2: Split single/continuous

Re: [Intel-gfx] [PATCH v3 1/1] drm/i915/uc: Make GuC/HuC fw fetch and loading functions/file structure symmetric

On 3/2/2018 3:44 PM, Sagar Arun Kamble wrote: On 3/2/2018 2:01 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2018-03-01 16:45:45) +static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma) +{ +   struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw

Re: [Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

transition beyond randomly chosen frequencies as well as up/down ramps. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Praveen Paneri <praveen.pan...@intel.com> Cc: Sagar A Kamble <sagar.a.kam...@intel.com> Cc: Antonio Argenziano <antonio.argenzi...@intel.com&

Re: [Intel-gfx] [PATCH v3 3/4] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c

iption is not updated for sanitize_options_early and intel_uc_init_mmio. With that: Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/intel_uc.c | 122 1 file changed, 61 insertions(+), 61 deletions(-) diff --git a/dri

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/uc: Use helper functions to detect fw load status

On 3/13/2018 7:24 PM, Michal Wajdeczko wrote: We don't have to check load status values. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun K

Re: [Intel-gfx] [PATCH v3 1/4] drm/i915/uc: Use correct error code for GuC initialization failure

hris-wilson.co.uk> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c| 17 ++--- drivers/gpu/drm/i915/intel_guc.h |

Re: [Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

after each invalid request v4: Check the frequencies reported by the kernel across the entire range. v5: Rewrite sandwich to create a sandwich between multiple concurrent engines. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Praveen Paneri <praveen.pan...@intel.com> Cc: Sa

Re: [Intel-gfx] [PATCH 2/3] drm/i915/uc: Sanitize uC together with GEM

Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c| 2 ++ drivers/gpu/drm/i915/intel_guc.h | 6

Re: [Intel-gfx] [PATCH v2 14/15] drm/i915/guc: Default to non-verbose GuC logging

Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> (v1) Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.c

Re: [Intel-gfx] [PATCH v2 12/15] drm/i915/guc: Don't print out relay statistics when relay is disabled

Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> --- drivers/gpu

Re: [Intel-gfx] [PATCH v2 10/15] drm/i915/guc: Get rid of GuC log runtime

...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Some might want other stats too as part of relay since we print them when relay is enabled. But th

Re: [Intel-gfx] [PATCH v2 08/15] drm/i915/guc: Split relay control and GuC log level

Use struct_mutex rather than runtime.lock for set_log_level Signed-off-by: Michał Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.c

Re: [Intel-gfx] [PATCH v2 07/15] drm/i915/guc: Flush directly in log unregister

-by: Michał Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Reviewed-by:

Re: [Intel-gfx] [PATCH v2 06/15] drm/i915/guc: Merge log relay file and channel creation

. v2: Remove obsoleted comments (Sagar) Signed-off-by: Michał Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal

Re: [Intel-gfx] [PATCH v2 05/15] drm/i915/guc: Log runtime should consist of both mapping and relay

...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- driver

Re: [Intel-gfx] [PATCH v2 03/15] drm/i915/guc: Move GuC notification handling to separate function

; Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Signed-off-by: Michał Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Saga

Re: [Intel-gfx] [PATCH v2 02/15] drm/i915/guc: Create common entry points for log register/unregister

;michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 6 +- drivers/gpu/drm/i915/intel_guc_log.c | 156 ++- drivers/g

Re: [Intel-gfx] [PATCH v2 01/15] drm/i915/guc: Tidy guc_log_control

incorrect input validaction (Sagar) Signed-off-by: Michał Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble &

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/uc: Start preparing GuC/HuC for reset

iele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> --- drivers/gpu/drm/i915/i915_

Re: [Intel-gfx] [PATCH 14/15] drm/i915/guc: Default to non-verbose GuC logging

raolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/intel_uc.c | 2 +- 1 file changed, 1 ins

Re: [Intel-gfx] [PATCH 12/15] drm/i915/guc: Don't print out relay statistics when relay is disabled

and tidy the debugfs formatting. Signed-off-by: Michał Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <

Re: [Intel-gfx] [PATCH 13/15] drm/i915/guc: Allow user to control default GuC logging

1 Non-verbose log 2-5 Verbose log Signed-off-by: Michał Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal

Re: [Intel-gfx] [PATCH 12/15] drm/i915/guc: Don't print out relay statistics when relay is disabled

formatting. Signed-off-by: Michał Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel

Re: [Intel-gfx] [PATCH 10/15] drm/i915/guc: Get rid of GuC log runtime

raolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> --- drivers/gpu/drm/i915/intel_guc.c | 14 drivers/gpu/drm/i915/intel_guc_log.c | 68 ++-- driver

Re: [Intel-gfx] [PATCH 11/15] drm/i915/guc: Always print log stats in i915_guc_info when using GuC

iele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 15 +--

Re: [Intel-gfx] [PATCH 09/15] drm/i915/guc: Move check for fast memcpy_wc to relay creation

gt; Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> ---

Re: [Intel-gfx] [PATCH 08/15] drm/i915/guc: Split relay control and GuC log level

iele.ceraolospu...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 56 ++ drivers/gpu/drm/i915/i915_drv.c | 2 - drivers/gpu

Re: [Intel-gfx] [PATCH 05/15] drm/i915/guc: Log runtime should consist of both mapping and relay

On 3/5/2018 7:44 PM, Michał Winiarski wrote: On Mon, Mar 05, 2018 at 04:01:18PM +0530, Sagar Arun Kamble wrote: On 2/27/2018 6:22 PM, Michał Winiarski wrote: Currently, we're treating relay and mapping of GuC log as a separate concepts. We're also using inconsistent locking, sometimes using

Re: [Intel-gfx] [PATCH 02/15] drm/i915/guc: Create common entry points for log register/unregister

On 3/5/2018 7:08 PM, Michał Winiarski wrote: On Mon, Mar 05, 2018 at 12:39:58PM +0530, Sagar Arun Kamble wrote: Overall change looks good. Could you please clarify on below: intel_uc_log_register|unregister are removed in patch later in the series. Should we just stay with inner functions

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