[Intel-gfx] [CI] drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw

2019-11-29 Thread Chris Wilson
After much hair pulling, resort to preallocating the ppGTT entries on init to circumvent the apparent lack of PD invalidate following the write to PP_DCLV upon switching mm between contexts (and here the same context after binding new objects). However, the details of that PP_DCLV invalidate are

[Intel-gfx] [CI] drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw

2019-11-29 Thread Chris Wilson
After much hair pulling, resort to preallocating the ppGTT entries on init to circumvent the apparent lack of PD invalidate following the write to PP_DCLV upon switching mm between contexts (and here the same context after binding new objects). However, the details of that PP_DCLV invalidate are

[Intel-gfx] [CI] drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw

2019-11-29 Thread Chris Wilson
After much hair pulling, resort to preallocating the ppGTT entries on init to circumvent the apparent lack of PD invalidate following the write to PP_DCLV upon switching mm between contexts (and here the same context after binding new objects). However, the details of that PP_DCLV invalidate are

[Intel-gfx] [CI] drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw

2019-11-28 Thread Chris Wilson
After much hair pulling, resort to preallocating the ppGTT entries on init to circumvent the apparent lack of PD invalidate following the write to PP_DCLV upon switching mm between contexts (and here the same context after binding new objects). However, the details of that PP_DCLV invalidate are