Re: [Intel-gfx] [PATCH] dri: Do not tile stencil buffer

2011-07-18 Thread Kenneth Graunke
On 07/18/2011 05:08 PM, Chad Versace wrote: > Until now, the stencil buffer was allocated as a Y tiled buffer, because > in several locations the PRM states that it is. However, it is actually > W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section > 4.5.2.1 W-Major Format: > W-Ma

[Intel-gfx] [PATCH] dri: Do not tile stencil buffer

2011-07-18 Thread Chad Versace
Until now, the stencil buffer was allocated as a Y tiled buffer, because in several locations the PRM states that it is. However, it is actually W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Format: W-Major Tile Format is used for separate stencil. The GTT

Re: [Intel-gfx] [PATCH] dri: Do not tile stencil buffer

2011-07-18 Thread Paul Menzel
Am Montag, den 18.07.2011, 00:55 -0700 schrieb Chad Versace: > Until now, the stencil buffer was allocated as a Y tiled buffer, because > in several locations the PRM states that it is. However, it is actually > W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section > 4.5.2.1 W-Major F

[Intel-gfx] [PATCH] dri: Do not tile stencil buffer

2011-07-18 Thread Chad Versace
Until now, the stencil buffer was allocated as a Y tiled buffer, because in several locations the PRM states that it is. However, it is actually W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Format: W-Major Tile Format is used for separate stencil. The GTT