Re: [Intel-gfx] [PATCH] drm/i915/glk, cnl: Implement WaDisableScalarClockGating

2017-09-29 Thread Imre Deak
On Thu, Sep 28, 2017 at 01:18:30PM -0700, Rodrigo Vivi wrote: > On Thu, Sep 28, 2017 at 07:54:36PM +, Imre Deak wrote: > > On GLK and CNL enabling a pipe with its pipe scaler enabled will result > > in a FIFO underrun. This happens only once after driver loading or > > system/runtime resume,

Re: [Intel-gfx] [PATCH] drm/i915/glk, cnl: Implement WaDisableScalarClockGating

2017-09-28 Thread Rodrigo Vivi
On Thu, Sep 28, 2017 at 07:54:36PM +, Imre Deak wrote: > On GLK and CNL enabling a pipe with its pipe scaler enabled will result > in a FIFO underrun. This happens only once after driver loading or > system/runtime resume, more specifically after power well 1 gets > enabled; subsequent

[Intel-gfx] [PATCH] drm/i915/glk, cnl: Implement WaDisableScalarClockGating

2017-09-28 Thread Imre Deak
On GLK and CNL enabling a pipe with its pipe scaler enabled will result in a FIFO underrun. This happens only once after driver loading or system/runtime resume, more specifically after power well 1 gets enabled; subsequent modesets seem to be free of underruns. The BSpec workaround for this is to