Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-06 Thread Jani Nikula
On Wed, 05 Apr 2017, Madhav Chauhan wrote: > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz. > Practically we can achive only 99% of these cdclk values (HW team > checking on this). So cdclk should be calculated for the given pixclk as > per that

[Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-05 Thread Madhav Chauhan
As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz. Practically we can achive only 99% of these cdclk values (HW team checking on this). So cdclk should be calculated for the given pixclk as per that otherwise it may lead to screen corruption, explained below: 1. For DSI AUO

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Chauhan, Madhav
> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Tuesday, April 4, 2017 6:26 PM > To: Chauhan, Madhav > Cc: Nikula, Jani ; Ander Conselvan De Oliveira > ;

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Ville Syrjälä
On Tue, Apr 04, 2017 at 11:53:42AM +, Chauhan, Madhav wrote: > > -Original Message- > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > > Sent: Tuesday, April 4, 2017 5:09 PM > > To: Chauhan, Madhav > > Cc: Nikula, Jani ;

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Chauhan, Madhav
> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Tuesday, April 4, 2017 5:09 PM > To: Chauhan, Madhav > Cc: Nikula, Jani ; Ander Conselvan De Oliveira > ;

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Chauhan, Madhav
> -Original Message- > From: Ander Conselvan De Oliveira [mailto:conselv...@gmail.com] > Sent: Tuesday, April 4, 2017 4:13 PM > To: Chauhan, Madhav ; Nikula, Jani > ; intel-gfx@lists.freedesktop.org > Cc: Ville Syrjälä

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Ville Syrjälä
On Tue, Apr 04, 2017 at 10:27:57AM +, Chauhan, Madhav wrote: > > -Original Message- > > From: Nikula, Jani > > Sent: Tuesday, April 4, 2017 3:48 PM > > To: Ander Conselvan De Oliveira ; intel- > > g...@lists.freedesktop.org > > Cc: Chauhan, Madhav

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Ander Conselvan De Oliveira
On Tue, 2017-04-04 at 10:27 +, Chauhan, Madhav wrote: > > -Original Message- > > From: Nikula, Jani > > Sent: Tuesday, April 4, 2017 3:48 PM > > To: Ander Conselvan De Oliveira ; intel- > > g...@lists.freedesktop.org > > Cc: Chauhan, Madhav

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Chauhan, Madhav
> -Original Message- > From: Nikula, Jani > Sent: Tuesday, April 4, 2017 3:48 PM > To: Ander Conselvan De Oliveira ; intel- > g...@lists.freedesktop.org > Cc: Chauhan, Madhav ; Ville Syrjälä > > Subject: Re:

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Jani Nikula
On Tue, 04 Apr 2017, Ander Conselvan De Oliveira wrote: > On Tue, 2017-04-04 at 11:40 +0300, Jani Nikula wrote: >> On Tue, 04 Apr 2017, Ander Conselvan De Oliveira >> wrote: >> > On Tue, 2017-04-04 at 11:15 +0300, Jani Nikula wrote: >> > > From:

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Ander Conselvan De Oliveira
On Tue, 2017-04-04 at 11:40 +0300, Jani Nikula wrote: > On Tue, 04 Apr 2017, Ander Conselvan De Oliveira wrote: > > On Tue, 2017-04-04 at 11:15 +0300, Jani Nikula wrote: > > > From: Madhav Chauhan > > > > > > As per BSPEC, valid cdclk values for

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Jani Nikula
On Tue, 04 Apr 2017, Ander Conselvan De Oliveira wrote: > On Tue, 2017-04-04 at 11:15 +0300, Jani Nikula wrote: >> From: Madhav Chauhan >> >> As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz. >> Practically we can achive only

Re: [Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Ander Conselvan De Oliveira
On Tue, 2017-04-04 at 11:15 +0300, Jani Nikula wrote: > From: Madhav Chauhan > > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz. > Practically we can achive only 99% of these cdclk values (HW team > checking on this). So cdclk should be calculated

[Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

2017-04-04 Thread Jani Nikula
From: Madhav Chauhan As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz. Practically we can achive only 99% of these cdclk values (HW team checking on this). So cdclk should be calculated for the given pixclk as per that otherwise it may lead to screen