Re: [Intel-gfx] [PATCH] drm/i915/guc: Update guc shim control programming on newer platforms

2022-01-25 Thread Belgaumkar, Vinay
On 1/20/2022 2:24 PM, Daniele Ceraolo Spurio wrote: Starting from xehpsdv, bit 0 of of the GuC shim control register has been repurposed, while bit 2 is now reserved, so we need to avoid setting those for their old meaning on newer platforms. Cc: Vinay Belgaumkar Cc: Stuart Summers

[Intel-gfx] [PATCH] drm/i915/guc: Update guc shim control programming on newer platforms

2022-01-20 Thread Daniele Ceraolo Spurio
Starting from xehpsdv, bit 0 of of the GuC shim control register has been repurposed, while bit 2 is now reserved, so we need to avoid setting those for their old meaning on newer platforms. Cc: Vinay Belgaumkar Cc: Stuart Summers Signed-off-by: Daniele Ceraolo Spurio ---